CN102446793A - Method for controlling pollution in manufacturing of semiconductor wafer - Google Patents
Method for controlling pollution in manufacturing of semiconductor wafer Download PDFInfo
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- CN102446793A CN102446793A CN2011103562882A CN201110356288A CN102446793A CN 102446793 A CN102446793 A CN 102446793A CN 2011103562882 A CN2011103562882 A CN 2011103562882A CN 201110356288 A CN201110356288 A CN 201110356288A CN 102446793 A CN102446793 A CN 102446793A
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Abstract
The invention relates to the field of semiconductor manufacturing, in particular to a method for controlling pollution in manufacturing of a semiconductor wafer. In the method for controlling pollution in manufacturing of the semiconductor wafer, a pollution sign is arranged on a silicon batch, the pollution sign allowing passing through is set on a machine, a mode by determining whether the pollution sign carried by the silicon batch is the pollution sign allowed to pass through by the machine is utilized for control, the pollution sign does not need to be scheduled for grades, and maintenance force can not be continually increased due to increase of pollution grades, therefore, easy control of cross pollution of a production line is realized, and pollution of low pollution grade silicon batch per se due to entering the high pollution grade machine can be effectively prevented.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacturing field thereof, relate in particular to groundwater pollution control in a kind of semiconductor crystal wafer manufacturing.
Background technology
In integrated circuit manufacturing process, in case after having the silicon chip of band pollution index to get into key processing equipment, will have a strong impact on the equipment atmosphere of this critical process; Especially in the subsequent job that does not stop, this atmosphere will have a strong impact on follow-up large batch of silicon chip, promptly in concrete manufacturing process; Some harmful elements of introducing in the device can directly cause this device reliability variation, even cause and can not work; What is more; The equipment of critical process directly can cause equipment to utilize again, thereby the running of factory is produced fatefulue influence after polluted by this; So how to prevent above-mentioned cross pollution, be when previous very important problem to avoid it in integrated circuit manufacturing process, to cause damage.
In the continuous process of development forward of processing procedure ability; Copper wiring is owing to its low-resistance, high various superiority such as deelectric transferred are widely used in 0.13nm and the following semiconductor fabrication process thereof; But based on the production capacity of production line and considering of cost; Need the shared production line of copper wiring and aluminum manufacturing procedure, pollute control this moment and become even more important.
Fig. 1 adopts conventional class of pollution mode to pollute the schematic flow sheet of control in the background technology of the present invention.Because the pollution of copper is more serious for the influence of device performance; Like short-channel effect enhancing etc.; And conventional pollution control is normally through the definition class of pollution; The silicon chip of the low class of pollution is criticized in the board that (Lot) can get into the high pollution grade; But the Lot of high pollution grade forbids getting in the board of the low class of pollution and pollutes control, and is as shown in Figure 1, has only the class of pollution a of Lot could allow this Lot entering board to carry out explained hereafter less than the class of pollution b that sets according to the board ability on the board.But along with produce device to pollute control require increasingly high; Division to the class of pollution is more and more thinner; Especially in copper wiring and the shared production line pattern of aluminum manufacturing procedure, the class of pollution of division is more and more, and increasing of the class of pollution will make that polluting control becomes increasingly complex; Though possibly exist simultaneously some to pollute mutual exclusion between sign, not have strict grade differential.
Summary of the invention
The invention discloses groundwater pollution control in a kind of semiconductor crystal wafer manufacturing, wherein, may further comprise the steps:
Step S1: need be arranged to one item missing based on management and control and pollute sign, and corresponding each technology website and characteristic thereof should be polluted and indicate and default on this technology website; Based on the board ability, on each board, set at least one the pollution that allows to get into and indicate;
Step S2: silicon chip is criticized when the technology website of technical process is arranged, and this technology website all is arranged at the pollution sign of presetting it on the traveler that silicon chip criticizes; During through non-technical process technology website, this silicon chip is criticized and is kept the pollution sign that gets into before the board operation.
Step S3: before the board that gets into next technology website; Allow the pollution sign of entering to compare the pollution sign on the traveler and this board; If the pollution sign on the traveler all among the pollution sign that this board allows to get into, then allows to get into this board; Otherwise, do not allow to get into this board.
Groundwater pollution control during above-mentioned semiconductor crystal wafer is made, wherein, each technical process technology website is provided with a pollution sign among the step S1.
Groundwater pollution control during above-mentioned semiconductor crystal wafer is made, wherein, according to the character decision of its employed board the technology website of process be that the technology website of technical process or the technology website of non-technical process are arranged.
Groundwater pollution control during above-mentioned semiconductor crystal wafer is made wherein, among the step S3, adopts manufacturing executive system to allow the pollution sign of entering to compare the pollution sign on the traveler and this board.
In sum; Owing to adopted technique scheme; The present invention proposes groundwater pollution control in a kind of semiconductor crystal wafer manufacturing; Pollute sign through criticizing at silicon chip to be provided with on (Lot), on board, set and allow the pollution sign that passes through, utilize judge silicon chip criticize with the pollution sign whether be that board allows to carry out management and control through the mode that pollution indicates; Not only need not give and pollute the sign ranked; Also can constantly not increase the weight of the strength safeguarded because of the increase of the class of pollution, thereby realize the easily cross pollution of control production line, the silicon chip that can also effectively prevent the low class of pollution is simultaneously criticized owing to get into the pollution that makes itself appearance behind the board of high pollution grade.
Description of drawings
Fig. 1 adopts conventional class of pollution mode to pollute the schematic flow sheet of control in the background technology of the present invention;
Fig. 2 is the schematic flow sheet of groundwater pollution control during semiconductor crystal wafer of the present invention is made.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
Fig. 2 is the schematic flow sheet of groundwater pollution control during semiconductor crystal wafer of the present invention is made.As shown in Figure 2, groundwater pollution control during a kind of semiconductor crystal wafer of the present invention is made:
At first, according to the pollution management and control demand on the actual production line, carry out classification setting to polluting sign; F0 is set representes that standard front, PR represent that leading portion band glue, BE represent that AL processing procedure back segment, BEPR represent that AL processing procedure back segment band glue, CU represent that copper wiring, CUPR represent that copper wiring band glue, NI represent that NI processing procedure, NIPR represent NI processing procedure band glue etc.
Secondly, according to each board and ability thereof, on this board, be set to the pollution sign that one item missing allows entering; Setting board 1/ ability 1 allows the pollution of entering to be masked as F0; The pollution that board 1/ ability 2 allows to get into is masked as BE, BEPR; The pollution that board 2/ ability 1 allows to get into is masked as F0, PR, BE, BEPR, and the pollution that board 2/ ability 2 allows to get into is masked as CU, CUPR.
Then, the pollution according to each technology website and the preset correspondence of characteristic thereof indicates on this technology website; Use the preset pollution of technology website of technology board to be masked as BE first, then criticize to be provided with to pollute on the traveler of (Lot) and indicate BE through the silicon chip of this technology website.
At last, before Lot gets into the board of next technology website, manufacture executive system the pollution on the traveler is indicated that the pollution sign that allows to get in this board compares, to confirm whether this Lot can get into this board and carry out technological operation.Be masked as BE owing to pollute on the Lot traveler, and current technology website to want the board ability be 2, then this Lot can only get into board 1/ ability 2 and carries out technological operation, board 1/ ability 1, board 2/ ability 1 and board 2/ ability 2 are all forbidden this Lot entering.
In sum; Owing to adopted technique scheme; The present invention proposes groundwater pollution control in a kind of semiconductor crystal wafer manufacturing; Pollute sign through criticizing at silicon chip to be provided with on (Lot), on board, set and allow the pollution sign that passes through, utilize judge silicon chip criticize with the pollution sign whether be that board allows to carry out management and control through the mode that pollution indicates; Not only need not give and pollute the sign ranked; Also can constantly not increase the weight of the strength safeguarded because of the increase of the class of pollution, thereby realize the easily cross pollution of control production line, the silicon chip that can also effectively prevent the low class of pollution is simultaneously criticized owing to get into the pollution that makes itself appearance behind the board of high pollution grade.
Through explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read above-mentioned explanation after, various variations and revise undoubtedly will be obvious.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (4)
1. groundwater pollution control during a semiconductor crystal wafer is made is characterized in that, may further comprise the steps:
Step S1: need be arranged to one item missing based on management and control and pollute sign, and corresponding each technology website and characteristic thereof should be polluted and indicate and default on this technology website; Based on the board ability, on each board, set at least one the pollution that allows to get into and indicate;
Step S2: silicon chip is criticized when the technology website of technical process is arranged, and this technology website all is arranged at the pollution sign of presetting it on the traveler that silicon chip criticizes; During through non-technical process technology website, this silicon chip is criticized and is kept the pollution sign that gets into before the board operation;
Step S3: before the board that gets into next technology website; Allow the pollution sign of entering to compare the pollution sign on the traveler and this board; If the pollution sign on the traveler all among the pollution sign that this board allows to get into, then allows to get into this board; Otherwise, do not allow to get into this board.
2. groundwater pollution control during semiconductor crystal wafer according to claim 1 is made is characterized in that, each technical process technology website is provided with a pollution sign among the step S1.
3. groundwater pollution control during semiconductor crystal wafer according to claim 1 is made is characterized in that, according to the character decision of its employed board the technology website of process be that the technology website of technical process or the technology website of non-technical process are arranged.
4. groundwater pollution control during semiconductor crystal wafer according to claim 1 is made is characterized in that, among the step S3, adopts manufacturing executive system to allow the pollution sign of entering to compare the pollution sign on the traveler and this board.
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CN 201110356288 CN102446793B (en) | 2011-11-11 | 2011-11-11 | Method for controlling pollution in manufacturing of semiconductor wafer |
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CN 201110356288 CN102446793B (en) | 2011-11-11 | 2011-11-11 | Method for controlling pollution in manufacturing of semiconductor wafer |
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CN102446793B CN102446793B (en) | 2013-08-07 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020045328A1 (en) * | 2000-10-12 | 2002-04-18 | Yoshiaki Kobayashi | Method of manufacturing a semiconductor integrated circuit device |
CN1490842A (en) * | 2002-10-16 | 2004-04-21 | 旺宏电子股份有限公司 | Method and device for protecting wafers from stains in semiconductor manufacturing procedure |
CN1664985A (en) * | 2004-03-03 | 2005-09-07 | 台湾积体电路制造股份有限公司 | System and method for process contamination prevention for semiconductor manufacturing |
CN1866491A (en) * | 2005-05-18 | 2006-11-22 | 国际商业机器公司 | Pod swapping internal to tool run time |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020045328A1 (en) * | 2000-10-12 | 2002-04-18 | Yoshiaki Kobayashi | Method of manufacturing a semiconductor integrated circuit device |
CN1490842A (en) * | 2002-10-16 | 2004-04-21 | 旺宏电子股份有限公司 | Method and device for protecting wafers from stains in semiconductor manufacturing procedure |
CN1664985A (en) * | 2004-03-03 | 2005-09-07 | 台湾积体电路制造股份有限公司 | System and method for process contamination prevention for semiconductor manufacturing |
CN1866491A (en) * | 2005-05-18 | 2006-11-22 | 国际商业机器公司 | Pod swapping internal to tool run time |
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