CN102426618A - Processing method for integrated circuit layout surface planarity and integrated circuit layout - Google Patents
Processing method for integrated circuit layout surface planarity and integrated circuit layout Download PDFInfo
- Publication number
- CN102426618A CN102426618A CN2011103366478A CN201110336647A CN102426618A CN 102426618 A CN102426618 A CN 102426618A CN 2011103366478 A CN2011103366478 A CN 2011103366478A CN 201110336647 A CN201110336647 A CN 201110336647A CN 102426618 A CN102426618 A CN 102426618A
- Authority
- CN
- China
- Prior art keywords
- redundant metal
- integrated circuit
- interconnection line
- circuit diagram
- redundant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The embodiment of the invention provides a processing method for integrated circuit layout surface planarity. An integrated circuit layout comprises interconnection lines and redundant metal, wherein the density of the redundant metal between the interconnection lines is constant; and the integrated circuit layout surface planarity is improved by adjusting distribution of the redundant metal. The embodiment of the invention, on the other hand, also provides the integrated circuit layout. In the scheme provided by the invention, dishing and erosion of the layout surface are reduced and the product reliability and yield are improved by considering influence of the factor of the redundant metal itself on the surface planarity. In addition, according to the scheme provided by the invention, small changes are made on the conventional integrated circuit design; and the method is easy and efficient to realize.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly, the present invention relates to the disposal route and the integrated circuit diagram of integrated circuit diagram surface.
Background technology
Redundant metal filled (Dummy Fill) is the applied technology of improving flattening surface in the integrated circuit manufacturing; It improves the homogeneity of domain density by redundant metal; Improvement is at CMP (Chemical Mechanical Polishing; Cmp) flatness on surface, back reduces dish-shaped defective (dishing), corrodes (erosion), and then improves reliability of products and yield.Integrated circuit (Integrated Circuit; IC) the speed development that doubles with per 18 months integrated levels according to Moore's Law of manufacturing technology; But when the characteristic dimension of integrated circuit drops to below 90 nanometers; The IC manufacturing technology has run into unprecedented challenge, and the smooth property of air spots has badly influenced the performance and the stability of device, the redundant metal filled indispensable step that become.
The most serious problem then is the variation of process below 90 nanometers.There are some factors can have influence on these variations of process, like lithography, cmp or the like.In the CMP stage, uneven density metal causes the inconsistent of metal and built-in electrical insulation body thickness, and therefore redundant metal is used to regulate density metal, thereby makes the metal level consistent in density reach better planarization in the CMP stage.Existing redundant metal filled in; Only considered the problem of domain density uniformity; Take to reach the density of regulation with a kind of filling mode for density regions; And do not pay close attention to the influence of the various character of redundant metal to the domain surface itself, so filling mode often is not an optimum way.Yet different redundant metal filled methods can cause different influences to the integrated circuit diagram surface.
Therefore,, be necessary to propose the corresponding techniques scheme, optimize the filling mode of redundant metal, make the surface of domain reach better flatness, thereby improve the stability and the manufacturability of product, improve the yield of product based on the needs of reality.
Summary of the invention
The object of the invention is intended to solve at least one of above-mentioned technological deficiency, and particularly the factor through considering redundant metal itself reduces dish-shaped defective, the erosion on domain surface to the influence of surface, improves product reliability and yield.
The embodiment of the invention has proposed a kind of disposal route of integrated circuit diagram surface on the one hand; Said integrated circuit diagram comprises interconnection line and redundant metal; The density of the redundant metal between the wherein said interconnection line is constant; Adjust the distribution of said redundant metal, improve said integrated circuit diagram surface.
The embodiment of the invention has also proposed a kind of integrated circuit diagram on the other hand; Said integrated circuit diagram comprises interconnection line and redundant metal; The density of the redundant metal between the wherein said interconnection line is constant, and the size of said redundant metal remains unchanged, and increases the distance between said interconnection line and the redundant metal; Reduce the distance between the said redundant metal simultaneously, improved said integrated circuit diagram surface.
The embodiment of the invention has also proposed a kind of integrated circuit diagram on the other hand; Said integrated circuit diagram comprises interconnection line and redundant metal; The density of the redundant metal between the wherein said interconnection line is constant; Distance between said redundant metal and the said interconnection line remains unchanged, and the size of the said redundant metal of scaled down improves said integrated circuit diagram surface.
The embodiment of the invention has also proposed a kind of integrated circuit diagram on the other hand; Said integrated circuit diagram comprises interconnection line and redundant metal; The density of the redundant metal between the wherein said interconnection line is constant, and the distance between said redundant metal and the said interconnection line remains unchanged, and the width of said redundant metal remains unchanged; Reduce the length of said redundant metal, improve said integrated circuit diagram surface.
The such scheme that the present invention proposes, the factor through considering redundant metal itself reduces the dish-shaped defective and the erosion on domain surface, raising product reliability and yield to the influence of surface.For example; The size through adjusting redundant metal and the length of side of the distance between the interconnection line or redundant metal and interconnection line corresponding sides; Reduce the dish-shaped defective and the erosion on domain surface under the same conditions, improved surface, meanwhile improved the manufacturability and the reliability of product.In addition, the such scheme that the present invention proposes, little to the change of existing IC design, and realize simple, efficient.
Aspect that the present invention adds and advantage part in the following description provide, and these will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is redundant metal and an interconnection line position relation in the prior art;
Fig. 2 is redundant metal of the embodiment of the invention and interconnection line position relation;
Fig. 3 is the redundant metal dimension synoptic diagram of embodiment of the invention scaled down;
Fig. 4 reduces the synoptic diagram of redundant metal length for the embodiment of the invention;
Fig. 5 for the embodiment of the invention increases between redundant metal and the signal wire apart from the time domain surface dish-shaped defective, erosion value the variation synoptic diagram;
The variation synoptic diagram of the dish-shaped defective in domain surface, erosion value when Fig. 6 increases the length of redundant metal for the embodiment of the invention;
Fig. 7 is that the density of the redundant metal of the embodiment of the invention and the distance between the interconnection line remain unchanged, and changes the size of redundant metal itself, the variation synoptic diagram of the dish-shaped defective in domain surface, erosion value.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
In order to realize the present invention's purpose; The embodiment of the invention has proposed a kind of disposal route of integrated circuit diagram surface; Said integrated circuit diagram comprises interconnection line and redundant metal; The density of the redundant metal between the wherein said interconnection line is constant, adjusts the distribution of said redundant metal, improves said integrated circuit diagram surface.
As shown in Figure 1, be redundant metal in the prior art and interconnection line position relation.With reference to above-mentioned relation, the present invention is set forth.
In order to reach the present invention's purpose; The technical scheme that the present invention adopts is: a kind of integrated circuit diagram; Comprise interconnection line and redundant metal, its special character is: the density of redundant metal, size remain unchanged between interconnection line, when the size of interconnection line and the distance between the signal wire are all constant; Increase the distance between redundant metal and the interconnection line, the distance between for example redundant metal and the interconnection line is 3 times of size of redundant metal itself; When the size of the distance between the density of redundant metal, redundant metal and the interconnection line, interconnection line and the distance between the interconnection line are all constant, the size of dwindling redundant metal; When the size of the width of the density of redundant metal, redundant metal, interconnection line and the distance between the interconnection line are all constant, reduce the length of redundant metal, promptly reduce the length on the limit of corresponding interconnection line.
Below in conjunction with accompanying drawing and embodiment, technical scheme of the present invention is further specified.
Referring to Fig. 2; The method of the present invention in the integrated circuit diagram redundant metal being positioned; The method is when density and the size of redundant metal between interconnection line remains unchanged, to increase the distance between interconnection line and the redundant metal, has reduced the distance between the redundant metal simultaneously.
As shown in Figure 3, the density of redundant metal and the distance between the interconnection line remain unchanged, the size of the redundant metal of scaled down.
As shown in Figure 4, the distance between the density of redundant metal, width and the interconnection line remains unchanged, and reduces the length of redundant metal.
As shown in Figure 5, the density and the size of redundant metal are certain, when d (as shown in Figure 2, d representes the distance between redundant metal and the signal wire) changes, and the variation of the dish-shaped defective in domain surface, erosion value.
As shown in Figure 6, the distance between the density of redundant metal, width and the interconnection line remains unchanged, and increases the length of redundant metal; The dish-shaped defective value in domain surface increases; The erosion value reduces, so should make redundant metal reduce (as shown in Figure 4, as to be L) over against the length of side of interconnection line.
As shown in Figure 7, the density of redundant metal and the distance between the interconnection line remain unchanged, and change the size of redundant metal itself, the variation of the dish-shaped defective in domain surface, erosion value.
Correspondingly, according to said method, the embodiment of the invention has also proposed a kind of integrated circuit diagram on the other hand; Said integrated circuit diagram comprises interconnection line and redundant metal; The density of the redundant metal between the wherein said interconnection line is constant, and the size of said redundant metal remains unchanged, and increases the distance between said interconnection line and the redundant metal; Reduce the distance between the said redundant metal simultaneously, improved said integrated circuit diagram surface.
Correspondingly; According to said method, the embodiment of the invention has also proposed a kind of integrated circuit diagram on the other hand, and said integrated circuit diagram comprises interconnection line and redundant metal; The density of the redundant metal between the wherein said interconnection line is constant; Distance between said redundant metal and the said interconnection line remains unchanged, and the size of the said redundant metal of scaled down improves said integrated circuit diagram surface.
Correspondingly, according to said method, the embodiment of the invention has also proposed a kind of integrated circuit diagram on the other hand; Said integrated circuit diagram comprises interconnection line and redundant metal; The density of the redundant metal between the wherein said interconnection line is constant, and the distance between said redundant metal and the said interconnection line remains unchanged, and the width of said redundant metal remains unchanged; Reduce the length of said redundant metal, improve said integrated circuit diagram surface.
The such scheme that the present invention proposes, the factor through considering redundant metal itself reduces dish-shaped defective, the erosion on domain surface, raising product reliability and yield to the influence of surface.For example; The size through adjusting redundant metal and the length of side of the distance between the interconnection line or redundant metal and interconnection line corresponding sides; Reduce dish-shaped defective, the erosion on domain surface under the same conditions, improved surface, meanwhile improved the manufacturability and the reliability of product.In addition, the such scheme that the present invention proposes, little to the change of existing IC design, and realize simple, efficient.
Though specify about example embodiment and advantage thereof, be to be understood that under the situation of the protection domain that does not break away from the qualification of spirit of the present invention and accompanying claims, can carry out various variations, replacement and modification to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping protection domain of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the instructions.From disclosure of the present invention; To easily understand as those of ordinary skill in the art; For the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present; Wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.
Therefore, accompanying claims of the present invention is intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection domain.Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention, can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (7)
1. the disposal route of an integrated circuit diagram surface; It is characterized in that; Said integrated circuit diagram comprises interconnection line and redundant metal; The density of the redundant metal between the wherein said interconnection line is constant, adjusts the distribution of said redundant metal, improves said integrated circuit diagram surface.
2. disposal route as claimed in claim 1 is characterized in that, the distribution of adjusting said redundant metal comprises:
The size of said redundant metal remains unchanged, and increases the distance between said interconnection line and the redundant metal, has reduced the distance between the said redundant metal simultaneously.
3. disposal route as claimed in claim 1 is characterized in that, the distribution of adjusting said redundant metal comprises:
Distance between said redundant metal and the said interconnection line remains unchanged, the size of the said redundant metal of scaled down.
4. disposal route as claimed in claim 1 is characterized in that, the distribution of adjusting said redundant metal comprises:
Distance between said redundant metal and the said interconnection line remains unchanged, and the width of said redundant metal remains unchanged, and reduces the length of said redundant metal.
5. integrated circuit diagram; It is characterized in that said integrated circuit diagram comprises interconnection line and redundant metal, the density of the redundant metal between the wherein said interconnection line is constant; The size of said redundant metal remains unchanged; Increase the distance between said interconnection line and the redundant metal, reduced the distance between the said redundant metal simultaneously, improve said integrated circuit diagram surface.
6. integrated circuit diagram; It is characterized in that; Said integrated circuit diagram comprises interconnection line and redundant metal, and the density of the redundant metal between the wherein said interconnection line is constant, and the distance between said redundant metal and the said interconnection line remains unchanged; The size of the said redundant metal of scaled down improves said integrated circuit diagram surface.
7. integrated circuit diagram; It is characterized in that said integrated circuit diagram comprises interconnection line and redundant metal, the density of the redundant metal between the wherein said interconnection line is constant; Distance between said redundant metal and the said interconnection line remains unchanged; The width of said redundant metal remains unchanged, and reduces the length of said redundant metal, improves said integrated circuit diagram surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103366478A CN102426618A (en) | 2011-10-31 | 2011-10-31 | Processing method for integrated circuit layout surface planarity and integrated circuit layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103366478A CN102426618A (en) | 2011-10-31 | 2011-10-31 | Processing method for integrated circuit layout surface planarity and integrated circuit layout |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102426618A true CN102426618A (en) | 2012-04-25 |
Family
ID=45960598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103366478A Pending CN102426618A (en) | 2011-10-31 | 2011-10-31 | Processing method for integrated circuit layout surface planarity and integrated circuit layout |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102426618A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7509622B2 (en) * | 2006-04-17 | 2009-03-24 | Synopsys, Inc. | Dummy filling technique for improved planarization of chip surface topography |
| CN102222643A (en) * | 2011-06-24 | 2011-10-19 | 中国科学院微电子研究所 | Method for filling redundant metal in manufacturing process of integrated circuit and semiconductor device |
-
2011
- 2011-10-31 CN CN2011103366478A patent/CN102426618A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7509622B2 (en) * | 2006-04-17 | 2009-03-24 | Synopsys, Inc. | Dummy filling technique for improved planarization of chip surface topography |
| CN102222643A (en) * | 2011-06-24 | 2011-10-19 | 中国科学院微电子研究所 | Method for filling redundant metal in manufacturing process of integrated circuit and semiconductor device |
Non-Patent Citations (4)
| Title |
|---|
| ARTHUR NIEUWOUDT等: "Impact of Dummy Filling Techniques on Interconnect Capacitance and Planarization in Nano-Scale Process Technology", 《GLSVLSI "08 PROCEEDINGS OF THE 18TH ACM GREAT LAKES SYMPOSIUM ON VLSI》, 31 December 2008 (2008-12-31), pages 152 - 154 * |
| 周隽雄，陈岚，阮文彪，李志刚，沈伟翔，叶甜春: "Dummy fill effect on CMP planarity", 《JOURNAL OF SEMICONDUCTORS》, vol. 31, no. 10, 30 October 2010 (2010-10-30), XP055254177, DOI: doi:10.1088/1674-4926/31/10/106003 * |
| 杨飞，何晓雄，陈岚: "冗余金属对互连线电容特性的影响", 《合肥工业大学学报（自然科学版）》, vol. 33, no. 11, 30 November 2010 (2010-11-30), pages 1721 - 1724 * |
| 杨飞: "冗余金属填充对电特性的影响研究", 《中国优秀硕士学位论文全文数据库》, 30 April 2011 (2011-04-30) * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103902789A (en) | Filling method of redundant graphs | |
| CN101376232B (en) | Chemical mechanical polishing method capable of enhancing polishing performance | |
| US20120276820A1 (en) | Method for Adjusting Metal Polishing Rate and Reducing Defects Arisen in a Polishing Process | |
| US20150200111A1 (en) | Planarization scheme for finfet gate height uniformity control | |
| Nagar et al. | Potassium sorbate as an inhibitor in copper chemical mechanical planarization slurries. Part II: Effects of sorbate on chemical mechanical planarization performance | |
| CN104745086A (en) | Chemical mechanical polishing solution for barrier layer planarization, and use method thereof | |
| CN102385656A (en) | Method for filling redundant metal into integrated circuit layout and integrated circuit | |
| Lee et al. | Experimental investigation of process parameters for roll-type linear chemical mechanical polishing (Roll-CMP) system | |
| CN102426618A (en) | Processing method for integrated circuit layout surface planarity and integrated circuit layout | |
| CN109664162B (en) | Method and system for dynamic process optimization in chemical mechanical polishing of metal plugs | |
| CN104745088A (en) | Chemical mechanical polishing solution for barrier layer planarization, and use method thereof | |
| Han et al. | Effect of pad surface roughness on material removal rate in chemical mechanical polishing using ultrafine colloidal ceria slurry | |
| Zhang et al. | Investigation on S-136 steel surface planarization by chemical mechanical polishing | |
| CN101934493B (en) | Polishing process of ultrathin zone-melting silicon polished wafer | |
| CN102371534B (en) | Chemical mechanical polishing method for surface of wafer | |
| JP6499059B2 (en) | Semiconductor device manufacturing method and chemical mechanical polishing slurry | |
| CN110614580B (en) | Polishing pad, preparation method thereof and chemical mechanical polishing equipment | |
| CN103531440B (en) | A kind of surface repairing method of wafer rear | |
| CN203622204U (en) | Grinding pad adjuster | |
| US9278423B2 (en) | CMP slurry particle breakup | |
| CN104308744A (en) | Chemical mechanical grinding liquid supply device | |
| CN105583718A (en) | Chemical mechanical polishing (CMP) method | |
| CN101457136A (en) | Lapping liquid and chemical-mechanical lapping method | |
| CN104239612A (en) | Method for improving laser annealing heat distribution | |
| Seo | Oxide-chemical mechanical polishing characteristics using silica slurry retreated by mixing of original and used slurry |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120425 |