CN102426472A - Hardware-in-the-loop generator and use method thereof - Google Patents
Hardware-in-the-loop generator and use method thereof Download PDFInfo
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Abstract
The invention discloses a hardware-in-the-loop generator which comprises a physical object part and a non-physical object part, wherein the non-physical object part is an upper computer loaded with waveform design simulation software; the physical object part is a lower computer; the lower computer comprises a D/A (Digital/Analogue) converter circuit, a signal conditioning circuit and an FPGA (Field Programmable Gate Array) chip in which an NiosII soft core processor is embedded; when the hardware-in-the-loop generator is in use, the non-physical object part can be used for calling an automatic mode by manual operation or program to set parameters of simulation waveform; if the displayed simulation waveform meets the requirement, module parameters are generated and transmitted to the lower computer and then are matched with an NiosII soft core processor and dual-port RAM (Random Access Memory) and DDS (Direct Digital Synthesizer) modules to transmit the processed digital signal to the D/A converter circuit; and finally, the processed digital signal is processed by the D/A converter circuit and the signal conditioning circuit to obtain a final signal. With the design, the hardware-in-the-loop generator disclosed by the invention has the advantages of higher precision, stronger intuitiveness, lower production cost, higher automatic degree and wide application range.
Description
Technical field
The present invention relates to a kind of signal generator, relate in particular to a kind of half signal generator in kind and method of application thereof, specifically be applicable to Nios II soft-core processor, DDS technology, SOPC is technological combines with the generation signal with upper computer software, lower computer hardware.
Background technology
At present, special-purpose on the market function signal generator mainly contains analog-and digital-two types.Analog signal generator adopts mimic channel to accomplish the conversion of signal, and precision is low, distortion is big, does not re-use basically; Digital signal generator adopts the DDS technology more, and the mode of utilizing DSP to combine with FPGA is accomplished the calculating and the output of signal, though precision is higher, requires circuit to have stronger arithmetic capability, and cost is higher.
In addition, existing signal generator adopts the mode of panel button control that the parameter and the type of waveform are set more, and not only the man-machine interface demonstration is directly perceived inadequately, and equipment volume is big, cost is higher.
The Chinese patent publication number is CN101162398A; The patent of invention that open day is on April 16th, 2008 discloses a kind of arbitrarily signal generating device based on FPGA, comprises PC, USB controller, MCU3, MCU interface module, crystal oscillator, EPC2, clock controller, binary channels DA output circuit, frequency controller, register matrix unit, keyboard, keyboard scan module, FLASH, FLASH control module, TFT display, TFT control module, DDS signal generator, waveform synthesis module and other waveform generator; During use, on the software control interface, behind input spectrum figure and the phase spectrum graph parameter, software is accomplished spectrum information identification automatically, obtains the amplitude and the phase parameter of frequency; With obtaining the time-domain information table behind the sampled value quantization encoding, download to DDS and produce among the RAM of circuit then, performance period or aperiodic time-domain signal reduction output, and the online stepping of wave-shape amplitude is adjustable.Though this invention can be imported through frequency domain, the mode of time domain output produces required signal, it still has following defective:
At first; This invention is that the mode through frequency domain input, time domain output produces required signal, rather than the various parameters of signal waveform are directly set, directly specific aim a little less than; There is distortion to a certain degree; Especially between frequency domain input, time domain output, will could realize that also this has further increased the possibility of distortion through Fourier transform, the degree of accuracy that therefore should invent is relatively poor;
Secondly, this invention is through PC and go up the software that loads and accomplish signal data, is sent to fpga chip in MCU, the slave computer successively to produce signal, wherein through USB interface again; When signal data produces, can only obtain the time-domain information table, and not have emulation to show for the concrete condition of reality generation signal, intuitive is too poor; In case be provided with wrongly, can only after slave computer shows, just can reflect, do over again then, bigger waste manpower and material resources; Increased production cost, in addition, this invention does not make full use of the internal resource of fpga chip; But signal data is carried out computing through MCU, the combined mode of fpga chip, and taking place thereby accomplish signal, this has not only increased the volume of equipment; And increased production cost once more, so this invent not only intuitive a little less than, and production cost is higher;
The 3rd, operations such as the input of this invention intermediate frequency spectrogram and phase place spectrogram, Fourier transform, periodic sampling all depend on manual input, and this has increased operation easier, and the automaticity that therefore should invent is lower;
The 4th; Host computer in this invention is sent to signal data in MCU, the fpga chip through USB interface successively, and not only transmission range is limited, and can only carry out man-to-man transmission; Limited the range of application of this device greatly, the range of application that therefore should invent is narrower.
Summary of the invention
The objective of the invention is to overcome the degree of accuracy that exists in the prior art is relatively poor, intuitive is weak, production cost is higher, automaticity is lower, range of application is narrower defective and problem, half signal generator in kind and the method for application thereof that a kind of degree of accuracy is higher, intuitive is strong, production cost is lower, automaticity is higher, range of application is wider is provided.
For realizing above purpose; Technical solution of the present invention is: a kind of half signal generator in kind; Comprise interconnective host computer and slave computer, said slave computer comprises fpga chip and DA converter circuit, and an end of fpga chip is communicated by letter with host computer and is connected; The other end is connected with the DA converter circuit, and on fpga chip, be connected with power supply, serial FLASH and clock;
Be mounted with the Waveform Design simulation software on the said host computer, the quantity of said slave computer is at least one, and slave computer also comprises signal conditioning circuit; Also be connected with RS232 interface, Ethernet interface and SDRAM storer on the said fpga chip, and in fpga chip, be provided with Nios II soft-core processor, DDS module, dual port RAM and frequency control word register;
Said Nios II soft-core processor comprises CPU processor, URAT controller, sdram controller, EPCS controller, ethernet controller, a PIO controller and No. two PIO controllers; The CPU processor is communicated by letter and is connected with RS232 interface, SDRAM storer, serial FLASH, Ethernet interface respectively through URAT controller, sdram controller, EPCS controller, ethernet controller; The other end of RS232 interface, Ethernet interface is all communicated by letter with host computer and is connected; The CPU processor is connected with dual port RAM through a PIO controller; The other end of dual port RAM is connected with DDS module, DA converter circuit respectively; The other end of DDS module is connected with the CPU processor through frequency control word register, No. two PIO controllers successively, and the other end of DA converter circuit is connected with signal conditioning circuit.
Said host computer is a PC, and said fpga chip adopts Cyclone, Cyclone II or the Cyclone III family chip of altera corp.
Said DA converter circuit comprises a high-speed D and a low-speed highly precise DA converter; One end of high-speed D is connected with dual port RAM; The other end is connected with signal conditioning circuit; One end of low-speed highly precise DA converter is connected with dual port RAM, and the other end is as the reference source input of high-speed D.
Said signal conditioning circuit comprises fixed gain amplifier, LC wave filter and power amplifier, and this fixed gain amplifier is connected with the other end of high-speed D.
A kind of method of application of above-mentioned half signal generator in kind, this method of application may further comprise the steps successively:
The first step: the Waveform Design simulation software to upper internal stowage is provided with earlier; Its method to set up comprises that the interface manually is provided with and routine call is provided with automatically, and it is provided with content and comprises: COM1, signal type, amplitude, frequency, phase place and high-low level; Said COM1 comprises RS232 interface or Ethernet interface, and said signal type comprises sine wave, triangular wave and the square wave in the reference waveform;
Second the step: above-mentioned end of text is set after; On the screen of host computer, demonstrate simulation waveform again; If the simulation waveform that shows meets the requirements; Then generate the required module parameter of DDS module in the slave computer by this Waveform Design simulation software, this module parameter comprises waveform ROM table data, phase accumulator initial value and amplitude control signal, through RS232 interface or Ethernet interface this module parameter is sent to slave computer then;
The 3rd step: first energized is configured fpga chip through serial FLASH, and Nios II soft-core processor is carried out the program loading; Receive the module parameter that host computer sends by Nios II soft-core processor through RS232 interface or Ethernet interface then; And this module parameter deposited in the SDRAM storer, carry out computing by the CPU processor again, the digital signal with the computing gained deposits in the dual port RAM then; And cooperate with the DDS module this digital signal is passed to the DA converter circuit; Convert this digital signal into simulating signal by the DA converter circuit again, handled by signal conditioning circuit then, can obtain final signal this moment.
In the said first step computing and the modulation that content also comprises signal be set; Its method to set up is: accomplish earlier the setting of two groups of signals, select compute mode again, this compute mode comprises and adding, subtracts, multiplication is modulated with signal; Confirm then, get final product the computing of end signal and the setting of modulation.
In the said first step; When adopting the manual set-up mode in interface; Its signal type also comprises random waveform, and the set-up mode of this random waveform is: open waveform earlier and draw panel, draw the waveform that manual drawing is wanted in the panel with mouse at waveform again; Click then and accomplish, can finish the setting of random waveform.
In the said first step, the maximal value of amplitude is 5V, and frequency is 0.1Hz – 10MHz.
Compared with prior art, beneficial effect of the present invention is:
1, owing in a kind of half signal generator in kind of the present invention and the method for application thereof COM1, signal type, amplitude, frequency, phase place and high-low level are set in the Waveform Design simulation software earlier; On the screen of host computer, demonstrate simulation waveform again; If the waveform that shows meets the requirements, then generate the module parameter that the DDS module needs by this Waveform Design simulation software; At first, the content of setting of the present invention is the direct parameter of signal waveform, and directly specific aim is stronger, is difficult for distortion, have higher degree of accuracy, and the present invention can also carry out the computing and the modulation of signal when being provided with, can further improve degree of accuracy; Secondly, the design shows simulation waveform earlier, and just generation module parameter meets the requirements; Not only intuitive is stronger, and is convenient to improve degree of accuracy and avoids doing over again, and has saved production cost; Especially when adopting the manual set-up mode in interface; Its signal type is a random waveform, and the complete armrest of this random waveform is depicted as, and intuitive is extremely strong.Therefore not only degree of accuracy is higher, intuitive is stronger in the present invention, and production cost is lower.
2, owing to be embedded with Nios II soft-core processor at fpga chip in a kind of half signal generator in kind of the present invention and the method for application thereof; This Nios II soft-core processor can be stored the data that the host computer transmission comes, computing; And the digital signal of computing gained deposited in the dual port RAM; And cooperate with the DDS module this digital signal passed to the DA converter circuit, this kind Nios II soft-core processor design use the internal resource of fpga chip, in conjunction with fpga chip handle fireballing advantage of digital circuit and Nios II soft-core processor processing controls task and data communication advantage easily; Rather than as prior art, signal data is carried out computing through MCU, the combined mode of fpga chip; The design has not only reduced the operand of system, and has saved a MCU, integrated keyboard and display screen, has simplified hardware configuration; Dwindle the volume of equipment, reduced the cost of equipment.Therefore production cost of the present invention is lower.
3, because a kind of half signal generator in kind of the present invention and method of application thereof when COM1, signal type, amplitude, frequency, phase place and high-low level are set in the Waveform Design simulation software; Its method to set up comprises that the interface manually is provided with and routine call is provided with automatically; This routine call is provided with automatically and is meant and can accomplishes setting through the mode of coding (Matlab, VC++), has alleviated manual fatigue greatly.Therefore automaticity of the present invention is higher.
4, because the host computer in a kind of half signal generator in kind of the present invention and the method for application thereof can be adopted as common PC; This design not only can effectively utilize PC fast operation, the friendly characteristics of man-machine interface; The slave computer operand is big to solve, button is provided with inconvenient technical barrier; But also can be widely used in the occasion that laboratory etc. has been equipped with PC, has needed signal source; Can under the condition of lowering apparatus performance not, reduce the volume and the cost of signal generator, the purpose that reach at lower cost, hardware simplicity, smaller size smaller realizes signal simulation and output; And the host computer among the present invention can be given many slave computers with data delivery through Ethernet interface, and not only transmission range is far away, and connection object is one-to-many, has enlarged range of application of the present invention greatly; In addition, the present invention not only can be applied to the design of instrument and meter, can also be applied in the circuit that needs the arbitrary signal generation; Submodule as wherein independently uses, and can be saved in the serial FLASH by the data of slave computer with the host computer transmission, then slave computer is broken away from host computer and uses; Promptly no longer need upper computer software toward slave computer transmission data; Only need power on during use, the data of preserving in the serial FLASH will be loaded in the SDRAM storer, have enlarged the design's range of application.Therefore range of application of the present invention is wider.
5, because the DA converter circuit in a kind of half signal generator in kind of the present invention and the method for application thereof comprises a high-speed D and a low-speed highly precise DA converter; The output of low-speed highly precise DA converter is the reference source input of high-speed D; This design is with the output voltage of the high-precision low speed DA of a slice converter reference voltage as high-speed D, and at this moment, each resolution corresponding voltage value is littler when less output voltage; Be convenient to the amplitude of waveform signal is adjusted; Improve system dynamics greatly and regulated the precision in the amplitude process, reduced noise, reduced error.Therefore degree of accuracy of the present invention is higher.
Description of drawings
Fig. 1 is a structural representation of the present invention.
Fig. 2 is the structural representation of DA converter circuit among Fig. 1.
Among the figure: host computer 1; Slave computer 2; Fpga chip 3; Serial FLASH 4; RS232 interface 5; SDRAM storer 6; Nios II soft-core processor 7; CPU processor 71; URAT controller 72; Sdram controller 73; EPCS controller 74; Ethernet controller 75; A PIO controller 76; No. two PIO controllers 77; DDS module 8; DA converter circuit 9; High-speed D 91; Low-speed highly precise DA converter 92; Signal conditioning circuit 10; Power supply 11; Clock 12; Ethernet interface 13; Dual port RAM 14; Frequency control word register 15.
Embodiment
Below in conjunction with description of drawings and embodiment the present invention is done further detailed explanation.
Referring to figure 1 – Fig. 2; A kind of half signal generator in kind; Comprise interconnective host computer 1 and slave computer 2, said slave computer 2 comprises fpga chip 3 and DA converter circuit 9, and an end of fpga chip 3 is connected with host computer 1 communication; The other end is connected with DA converter circuit 9, and on fpga chip 3, be connected with power supply 11, serial FLASH 4 and clock 12;
Be mounted with the Waveform Design simulation software on the said host computer 1, the quantity of said slave computer 2 is at least one, and slave computer 2 also comprises signal conditioning circuit 10; Also be connected with RS232 interface 5, Ethernet interface 13 and SDRAM storer 6 on the said fpga chip 3, and in fpga chip 3, be provided with Nios II soft-core processor 7, DDS module 8, dual port RAM 14 and frequency control word register 15;
Said Nios II soft-core processor 7 comprises CPU processor 71, URAT controller 72, sdram controller 73, EPCS controller 74, ethernet controller 75, a PIO controller 76 and No. two PIO controllers 77; CPU processor 71 is connected with RS232 interface 5, SDRAM storer 6, serial FLASH 4, Ethernet interface 13 communications respectively through URAT controller 72, sdram controller 73, EPCS controller 74, ethernet controller 75; The other end of RS232 interface 5, Ethernet interface 13 all is connected with host computer 1 communication; CPU processor 71 is connected with dual port RAM 14 through a PIO controller 76; The other end of dual port RAM 14 is connected with DDS module 8, DA converter circuit 9 respectively; The other end of DDS module 8 is connected with CPU processor 71 through frequency control word register 15, No. two PIO controllers 77 successively, and the other end of DA converter circuit 9 is connected with signal conditioning circuit 10.
Said host computer 1 is a PC, and said fpga chip 3 adopts Cyclone, Cyclone II or the Cyclone III family chip of altera corp.
Said DA converter circuit 9 comprises a high-speed D 91 and a low-speed highly precise DA converter 92; One end of high-speed D 91 is connected with dual port RAM 14; The other end is connected with signal conditioning circuit 10; One end of low-speed highly precise DA converter 92 is connected with dual port RAM 14, and the other end is as the reference source input of high-speed D 91.
Said signal conditioning circuit 10 comprises fixed gain amplifier, LC wave filter and power amplifier, and this fixed gain amplifier is connected with the other end of high-speed D 91.
A kind of method of application of above-mentioned half signal generator in kind, this method of application may further comprise the steps successively:
The first step: earlier the Waveform Design simulation software that loads in the host computer 1 is provided with; Its method to set up comprises that the interface manually is provided with and routine call is provided with automatically, and it is provided with content and comprises: COM1, signal type, amplitude, frequency, phase place and high-low level; Said COM1 comprises RS232 interface 5 or Ethernet interface 13, and said signal type comprises sine wave, triangular wave and the square wave in the reference waveform;
Second the step: above-mentioned end of text is set after; On the screen of host computer 1, demonstrate simulation waveform again; If the simulation waveform that shows meets the requirements; Then generate the required module parameter of DDS module in slave computer 28 by this Waveform Design simulation software, this module parameter comprises waveform ROM table data, phase accumulator initial value and amplitude control signal, through RS232 interface 5 or Ethernet interface 13 this module parameter is sent to slave computer 2 then;
The 3rd step: first energized 11; Be configured through 4 pairs of fpga chips 3 of serial FLASH again; And Nios II soft-core processor 7 is carried out program load, receive the module parameter that host computers 1 send by Nios II soft-core processor 7 through RS232 interface 5 or Ethernet interface 13 then, and this module parameter is deposited in the SDRAM storer 6; Carry out computing by CPU processor 71 again; Digital signal with the computing gained deposits in the dual port RAM 14 then, and cooperates with DDS module 8 this digital signal is passed to DA converter circuit 9, converts this digital signal into simulating signal by DA converter circuit 9 again; Handled by signal conditioning circuit 10 then, can obtain final signal this moment.
In the said first step computing and the modulation that content also comprises signal be set; Its method to set up is: accomplish earlier the setting of two groups of signals, select compute mode again, this compute mode comprises and adding, subtracts, multiplication is modulated with signal; Confirm then, get final product the computing of end signal and the setting of modulation.
In the said first step; When adopting the manual set-up mode in interface; Its signal type also comprises random waveform, and the set-up mode of this random waveform is: open waveform earlier and draw panel, draw the waveform that manual drawing is wanted in the panel with mouse at waveform again; Click then and accomplish, can finish the setting of random waveform.
In the said first step, the maximal value of amplitude is 5V, and frequency is 0.1Hz – 10MHz.
Principle of the present invention is explained as follows:
The Waveform Design simulation software: this software loading is in host computer; Has the dynamic link calling function; And the dynamic link calling function can be realized the program setting of signal parameter; In Matlab, VC++ supervisor, can accomplish and set, thereby this software could be provided with the parameter of simulation waveform automatically through routine call through the coding code.
Power supply: input 220V alternating voltage, output ± 5V, ± 15V or 3.3V DC voltage, supply total system work.
The RS232 interface: its relative interface circuit is accomplished by the MAX232 chip, can communicate through serial ports interconnection line and host computer.
Clock: the clock of mainly supplying with fpga chip uses, because the high output signal frequency of system is 10M, according to being Qwest's sampling law, the highest output frequency is the half the of system clock, adopts the 50M crystal oscillator can meet the demands fully here.
SDRAM storer: be used to store data and carry out the high speed read-write.
SDRAM circuit on the fpga chip is used to provide Nios the II memory headroom and the storing high-speed data of soft nuclear operation.
EPCS series serial Flash configuring chip: be used for preserving the configuration file of FPGA, guarantee the power on loading of back program of FPGA.
EPCS circuit on the fpga chip adopts the EPCS16 chip of altera corp, is used to preserve the configuration file of FPGA, and after resetting, automatically program code is copied among the SDRAM from EPCS.
The effect of PIO controller is a middle controller: because fpga chip is equally controlled the IO mouth unlike common single-chip microcomputer; Therefore the function that needs PIO controller to come the common IO mouth on the analogy single-chip microcomputer, the setting of No. one, No. two PIO controller are in order to explain that Nios II soft-core processor will control the just essential such middle controller of other circuit.
DA converter circuit: referring to Fig. 2; Adopt the cooperative structure of two-stage DA chip; Utilize the reference source of a serial high precision DA, improved system dynamics greatly and regulated precision in the amplitude process, reduced noise, reduced error as the another one high-speed D.Generally speaking, amplitude is regulated and can be realized through the amplitude size of direct modification waveform ROM table, but the adjusting of this method can only realize that amplitude is big the time, and amplitude hour is in this way with regard to out of true.For this reason; The present invention adopts the cooperative design of two-stage DA chip in the DA converter circuit; This design adopts hardware to realize that high-precision amplitude regulates, and with the output voltage of the high-precision low speed DA of a slice converter reference voltage as high-speed D, each resolution corresponding voltage value is littler when less output voltage; Be convenient to hour amplitude regulated, thereby improved the precision of system in amplitude.
Signal conditioning circuit: comprise fixed gain amplifier, LC wave filter, three parts of power amplifier; Because the signal of DA converter circuit output is 2Vpp; Needs increase fixed gain is 5 amplifier, and it is 20M that the LC wave filter is provided with cutoff frequency, the high order noise of filtering appts; Power amplification circuit increases the fan-out capability of electric current, and guarantees that the output signal does not change because of the variation of load.
Ethernet interface: comprise network transformer and ethernet control chip, it can through different each instruments of ID identification, can accept data through network with this kind signal generator access to LAN, realizes network control.
Embodiment 1:
A kind of half signal generator in kind; Comprise host computer 1 and at least one slave computer 2; Be mounted with the Waveform Design simulation software on the host computer 1; Slave computer 2 comprises fpga chip 3, DA converter circuit 9 and signal conditioning circuit 10; Be connected with serial FLASH 4, RS232 interface 5, power supply 11, SDRAM storer 6, clock 12 and Ethernet interface 13 on the fpga chip 3; Fpga chip 3 is embedded with Nios II soft-core processor 7, DDS module 8, dual port RAM 14 and frequency control word register 15; Nios II soft-core processor 7 comprises CPU processor 71, URAT controller 72, sdram controller 73, EPCS controller 74, ethernet controller 75, a PIO controller 76 and No. two PIO controllers 77; CPU processor 71 is connected with RS232 interface 5, SDRAM storer 6, serial FLASH 4, Ethernet interface 13 communications respectively through URAT controller 72, sdram controller 73, EPCS controller 74, ethernet controller 75; The other end of RS232 interface 5, Ethernet interface 13 all is connected with host computer 1 communication, and CPU processor 71 is connected with dual port RAM 14 through a PIO controller 76, and the other end of dual port RAM 14 is connected with DDS module 8, DA converter circuit 9 respectively; The other end of DDS module 8 is connected with CPU processor 71 through frequency control word register 15, No. two PIO controllers 77 successively, and the other end of DA converter circuit 9 is connected with signal conditioning circuit 10.Said DA converter circuit 9 comprises a high-speed D 91 and a low-speed highly precise DA converter 92; One end of high-speed D 91 is connected with dual port RAM 14; The other end is connected with signal conditioning circuit 10; One end of low-speed highly precise DA converter 92 is connected with dual port RAM 14, and the other end is as the reference source input of high-speed D 91.Said signal conditioning circuit 10 comprises fixed gain amplifier, LC wave filter and power amplifier, and this fixed gain amplifier is connected with the other end of high-speed D 91.
A kind of method of application of above-mentioned half signal generator in kind, this method of application may further comprise the steps successively:
The first step: earlier the Waveform Design simulation software that loads in the host computer 1 is provided with; Its method to set up comprises that the interface manually is provided with and routine call is provided with automatically, and it is provided with content and comprises: COM1, signal type, amplitude, frequency, phase place and high-low level; Said COM1 comprises RS232 interface 5 or Ethernet interface 13, and said signal type comprises sine wave, triangular wave and the square wave in the reference waveform;
Said computing and the modulation that content also comprises signal be set; Its method to set up is: accomplish earlier the setting of two groups of signals, select compute mode again, this compute mode comprises and adding, subtracts, multiplication is modulated with signal; Confirm then, get final product the computing of end signal and the setting of modulation;
When adopting the manual set-up mode in interface; Its signal type also comprises random waveform, and the set-up mode of this random waveform is: open waveform earlier and draw panel, draw the waveform that manual drawing is wanted in the panel with mouse at waveform again; Click then and accomplish, can finish the setting of random waveform;
The maximal value of said amplitude is 5V, and frequency is 0.1Hz – 10MHz;
Second the step: above-mentioned end of text is set after; On the screen of host computer 1, demonstrate simulation waveform again; If the simulation waveform that shows meets the requirements; Then generate the required module parameter of DDS module in slave computer 28 by this Waveform Design simulation software, this module parameter comprises waveform ROM table data, phase accumulator initial value and amplitude control signal, through RS232 interface 5 or Ethernet interface 13 this module parameter is sent to slave computer 2 then;
The 3rd step: first energized 11; Be configured through 4 pairs of fpga chips 3 of serial FLASH again; And Nios II soft-core processor 7 is carried out program load, receive the module parameter that host computers 1 send by Nios II soft-core processor 7 through RS232 interface 5 or Ethernet interface 13 then, and this module parameter is deposited in the SDRAM storer 6; Carry out computing by CPU processor 71 again; Digital signal with the computing gained deposits in the dual port RAM 14 then, and cooperates with DDS module 8 this digital signal is passed to DA converter circuit 9, converts this digital signal into simulating signal by DA converter circuit 9 again; Handled by signal conditioning circuit 10 then, can obtain final signal this moment.
Therefore not only degree of accuracy is higher in the present invention, intuitive is strong, production cost is lower, and automaticity is higher, range of application is wider.
Claims (8)
1. one and half signal generators in kind; Comprise interconnective host computer (1) and slave computer (2); Said slave computer (2) comprises fpga chip (3) and DA converter circuit (9), and an end of fpga chip (3) is connected with host computer (1) communication, and the other end is connected with DA converter circuit (9); And on fpga chip (3), be connected with power supply (11), serial FLASH (4) and clock (12), it is characterized in that:
Said host computer is mounted with the Waveform Design simulation software on (1), and the quantity of said slave computer (2) is at least one, and slave computer (2) also comprises signal conditioning circuit (10); Also be connected with RS232 interface (5), Ethernet interface (13) and SDRAM storer (6) on the said fpga chip (3), and in fpga chip (3), be provided with Nios II soft-core processor (7), DDS module (8), dual port RAM (14) and frequency control word register (15);
Said Nios II soft-core processor (7) comprises CPU processor (71), URAT controller (72), sdram controller (73), EPCS controller (74), ethernet controller (75), a PIO controller (76) and No. two PIO controllers (77); CPU processor (71) is connected with RS232 interface (5), SDRAM storer (6), serial FLASH (4), Ethernet interface (13) communication respectively through URAT controller (72), sdram controller (73), EPCS controller (74), ethernet controller (75); The other end of RS232 interface (5), Ethernet interface (13) all is connected with host computer (1) communication; CPU processor (71) is connected with dual port RAM (14) through a PIO controller (76); The other end of dual port RAM (14) is connected with DDS module (8), DA converter circuit (9) respectively; The other end of DDS module (8) is connected with CPU processor (71) through frequency control word register (15), No. two PIO controllers (77) successively, and the other end of DA converter circuit (9) is connected with signal conditioning circuit (10).
2. a kind of half signal generator in kind according to claim 1, it is characterized in that: said host computer (1) is a PC, said fpga chip (3) adopts Cyclone, Cyclone II or the Cyclone III family chip of altera corp.
3. a kind of half signal generator in kind according to claim 1 and 2; It is characterized in that: said DA converter circuit (9) comprises a high-speed D (91) and a low-speed highly precise DA converter (92); One end of high-speed D (91) is connected with dual port RAM (14); The other end is connected with signal conditioning circuit (10); One end of low-speed highly precise DA converter (92) is connected with dual port RAM (14), and the other end is as the reference source input of high-speed D (91).
4. a kind of half signal generator in kind according to claim 1 and 2; It is characterized in that: said signal conditioning circuit (10) comprises fixed gain amplifier, LC wave filter and power amplifier, and this fixed gain amplifier is connected with the other end of high-speed D (91).
5. the method for application of described half signal generator in kind of a claim 1 is characterized in that this method of application may further comprise the steps successively:
The first step: earlier the Waveform Design simulation software that loads in the host computer (1) is provided with; Its method to set up comprises that the interface manually is provided with and routine call is provided with automatically, and it is provided with content and comprises: COM1, signal type, amplitude, frequency, phase place and high-low level; Said COM1 comprises RS232 interface (5) or Ethernet interface (13), and said signal type comprises sine wave, triangular wave and the square wave in the reference waveform;
Second the step: above-mentioned end of text is set after; On the screen of host computer (1), demonstrate simulation waveform again; If the simulation waveform that shows meets the requirements; Then generate the required module parameter of DDS module (8) in the slave computer (2) by this Waveform Design simulation software, this module parameter comprises waveform ROM table data, phase accumulator initial value and amplitude control signal, through RS232 interface (5) or Ethernet interface (13) this module parameter is sent to slave computer (2) then;
The 3rd step: first energized (11); Through serial FLASH (4) fpga chip (3) is configured again; And Nios II soft-core processor (7) is carried out program load, the module parameter that sends through RS232 interface (5) or Ethernet interface (13) reception host computer (1) by Nios II soft-core processor (7) then, and this module parameter deposited in the SDRAM storer (6); Carry out computing by CPU processor (71) again; Digital signal with the computing gained deposits in the dual port RAM (14) then, and cooperates with DDS module (8) this digital signal is passed to DA converter circuit (9), converts this digital signal into simulating signal by DA converter circuit (9) again; Handled by signal conditioning circuit (10) then, can obtain final signal this moment.
6. the method for application of a kind of half signal generator in kind according to claim 6; It is characterized in that: in the said first step computing and the modulation that content also comprises signal be set; Its method to set up is: accomplish earlier the setting of two groups of signals, select compute mode again, this compute mode comprises and adding, subtracts, multiplication is modulated with signal; Confirm then, get final product the computing of end signal and the setting of modulation.
7. according to claim 5 or 6 described a kind of partly method of application of signal generators in kind; It is characterized in that: in the said first step, when adopting the manual set-up mode in interface, its signal type also comprises random waveform; The set-up mode of this random waveform is: open waveform earlier and draw panel; Draw the waveform that manual drawing is wanted in the panel with mouse at waveform again, click then and accomplish, can finish the setting of random waveform.
8. according to the method for application of claim 5 or 6 described a kind of half signal generators in kind, it is characterized in that: in the said first step, the maximal value of amplitude is 5V, and frequency is 0.1Hz – 10MHz.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103645665A (en) * | 2013-12-24 | 2014-03-19 | 南京富士通南大软件技术有限公司 | Programmable signal generator and signal generation method thereof |
| CN104569020A (en) * | 2013-10-29 | 2015-04-29 | 中南大学 | Photoelectron spectrometer signal source |
| CN104965200A (en) * | 2015-07-09 | 2015-10-07 | 国家海洋技术中心 | Towed underwater acoustic signal transmitting system-based dynamic signal generation device |
| CN105116183A (en) * | 2015-08-24 | 2015-12-02 | 中国科学院微电子研究所 | Multichannel waveform signal generator |
| CN106444962A (en) * | 2016-11-30 | 2017-02-22 | 桂林电子科技大学 | Drawing random waveform signal generator |
| CN110442185A (en) * | 2019-07-09 | 2019-11-12 | 深圳市鼎阳科技有限公司 | A kind of waveform sequence generator |
| CN110456656A (en) * | 2019-07-08 | 2019-11-15 | 许继电气股份有限公司 | EMTDC simulator, EMTDC analogue system and its emulation mode |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101605048A (en) * | 2008-06-11 | 2009-12-16 | 北京泰美世纪科技有限公司 | Mobile TV transmitting terminal is carried out the mthods, systems and devices of network management |
| CN101795019A (en) * | 2010-01-19 | 2010-08-04 | 东南大学 | Soft core based merging unit of photoelectric current transformers |
| CN102012209A (en) * | 2010-09-29 | 2011-04-13 | 北京京海泉传感科技有限公司 | Digital transmission demodulating method of differential transformer displacement transducer |
-
2011
- 2011-08-19 CN CN201110239506.4A patent/CN102426472B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101605048A (en) * | 2008-06-11 | 2009-12-16 | 北京泰美世纪科技有限公司 | Mobile TV transmitting terminal is carried out the mthods, systems and devices of network management |
| CN101795019A (en) * | 2010-01-19 | 2010-08-04 | 东南大学 | Soft core based merging unit of photoelectric current transformers |
| CN102012209A (en) * | 2010-09-29 | 2011-04-13 | 北京京海泉传感科技有限公司 | Digital transmission demodulating method of differential transformer displacement transducer |
Non-Patent Citations (4)
| Title |
|---|
| 《电子测量技术》 20110131 刘畅 等 "基于LabVIEW和SOPC的任意波形发生器设计" 第66-68页 1-5 第34卷, 第1期 * |
| 《西华大学学报（自然科学版）》 20090331 牟涛 等 "基于LabVIEW和SOPC技术的信号发生系统" 第21-24页 1-5 第28卷, 第2期 * |
| 刘畅 等: ""基于LabVIEW和SOPC的任意波形发生器设计"", 《电子测量技术》 * |
| 牟涛 等: ""基于LabVIEW和SOPC技术的信号发生系统"", 《西华大学学报（自然科学版）》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104569020A (en) * | 2013-10-29 | 2015-04-29 | 中南大学 | Photoelectron spectrometer signal source |
| CN103645665A (en) * | 2013-12-24 | 2014-03-19 | 南京富士通南大软件技术有限公司 | Programmable signal generator and signal generation method thereof |
| CN104965200A (en) * | 2015-07-09 | 2015-10-07 | 国家海洋技术中心 | Towed underwater acoustic signal transmitting system-based dynamic signal generation device |
| CN104965200B (en) * | 2015-07-09 | 2017-04-05 | 国家海洋技术中心 | Dynamic Signal generating means based on pull-type underwater sound signal emission system |
| CN105116183A (en) * | 2015-08-24 | 2015-12-02 | 中国科学院微电子研究所 | Multichannel waveform signal generator |
| CN106444962A (en) * | 2016-11-30 | 2017-02-22 | 桂林电子科技大学 | Drawing random waveform signal generator |
| CN110456656A (en) * | 2019-07-08 | 2019-11-15 | 许继电气股份有限公司 | EMTDC simulator, EMTDC analogue system and its emulation mode |
| CN110456656B (en) * | 2019-07-08 | 2022-08-16 | 许继电气股份有限公司 | EMTDC (electro-magnetic transient DC) simulation device, EMTDC simulation system and simulation method thereof |
| CN110442185A (en) * | 2019-07-09 | 2019-11-12 | 深圳市鼎阳科技有限公司 | A kind of waveform sequence generator |
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