CN102412357B - LED (light-emitting diode) of thin film structure - Google Patents
LED (light-emitting diode) of thin film structure Download PDFInfo
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- CN102412357B CN102412357B CN201010292342.7A CN201010292342A CN102412357B CN 102412357 B CN102412357 B CN 102412357B CN 201010292342 A CN201010292342 A CN 201010292342A CN 102412357 B CN102412357 B CN 102412357B
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Abstract
The invention discloses an LED (light-emitting diode) of a thin film structure. The LED comprises an epitaxial wafer, a bonded substrate and through-hole metal studs, wherein, a first bonded metal layer is arranged on a P-type semiconductor layer of the epitaxial wafer; a concave hole extending to an N-type semiconductor layer is arranged on the epitaxial wafer, and an N electrode is arranged on the surface of the N-type semiconductor layer in the concave hole; the surface of the epitaxial wafer is wrapped with a protection film, and only the first bonded metal layer and the N electrode are exposed; the bonded substrate is provided with a through hole corresponding to the concave hole as well as a second bonded metal layer matched with the first bonded metal layer; the epitaxial wafer is butted with the bonded substrate in a bonding manner; the through-hole metal studs are positioned in the through hole and the concave hole and are in contact with the N electrode to lead out the electrode; and the first bonded metal layer or the second bonded metal layer is led out to be taken as a P electrode. The LED of the thin film structure has the advantages that the chip bonding firmness is strengthened, the heat dissipation area is increased, the thermal resistance is lowered, and current injection is improved; and the N electrode is arranged at the back side of a light emission surface so as to improve the luminous efficiency of the LED.
Description
Technical field
The present invention relates to the chip structure of light-emitting diode, refer in particular to a kind of light-emitting diode of membrane structure.
Background technology
Light-emitting diode has that volume is little, efficiency is high and the advantage such as the life-span is long, in fields such as traffic indication, outdoor panchromatic demonstrations, has a wide range of applications.Especially utilize large-power light-emitting diodes may realize semiconductor solid lighting, cause mankind's revolution of history of throwing light on, thereby become gradually the study hotspot of current person in electronics.The light extraction efficiency of LED refers to the ratio that shines the outer photon that can be produced by electron-hole recombinations for the active area of the photon utilizing and epitaxial wafer of device.In traditional LED device, due to the existence of the factors such as substrate absorbs, electrode stops, the total reflection of exiting surface, light extraction efficiency is conventionally less than 10%, and most photons are limited in device inside cannot outgoing and be transformed into heat, becomes the undesirable element that affects device reliability.For improving light extraction efficiency, make the photon producing in device body be transmitted into more external, and improve device inside thermal characteristics, through years of researches and practice, people have proposed the method that multiple light extraction efficiency improves, such as CURRENT DISTRIBUTION and current-dispersing structure, chip form geometrization structure, surface micro-structure etc.
Conventionally the chip structure of LED be on the substrates such as sapphire successively extension the structure of n type semiconductor layer, active layer, p type semiconductor layer.In addition, on p type semiconductor layer, dispose P electrode, on n type semiconductor layer, dispose N electrode.Final chip can be positive assembling structure, inverted structure, vertical stratification etc.Wherein, as shown in Figure 1, two electrodes of vertical structure LED are respectively in the both sides up and down of active layer for traditional vertical stratification, and electric current almost whole vertical currents is crossed gallium nitride-based epitaxial layer, there is no the electric current of lateral flow.Therefore, resistance reduces, and does not have electric current congested, and CURRENT DISTRIBUTION is even, makes full use of the material of luminescent layer, and the heat that electric current produces reduces, lower voltage, and antistatic effect improves.Its traditional manufacturing process comprises the steps: (to comprise successively n type semiconductor layer, active layer, p type semiconductor layer at Grown on Sapphire Substrates one intermediary layer and gallium nitride-based epitaxial layer, Deng), bonding one conductive support substrate on gallium nitrate based p type semiconductor layer, the stacked P electrode of another side of this conductive support substrate.Utilize Ear Mucosa Treated by He Ne Laser Irradiation on intermediary layer, gallium nitride decomposes, and Sapphire Substrate is Fen Li with gallium nitride-based epitaxial layer, i.e. laser lift-off, the making of then manufacturing N electrode and complete chip structure.Although this traditional vertical stratification is conducive to the heat radiation of great power LED, often more complicated of its manufacturing process, the fastness of bonding conductive support substrate is more difficult control also, is unfavorable for producing the raising of yields.
Therefore, how to break through prior art further improve chip yields, improve chip heat-sinking capability, improve electric current inject, thereby improve light emission rate, remain those skilled in the art's technical task urgently to be resolved hurrily.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of light-emitting diode of membrane structure, improves the luminous efficiency of chip.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of membrane structure light-emitting diode, comprising: epitaxial wafer, bonded substrate and via metal bolt;
Described epitaxial wafer at least comprises n type semiconductor layer, be positioned at active layer on n type semiconductor layer, be positioned at the p type semiconductor layer on active layer; On p type semiconductor layer, be provided with successively transparency conducting layer and reflector; On described reflector, be provided with the first bonding metal layer; Described epitaxial wafer is provided with shrinkage pool, and described shrinkage pool is deep to n type semiconductor layer, and the n type semiconductor layer surface in described shrinkage pool is provided with N electrode; Described epitaxial wafer and transparency conducting layer and reflector be coated with the first insulating protective layer, only described the first bonding metal layer and N electrode are exposed;
In described bonded substrate, be provided with the through hole corresponding with described shrinkage pool; In described bonded substrate, be also provided with the second bonding metal layer matching with described the first bonding metal layer;
Described epitaxial wafer and described bonded substrate link together by the first bonding metal layer and the second bonding metal layer bonding, and the first bonding metal layer or the second bonding metal layer are drawn as P electrode; Described through hole and the shrinkage pool formation cavity that connects, described via metal bolt is arranged in this cavity and N electrode contact, thereby N electrode is drawn.
Wherein, n type semiconductor layer is n type gallium nitride based material layer, and p type semiconductor layer is P type gallium nitride-based material layer, and active layer is multiple quantum well layer; Transparency conducting layer adopts ITO material; The first bonding metal layer and the second bonding metal layer adopt the laminated construction of the high reflecting metal compositions such as Ag, Al, Au, DBR material or DBR and Al, Ag, Au or AlAg alloy.The first insulating protective layer adopts SiO
2material.Described via metal bolt adopts Cu metal material.
As one of preferred version of the present invention, described bonded substrate adopts ceramic substrate.
As another preferred version of the present invention, described bonded substrate adopts Si substrate; At described Si substrate surface, be first enclosed with the second insulating protective layer, then at the second insulating protective layer outer wrapping metal diffusion barrier layer, described the second bonding metal layer is positioned at outside metal diffusion barrier layer.Described the second insulating protective layer adopts SiO
2material, described metal diffusion barrier layer adopts TiN material.
Compared to prior art, beneficial effect of the present invention is: membrane structure light-emitting diode of the present invention has adopted the design of via metal bolt, on the one hand, can make chip integration, increases the bonding fastness of chip, thereby can improve the yields of chip; On the other hand, via metal stud structure gos deep into chip internal, can increase the thermal diffusion area of chip, reduces the thermal resistance of chip, improves electric current and injects, thereby reach the object that improves chip light emitting efficiency; In addition, conventionally the N electrode of inverted structure is all arranged on the growth substrates N type semiconductor face afterwards of peeling off, and this N type semiconductor release surface is exiting surface in fact, how many existence of electrode can affect bright dipping, the N electrode of the present invention's design is drawn from the back side of exiting surface by via metal bolt, can further improve the luminous efficiency of chip, P electrode is to be drawn by side at bonded substrate place in addition, is conducive to the encapsulation of chip.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of light emitting diode with vertical structure traditional in background technology.
Fig. 2 is the cross-sectional view of epitaxial wafer in embodiment mono-.
Fig. 3 is the schematic diagram of bonded substrate in embodiment mono-.
Fig. 4 is the cross-sectional view of membrane structure light-emitting diode chip for backlight unit in embodiment mono-.
Fig. 5 is the cross-sectional view of membrane structure light-emitting diode chip for backlight unit in embodiment bis-.
Description of symbols in figure:
1 growth substrates 2 n type semiconductor layer 3 active layers
4 p type semiconductor layer 5 transparency conducting layer 6 reflector
7 first bonding metal layer 8 N electrode 9 first insulating protective layers
10 second bonding metal layer 11 second insulating protective layer 12 metal diffusion barrier layers
13 via metal bolt 14 Si substrate 15 ceramic substrate
Embodiment
Below in conjunction with accompanying drawing, further illustrate specific embodiment of the invention step, for the accompanying drawing that facilitates illustrating is not proportionally drawn.
Membrane structure light-emitting diode provided by the invention, comprising: epitaxial wafer, bonded substrate and via metal bolt.Wherein, epitaxial wafer at least comprises n type semiconductor layer, is positioned at active layer on n type semiconductor layer, is positioned at the p type semiconductor layer on active layer.On p type semiconductor layer, be provided with transparency conducting layer and reflector, on reflector, be provided with the first bonding metal layer.This epitaxial wafer is provided with shrinkage pool, and described shrinkage pool gos deep in epitaxial wafer, until n type semiconductor layer exposes n type semiconductor layer, the n type semiconductor layer surface of exposing in this shrinkage pool is provided with N electrode; Described epitaxial wafer and transparency conducting layer and reflector be coated with the first insulating protective layer, for the isolation of insulating, only described the first bonding metal layer and N electrode are exposed.In bonded substrate, be provided with the through hole corresponding with above-mentioned shrinkage pool; In this bonded substrate, be also provided with the second bonding metal layer matching with the first bonding metal layer.
Epitaxial wafer and bonded substrate link together by the first bonding metal layer and the second bonding metal layer bonding, by the first bonding metal layer or the second bonding metal layer, as P electrode, draw.Can draw from the side like this P electrode, be conducive to the encapsulation of chip.Wherein, bonding connects through hole and shrinkage pool, and via metal bolt can, by technique integral manufacturings such as evaporations in the cavity of through hole and shrinkage pool formation, with N electrode contact, thereby be drawn N electrode.Utilize via metal bolt to draw N electrode from the back side of exiting surface, can not take the area of the exiting surface of chip, be conducive to the light effect that of chip.In addition, the design of this via metal bolt can also increase the fastness of bonding, and metal bolt has good thermal conductivity, can increase the thermal diffusion area of chip, reduces the thermal resistance of chip.This overall structure is conducive to improve electric current to be injected, thereby effectively improves the luminous efficiency of chip.
Embodiment mono-
Please refer to Fig. 2-4, the present embodiment adopts common Si substrate 14 as bonded substrate.
Fig. 2 is the cross-sectional view of epitaxial wafer, and it is upper that described epitaxial wafer grows in growth substrates 1 (as Sapphire Substrate), comprises n type semiconductor layer 2, active layer 3 and p type semiconductor layer 4.On p type semiconductor layer 4, be provided with transparency conducting layer 5 and reflector 6, on reflector 6, be provided with the first bonding metal layer 7.
Wherein, n type semiconductor layer 2 is preferably n type gallium nitride basic unit, p type semiconductor layer 4 is preferably P type gallium nitride-based material layer, but be not limited only to this, described gallium nitride-based material can be binary, ternary, quaternary compound or the mixture of Ga, In, Al, N composition, as GaN, AlGaN, GaInN, AlGaInN etc.Active layer 3 is preferably multiple quantum well layer, binary, ternary, quaternary compound or mixture that selection can be comprised of Ga, In, Al, N, but be not limited only to this; Transparency conducting layer 5 can adopt ITO material, can be also the other materials with current spread effect.
This epitaxial wafer is provided with shrinkage pool deeply to n type semiconductor layer 2, and n type semiconductor layer 2 is exposed, and n type semiconductor layer 2 surfaces of exposing in this shrinkage pool are provided with N electrode 8.Shrinkage pool in the present embodiment is round taper hole, is conducive to via metal bolt 13 and fully contacts with N electrode 8, and shrinkage pool is darker, and via metal bolt 13 is just larger with the contact area of N electrode 8.
The surface that expose in described epitaxial wafer and transparency conducting layer 5 and reflector 6 is also enclosed with the first insulating protective layer 9; only described the first bonding metal layer 7 and N electrode 8 are exposed; prevent that other parts of via metal bolt 13 and epitaxial wafer from contacting, and protects the naked region being exposed on the external simultaneously.The first insulating protective layer 9 can adopt SiO
2material, but be not limited only to this, can be also other materials with insulation blocking effect.
Fig. 3 is the cross-sectional view of bonded substrate, is provided with the through hole corresponding with above-mentioned shrinkage pool in bonded substrate; In this bonded substrate, be also provided with the second bonding metal layer 10 matching with the first bonding metal layer 7.On bonded substrate (Si substrate 14) surface, be first enclosed with the second insulating protective layer 11, then be positioned at outside metal diffusion barrier layer 12 at the second insulating protective layer 11 outer wrapping metal diffusion barrier layer 12, the second bonding metal layers 10.Described the second insulating protective layer 11 can adopt SiO
2material, for insulation blocking bonded substrate, described metal diffusion barrier layer 12 can adopt TiN material, or other have the material of diffusion barrier effect to metal, for insulation blocking bonded substrate.
By epitaxial wafer (Fig. 2) and bonded substrate (Fig. 3) bonding, the first bonding metal layer 7 and the second bonding metal layer 10 are bonded together, through hole and shrinkage pool connect and form a cavity, then utilize the techniques such as evaporation by via metal bolt 13 integral manufacturings in this cavity, form the chip structure shown in Fig. 4.Via metal bolt 13 contacts with N electrode 8, thereby electrode is drawn.Draw by the second bonding metal layer 10 in reflector 6.In Fig. 4 the second bonding metal layer 10 some be wider than the first bonding metal layer 7 of its below, this part can be used for extraction electrode.Draw from the side P electrode and be conducive to follow-up encapsulation.Wherein, the first bonding metal layer 7 and the second bonding metal layer 10 can adopt the laminated construction of the high reflecting metal compositions such as Ag, Al, Au, DBR (Distributed Bragg Reflectors) material or DBR and Al, Ag, Au or AlAg alloy, can be to pad the metal that a floor height reflects after being first DBR again.Via metal bolt 13 adopts Cu metal material.
Because the easy thermal diffusion of Cu enters in Si material, affect chip performance, therefore adopt especially in the present embodiment TiN material to isolate as metal diffusion barrier layer 12, thereby played the effect of protection Si material, further promote chip performance.
If need to, from n type semiconductor layer 2 bright dippings, make so after said structure, also need laser lift-off growth substrates 1.If but growth substrates 1 adopts Sapphire Substrate, and need to, from Sapphire Substrate bright dipping, so just can not peel off growth substrates 1, thereby simplify manufacture craft.As seen from Figure 4, N electrode 8 is positioned at the back side of chip light-emitting region (release surface or the sapphire growth substrates 1 of n type semiconductor layer 2 and growth substrates 1), by via metal bolt 13, is drawn.
The chip structure finally obtaining, through subsequent techniques such as cutting, encapsulation, can obtain the membrane structure light-emitting diode that light emission rate is higher.
Embodiment bis-
Please refer to Fig. 5, the present embodiment and embodiment mono-adopt essentially identical technical scheme, difference is, the present embodiment has adopted ceramic substrate 15 as bonded substrate, owing to not having the diffusion phenomena of Cu to Si between Cu metal (via metal bolt 13) and ceramic substrate 15, therefore do not need to make SiO
2material the second insulating protective layer and TiN material metal diffusion impervious layer are protected, and make its structure can be simpler.
Other process conditions that relate in the present invention are common process condition, belong to the familiar category of those skilled in the art, do not repeat them here.Above-described embodiment is the unrestricted technical scheme of the present invention in order to explanation only.Any technical scheme that does not depart from spirit and scope of the invention all should be encompassed in the middle of patent claim of the present invention.
Claims (8)
1. a membrane structure light-emitting diode, is characterized in that, comprising: epitaxial wafer, bonded substrate and via metal bolt;
Described epitaxial wafer at least comprises n type semiconductor layer, be positioned at active layer on n type semiconductor layer, be positioned at the p type semiconductor layer on active layer; On p type semiconductor layer, be provided with successively transparency conducting layer and reflector; On described reflector, be provided with the first bonding metal layer; Described epitaxial wafer is provided with shrinkage pool, and described shrinkage pool is deep to n type semiconductor layer, and the n type semiconductor layer surface in described shrinkage pool is provided with N electrode; Described epitaxial wafer and transparency conducting layer and reflector be coated with the first insulating protective layer, only described the first bonding metal layer and N electrode are exposed;
In described bonded substrate, be provided with the through hole corresponding with described shrinkage pool; In described bonded substrate, be also provided with the second bonding metal layer matching with described the first bonding metal layer;
Described epitaxial wafer and described bonded substrate link together by the first bonding metal layer and the second bonding metal layer bonding, and the first bonding metal layer or the second bonding metal layer are drawn as P electrode; Described through hole and the shrinkage pool formation cavity that connects, described via metal bolt is arranged in this cavity and N electrode contact, thereby N electrode is drawn;
Described bonded substrate adopts Si substrate, be first enclosed with the second insulating protective layer, then at the second insulating protective layer outer wrapping metal diffusion barrier layer, described the second bonding metal layer is positioned at outside metal diffusion barrier layer at described Si substrate surface.
2. membrane structure light-emitting diode according to claim 1, is characterized in that: n type semiconductor layer is n type gallium nitride based material layer, and p type semiconductor layer is P type gallium nitride-based material layer, and active layer is multiple quantum well layer.
3. membrane structure light-emitting diode according to claim 1, is characterized in that: transparency conducting layer adopts ITO material.
4. membrane structure light-emitting diode according to claim 1, is characterized in that: the first bonding metal layer and the second bonding metal layer adopt the laminated construction of Ag, Al, Au, DBR material or DBR and Al, Ag, Au or AlAg alloy composition.
5. membrane structure light-emitting diode according to claim 1, is characterized in that: the first insulating protective layer adopts SiO
2material.
6. membrane structure light-emitting diode according to claim 1, is characterized in that: described via metal bolt adopts Cu metal material.
7. membrane structure light-emitting diode according to claim 1, is characterized in that: described the second insulating protective layer adopts SiO
2material.
8. membrane structure light-emitting diode according to claim 1, is characterized in that: described metal diffusion barrier layer adopts TiN material.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010292342.7A CN102412357B (en) | 2010-09-26 | 2010-09-26 | LED (light-emitting diode) of thin film structure |
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| CN201010292342.7A CN102412357B (en) | 2010-09-26 | 2010-09-26 | LED (light-emitting diode) of thin film structure |
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| CN102412357B true CN102412357B (en) | 2014-04-30 |
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| CN103682004B (en) * | 2012-09-07 | 2017-06-06 | 晶能光电（江西）有限公司 | A kind of light emitting diode flip-chip for improving light emission rate and preparation method thereof |
| TWI616004B (en) * | 2013-11-27 | 2018-02-21 | 晶元光電股份有限公司 | Semiconductor light-emitting device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1797795A (en) * | 2004-12-27 | 2006-07-05 | 北京大学 | Method for preparing LED chip with 2D natural scattered faces for outputting light |
| CN101005110A (en) * | 2007-01-12 | 2007-07-25 | 中国科学院上海微系统与信息技术研究所 | Method for realizing gallium nitride ELD vertical structure using metal bounding process |
| CN101488547A (en) * | 2008-12-30 | 2009-07-22 | 上海蓝光科技有限公司 | LED chip construction and manufacturing method thereof |
| CN101640242A (en) * | 2009-08-05 | 2010-02-03 | 上海蓝光科技有限公司 | Manufacturing method for light-emitting diode chip |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1797795A (en) * | 2004-12-27 | 2006-07-05 | 北京大学 | Method for preparing LED chip with 2D natural scattered faces for outputting light |
| CN101005110A (en) * | 2007-01-12 | 2007-07-25 | 中国科学院上海微系统与信息技术研究所 | Method for realizing gallium nitride ELD vertical structure using metal bounding process |
| CN101488547A (en) * | 2008-12-30 | 2009-07-22 | 上海蓝光科技有限公司 | LED chip construction and manufacturing method thereof |
| CN101640242A (en) * | 2009-08-05 | 2010-02-03 | 上海蓝光科技有限公司 | Manufacturing method for light-emitting diode chip |
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