CN102411492B - Data processing method and device - Google Patents
Data processing method and device Download PDFInfo
- Publication number
- CN102411492B CN102411492B CN201110379988.3A CN201110379988A CN102411492B CN 102411492 B CN102411492 B CN 102411492B CN 201110379988 A CN201110379988 A CN 201110379988A CN 102411492 B CN102411492 B CN 102411492B
- Authority
- CN
- China
- Prior art keywords
- data processing
- processing rate
- data
- configuration
- rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Image Processing (AREA)
Abstract
The invention discloses a data processing method and device, which can be used for realizing flexible adjustment of the data processing speed on a hardware pipeline by adopting different data processing speeds on the hardware pipeline. The data processing method provided by the embodiment of the invention comprises the following steps of: allocating the currently used data processing speed; and informing the hardware pipeline of the allocated data processing speed so that the hardware pipeline performs data processing according to the currently allocated data processing speed.
Description
Technical field
The present invention relates to data communication field, particularly relate to a kind of method and apparatus of data processing.
Background technology
Data processing is systems engineering and the automatic basic link of controlling.Data processing comprises collection, storage, retrieval, processing, conversion and the transmission to data.The basic object of data processing from a large amount of, may be that rambling, elusive data, extracting and derive for some specific people is valuable, significant data.Data are a kind of expression-forms to the fact, concept or instruction, can be processed by artificial or automation equipment.The form of data can be numeral, word, figure or sound etc., and data, through after explaining and giving certain meaning, just become information.
While carrying out data processing at present on hardware chip, raw data is left in internal memory, the module cooperative work of respectively processing on hardware pipeline, within each clock period, by read module, read several data in raw data, next module that these data are sent on hardware pipeline is processed, until being disposed to these data.Data after finishing dealing with are write back to internal memory according to the same manner by bus by writing module, form new data.
The form of data of take is that image is example, and in image is processed, raw image data is stored in internal memory frame by frame.Hardware pipeline (by row, by row or by piece) within each clock period reads several pixel datas in original image, the data after finishing dealing with is write back to internal memory according to the same manner, to form the image that a frame is new.
Yet at least there are the following problems for existing data processing scheme:
In existing data handling system, the data volume that hardware pipeline reads within each clock period from internal memory is scheduled to, and data processing rate is fixed in advance, thereby causes the mode of data processing too single, data processing method underaction.
Summary of the invention
The embodiment of the present invention provides a kind of method and apparatus of data processing, can on hardware pipeline, adopt different data processing rate, realizes the flexible adjustment of data processing rate on hardware pipeline.
For achieving the above object, technical scheme of the present invention is achieved in that
The embodiment of the present invention provides a kind of method of data processing, and the method comprises:
Configure presently used data processing rate;
By configured data processing rate notice hardware pipeline, so that hardware pipeline carries out data processing according to current configured data processing rate.
The embodiment of the present invention also provides a kind of device of data processing, and this device comprises:
Speed control module, for configuring presently used data processing rate, and, by current configured data processing rate notice hardware pipeline;
Data processing unit, at hardware pipeline, carries out data processing according to known current configured data processing rate.
From above-mentioned, the technical scheme of the embodiment of the present invention, by a kind of variable data processing rate mechanism is set, can adopt different data processing rate under different condition according to actual conditions, realize the flexible adjustment of data processing rate on hardware pipeline.
Accompanying drawing explanation
Fig. 1 is the method flow schematic diagram of a kind of data processing of providing of the embodiment of the present invention one;
Fig. 2 is that the embodiment of the present invention two provides a kind of schematic flow sheet when view data is processed;
Fig. 3 is the apparatus structure schematic diagram of a kind of data processing of providing of the embodiment of the present invention three;
Fig. 4 is the apparatus structure schematic diagram of the another kind of data processing that provides of the embodiment of the present invention three.
Embodiment
In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with the drawings and specific embodiments, describe the present invention.
The embodiment of the present invention one provides a kind of method of data processing, and referring to Fig. 1, the method comprises:
11: configure presently used data processing rate.
12: by configured data processing rate notice hardware pipeline, so that hardware pipeline carries out data processing according to current configured data processing rate.
Hardware pipeline consists of the each processing unit of mutual collaborative work each other.On hardware pipeline, each processing unit is carried out following data processing according to current configured data processing rate:
13: according to current configured data processing rate, by bus, from internal memory, read raw data;
14: the raw data reading is carried out to corresponding service processing, and the result data obtaining after processing is passed through to bus write memory.
Above-mentioned data processing rate refers to the data volume that on hardware pipeline, per clock period of each processing unit processes.Clock period refers to the synchronizing signal of digital circuit, and it is the minimum time unit of data circuit work.
If the each processing unit on hardware pipeline reads and process N data in 1 clock period, data processing rate is N.If the every N of the each processing unit on hardware pipeline clock period processed 1 data, data processing rate is 1/N.
In above-mentioned steps 11, correlation unit or the device that can arrange by the function software moving on hardware chip on several data processing speed control hardware streamline move according to set data processing rate, also can directly by the correlation unit on adjustment hardware pipeline or the pin setting of device, realize variable data processing rate.
From above-mentioned, the technical scheme of the embodiment of the present invention, by a kind of variable data processing rate mechanism is set, can adopt different data processing rate under different condition according to actual conditions, realize the flexible adjustment of data processing rate on hardware pipeline.
The method of the data processing below embodiment of the present invention two being provided describes.The present embodiment mainly be take scene that need data to be processed are view data and is described as example.
11: configure presently used data processing rate.
The preferred data processing rate M that adopts software that variable pixel is set in the embodiment of the present invention, as utilize the CPU on hardware chip to adopt the mode of software control to configure presently used data processing rate for M, the each processing unit on hardware pipeline reads the mode of M pixel according to each clock period, and the data processing rate that realizes pixel is adjustable.This setup has been avoided the change to hardware, and compatible existing hardware equipment, has higher feasibility preferably, and set-up mode is also convenient more flexibly.
Concrete, the data processing rate in the present embodiment refers to processed pixels data volume in per clock period of hardware pipeline.On hardware pipeline, allow and support multiple different data processing rate.
For example, each processing unit on hardware pipeline reads and processes 1 pixel in every 1 clock period, data processing rate M is 1 o'clock, if software configuration data processing speed M is 2, the relevant treatment unit (as data-reading unit) on hardware pipeline can improve the data volume at every turn reading, and each clock period reads 2 pixels and processes.If software configuration data processing speed M is 1/2, the each processing unit on hardware pipeline can be counted the clock period, and every 2 clock period read 1 pixel and process.
The factor of above-mentioned configuration mode institute foundation comprise that the power consumption of system requires and hardware pipeline on the congestion condition of clock frequency, bus and service priority, internal memory in one or more in the processing speed of result data in the generating rate of raw data and internal memory.From this four aspect, explanation configures the concrete grammar of presently used data processing rate respectively below:
The power consumption requirement of system and the clock frequency on hardware pipeline
Power consumption requirement in different system and the power consumption under same system different application scene require normally different, can utilize the power consumption requirement after change, configure presently used data processing rate.At this, in conjunction with power consumption, require and two factor configuration data processing speeds of clock frequency, mainly consider when change that power consumption requires causes clock frequency to change, can adapt to by changing data processing rate the change of power consumption, so cause power consumption to require the factor changing no longer to discuss in detail at this to other.
When the change requiring when system power dissipation in the present embodiment causes the clock frequency on hardware pipeline to change, configure presently used data processing rate and meet required data volume processing power.
In the situation that data volume processing power remains unchanged, if the clock frequency on current configuration moment hardware pipeline is lower than the clock frequency on the first configuration hardware pipeline constantly, configure presently used data processing rate higher than the first corresponding data processing rate of the configuration moment, otherwise, configure presently used data processing rate lower than the first corresponding data processing rate of the configuration moment.
The first configuration can be the moment before current configuration constantly constantly, can be also the moment after current configuration constantly.In this case, for keeping certain data-handling capacity, when system requirements reduces power consumption and causes the slowing of clocks, improve the data volume that per clock period reads, when system can tolerate that larger power consumption improves clock frequency, reduce the data volume that per clock period reads.
The concrete numerical value of the data processing rate configuring can be determined according to the variable quantity of the data-handling capacity that will keep and clock frequency.
The congestion condition of bus and service priority
According to the congestion control requirement of bus and the service priority of current business, configure presently used data processing rate and meet service priority and congestion control requirement.
The congestion control of above-mentioned bus requires as not allowing the congestion condition differentiation amount of bus to surpass congested discrimination threshold, the congestion condition of bus is arranged to congestion state differentiation amount, and the tolerable congested discrimination threshold of the system that arranges, when congestion condition differentiation amount surpasses congested discrimination threshold, represent that the congestion situation in bus is more serious, need to adopt the measure of alleviate congestion.
When utilizing the change alleviate congestion of data processing rate, also need the priority that factor is exactly business of considering, when service priority is higher, for example, current business is the business of relatively paying close attention to, do not advise carrying out alleviate congestion by reducing the data processing rate of this business, only have when service priority is lower, for example, the service priority of current business is lower than level threshold, be the attention rate of current business when lower, just by reducing the data processing rate of this business, carry out alleviate congestion.
If inscribe the congestion condition differentiation amount of bus during current configuration, surpass congested discrimination threshold, and the service priority of current business is lower than level threshold, and the congestion condition differentiation amount that first when configuration inscribed bus is lower than congested discrimination threshold, configure presently used data processing rate lower than the first configuration corresponding data processing rate constantly.
Utilize above-mentioned congestion state to differentiate when scale is levied current configuration and inscribe the congestion situation of bus, this congestion state differentiation amount can be the statistical value to a period of time internal bus congestion situation.The concrete value of above-mentioned congested discrimination threshold can arrange as required flexibly.
If judge current bus in congestion condition, and a plurality of equipment is need to access bus time, at this moment reduces data processing rate, just whole need data volume to be processed on average can be arrived in the longer time period, avoids increasing the weight of the congested of bus.
The generating rate of raw data in internal memory
According to the generating rate of raw data in internal memory, configure the generating rate that presently used data processing rate is not less than described raw data.
Concrete, if inscribe the generating rate of raw data in internal memory when the data processing rate that a upper configuration is used is constantly not less than current configuration, the data processing rate that the data processing rate of a upper configuration being used constantly is constantly used as current configuration, otherwise, increase the data processing rate that a upper configuration constantly used until inscribe the generating rate of raw data in internal memory, the data processing rate that the data processing rate that the upper configuration after increasing is used was constantly used as the current configuration moment while being not less than current configuration.
In this case, when the generating rate of raw data accelerates, this programme can improve data processing rate, when the generating rate of raw data is slack-off, reduces data processing rate, thereby has both met the requirement of data processing, has reduced again the power consumption of system.
The processing speed of result data in internal memory
According to the processing speed of result data in internal memory, configure the processing speed that presently used data processing rate is not more than described result data.
Concrete, the processing speed of inscribing result data in internal memory when if the data processing rate that a upper configuration is used is constantly not more than current configuration, the data processing rate that the data processing rate of a upper configuration being used constantly is constantly used as current configuration, otherwise, reduce the data processing rate that a upper configuration constantly used until the processing speed of inscribing result data in internal memory while being not more than current configuration, the data processing rate that the data processing rate that the upper configuration after reducing is used constantly is constantly used as current configuration.
In this case, follow-up can be very fast processed when complete when result data, the data processing rate on hardware pipeline can be improved, thereby the processing speed of data integral body can be improved; When result data is when follow-up processing speed is slower, can reduce the data processing rate on hardware pipeline, with the overlong time of avoiding pending data to wait for, increase internal memory burden.
When configuration data processing speed, can consider separately above-mentioned a kind of factor, also two or more above-mentioned combined factors can be considered together.
12: by configured data processing rate notice hardware pipeline;
Setting up CPU is connected between the first processing unit with on hardware pipeline and on this first processing unit, command interface is set;
By CPU, to described processing first module transmission configuration order and described the first processing unit, utilize command interface to receive this configuration order, by the first processing unit on configured data processing rate notice hardware pipeline, when the first processing unit is known current configured data processing rate and carry out data processing according to this data processing rate, due to each processing unit collaborative work on hardware pipeline, the all processing units on hardware pipeline all carry out data processing according to this data processing rate, shown in the content of stating in step 13 and 14 specific as follows.
13: according to current configured data processing rate, by bus, from internal memory, read raw data;
According to configured data processing rate, the processing unit on hardware pipeline reads the raw data of corresponding data amount from internal memory.
14: the raw data reading is carried out to corresponding service processing, and the result data obtaining after processing is passed through to bus write memory.
Referring to Fig. 2, shown the schematic flow sheet when embodiment of the present invention is processed view data.Below in conjunction with Fig. 2, to above-mentioned steps 11, the disposal route to step 13 describes.
In the present embodiment, the processing procedure of view data is split as and comprises following a plurality of step: as read, denoising, convergent-divergent, level and smooth, color conversion and write back etc., and by a plurality of hardware handles unit, executed in parallel is carried out speed up processing.Preferably, speed is set in reading unit and adjusts function, on reading unit, there is command interface, receive configuration order, through-rate is controlled function and by bus, from internal memory, is read raw data according to the indicated data processing rate of configuration order, be sent to denoising unit and process, and pass through unit for scaling successively, the processing of smooth unit, color conversion cell etc., obtain result data.This result data is sent to and writes back unit, by writing back unit, result data is passed through to bus write memory, to utilize result data again to form a new two field picture.
The processing speed of above-mentioned each unit can be identical, and for example, the processing speed of each unit, all according to current configured data processing rate, is consistent data processing rate, and data processing path is more reasonable; Or the processing speed of above-mentioned each unit also can be different, at this moment, the processing speed that requires unit for scaling, smooth unit, color conversion cell and write back unit etc. is not less than configured data processing rate, is not less than the data read rates of reading unit.
For example, unit for scaling, smooth unit, color conversion cell and write back unit etc. according to first rate, the raw data reading is carried out to respective handling, and the result data obtaining after processing is passed through to bus write memory, wherein, described first rate is not less than current configured data processing rate (being the data read rates of reading unit).
Further, the maximum data processing speed in each data processing rate configuring in this programme need to be less than the maximum data processing speed of supporting on hardware pipeline, to guarantee the successful execution of data processing.
From the above mentioned, this programme is the processing time of unit data on control hardware streamline rationally, meets the multiple requirement of data processing, avoids the sudden congested of bus, improves the overall performance of hardware chip.
The embodiment of the present invention three also provides a kind of device of data processing, and referring to Fig. 3, this device comprises:
Further, each data processing unit comprises the first processing unit, and this first processing unit is provided with command interface.This first processing unit can be realized by the data-reading unit on hardware pipeline.
Referring to Fig. 4, described speed control module 31 also comprises connecting sets up unit 311, for setting up being connected between speed control module and described the first processing unit,
Described speed control module 31, specifically for configuring presently used data processing rate, and, by described connection, to the first processing unit, send configuration order, by several the first processing units on current configured data processing rate notice hardware pipeline;
Described the first processing unit, receives configuration order by this command interface, knows current configured data processing rate.
Further, the first processing unit can be realized by the data-reading unit 321 on hardware pipeline, and above-mentioned data processing unit 32 comprises as lower unit:
Described data-reading unit 321, be provided with command interface, for receiving configuration order by this command interface, according to indicated current the configured data processing rate of configuration order, by bus, from internal memory, read raw data, and this raw data is sent to Service Processing Unit 322;
Described Service Processing Unit 322, carries out corresponding service processing for the raw data to from data-reading unit, and the result data obtaining after processing is sent to data write unit 323;
Described data write unit 323, for passing through bus write memory by described result data.
Further, described speed control module 31, specifically on hardware pipeline, at least two kinds of different data processing rate are set, when the change of system power dissipation requirement causes the clock frequency variation on hardware pipeline, configure presently used data processing rate and meet required data volume processing power; And/or,
Described speed control module 31, specifically on hardware pipeline, at least two kinds of different data processing rate are set, according to the congestion control requirement of bus and the service priority of current business, configure presently used data processing rate and meet service priority and congestion control requirement; And/or,
Described speed control module 31, specifically on hardware pipeline, at least two kinds of different data processing rate are set, according to the generating rate of raw data in internal memory, configure the generating rate that presently used data processing rate is not less than described raw data; And/or,
Described speed control module 31, specifically on hardware pipeline, at least two kinds of different data processing rate are set, according to the processing speed of result data in internal memory, configure the processing speed that presently used data processing rate is not more than described result data.
Concrete, speed control module 31, when carrying out the configuration of data processing rate according to above-mentioned configuration mode, can specifically comprise at least one following operation:
Described speed control module 31, specifically in the situation that data volume processing power remains unchanged, if the clock frequency on current configuration moment hardware pipeline is lower than the clock frequency on the first configuration hardware pipeline constantly, configure presently used data processing rate higher than the first corresponding data processing rate of the configuration moment, otherwise, configure presently used data processing rate lower than the first corresponding data processing rate of the configuration moment, and, by current configured data processing rate notification data processing unit;
And/or,
Described speed control module 31, specifically for the congestion control when bus, require as not allowing the congestion condition differentiation amount of bus to surpass congested discrimination threshold, if inscribe the congestion condition differentiation amount of bus during current configuration, surpass congested discrimination threshold, and the service priority of current business is lower than level threshold, and the congestion condition differentiation amount that first when configuration inscribed bus is lower than congested discrimination threshold, configure presently used data processing rate lower than the first corresponding data processing rate of the configuration moment, and, by current configured data processing rate notification data processing unit, and/or
Described speed control module 31, if inscribe the generating rate of raw data in internal memory when the data processing rate of constantly using specifically for a upper configuration is not less than current configuration, the data processing rate that the data processing rate of a upper configuration being used constantly is constantly used as current configuration, otherwise, increase the data processing rate that a upper configuration constantly used until inscribe the generating rate of raw data in internal memory while being not less than current configuration, the data processing rate that the data processing rate that a upper configuration after increasing is used constantly is constantly used as current configuration, and, by current configured data processing rate notification data processing unit, and/or,
Described speed control module 31, the processing speed of inscribing result data in internal memory when if the data processing rate of constantly using specifically for a upper configuration is not more than current configuration, the data processing rate that the data processing rate of a upper configuration being used constantly is constantly used as current configuration, otherwise, reduce the data processing rate that a upper configuration constantly used until the processing speed of inscribing result data in internal memory while being not more than current configuration, the data processing rate that the data processing rate that a upper configuration after reducing is used constantly is constantly used as current configuration, and, by current configured data processing rate notification data processing unit.
Further, described speed control module 31, also, specifically for when configuring presently used data processing rate, the maximum data processing speed in the data processing rate configuring is less than the maximum data processing speed of supporting on hardware pipeline.
The speed of above-mentioned data-reading unit reading out data and Service Processing Unit, data write unit are processed or the speed of data writing can be identical, also can be different, for example: described Service Processing Unit, specifically for according to first rate, raw data from data-reading unit is carried out to corresponding service processing, the result data obtaining after processing is sent to data write unit; Described data write unit, specifically for according to first rate, passes through bus write memory by described result data; Wherein, described first rate is not less than the data processing rate that described speed control module is current configured (being not less than the speed of data-reading unit reading out data).
Above-mentioned each unit can be realized separately, also some unit can be integrated to realization.Exemplary, above-mentioned speed control module can be realized in the CPU of hardware chip.
From above-mentioned, the technical scheme of the embodiment of the present invention, by a kind of variable data processing rate mechanism is set, can adopt different data processing rate under different condition according to actual conditions, realize the flexible adjustment of data processing rate on hardware pipeline.
This programme is the processing time of unit data on control hardware streamline rationally, meets the multiple requirement of data processing, avoids the sudden congested of bus, improves the overall performance of hardware chip.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (8)
1. a method for data processing, is characterized in that, the method comprises:
Configure presently used data processing rate;
By configured data processing rate notice hardware pipeline, so that hardware pipeline carries out data processing according to current configured data processing rate;
The presently used data processing rate of described configuration comprises:
When the change of system power dissipation requirement causes the clock frequency variation on hardware pipeline, configure presently used data processing rate and meet required data volume processing power, particularly, in the situation that data volume processing power remains unchanged, if the clock frequency on current configuration moment hardware pipeline is lower than the clock frequency on the first configuration hardware pipeline constantly, configure presently used data processing rate higher than the first corresponding data processing rate of the configuration moment, otherwise, configure presently used data processing rate lower than the first corresponding data processing rate of the configuration moment, and/or,
According to the congestion control requirement of bus and the service priority of current business, configure presently used data processing rate and meet service priority and congestion control requirement, particularly, the congestion control of described bus requires as not allowing the congestion condition differentiation amount of bus to surpass congested discrimination threshold, if inscribe the congestion condition differentiation amount of bus during current configuration, surpass congested discrimination threshold, and the service priority of current business is lower than level threshold, and the congestion condition differentiation amount that first when configuration inscribed bus is lower than congested discrimination threshold, configure presently used data processing rate lower than the first corresponding data processing rate of the configuration moment, and/or
According to the generating rate of raw data in internal memory, configure the generating rate that presently used data processing rate is not less than described raw data, particularly, if inscribe the generating rate of raw data in internal memory when the data processing rate that a upper configuration is used is constantly not less than current configuration, the data processing rate that the data processing rate of a upper configuration being used constantly is constantly used as current configuration, otherwise, increase the data processing rate that a upper configuration constantly used until inscribe the generating rate of raw data in internal memory while being not less than current configuration, the data processing rate that the data processing rate that a upper configuration after increasing is used constantly is constantly used as current configuration, and/or,
According to the processing speed of result data in internal memory, configure the processing speed that presently used data processing rate is not more than described result data, particularly, the processing speed of inscribing result data in internal memory when if the data processing rate that a upper configuration is used is constantly not more than current configuration, the data processing rate that the data processing rate of a upper configuration being used constantly is constantly used as current configuration, otherwise, reduce the data processing rate that a upper configuration constantly used until the processing speed of inscribing result data in internal memory while being not more than current configuration, the data processing rate that the data processing rate that a upper configuration after reducing is used constantly is constantly used as current configuration.
2. method according to claim 1, is characterized in that,
The presently used data processing rate of described configuration comprises:
Utilize the CPU on hardware chip to configure presently used data processing rate;
Described configured data processing rate notice hardware pipeline is comprised:
On described hardware pipeline, be provided with the first processing unit, set up CPU and being connected and on the first processing unit, command interface being set between the first processing unit on hardware pipeline;
CPU sends configuration order to described the first processing unit;
Described command interface receives this configuration order, so that the first processing unit is known current configured data processing rate.
3. method according to claim 1, is characterized in that, described hardware pipeline carries out data processing according to current configured data processing rate and comprises:
According to current configured data processing rate, by bus, from internal memory, read raw data; The raw data reading is carried out to corresponding service processing, and the result data obtaining is passed through to bus write memory.
4. method according to claim 1, is characterized in that, the maximum data processing speed in the data processing rate configuring is less than the maximum data processing speed of supporting on hardware pipeline.
5. a device for data processing, is characterized in that, this device comprises:
Speed control module, for configuring presently used data processing rate, and, by current configured data processing rate notice hardware pipeline;
Data processing unit, at hardware pipeline, carries out data processing according to known current configured data processing rate;
Described speed control module is specifically for configuring in the following way presently used data processing rate:
Described speed control module, while causing the clock frequency variation on hardware pipeline for the change requiring when system power dissipation, configure presently used data processing rate and meet required data volume processing power, particularly, in the situation that data volume processing power remains unchanged, if the clock frequency on current configuration moment hardware pipeline is lower than the clock frequency on the first configuration hardware pipeline constantly, configure presently used data processing rate higher than the first corresponding data processing rate of the configuration moment, otherwise, configure presently used data processing rate lower than the first corresponding data processing rate of the configuration moment, and, by current configured data processing rate notification data processing unit, and/or,
Described speed control module, be used for according to the congestion control requirement of bus and the service priority of current business, configure presently used data processing rate and meet service priority and congestion control requirement, particularly, when the congestion control of bus requires as not allowing the congestion condition differentiation amount of bus to surpass congested discrimination threshold, if inscribe the congestion condition differentiation amount of bus during current configuration, surpass congested discrimination threshold, and the service priority of current business is lower than level threshold, and the congestion condition differentiation amount that first when configuration inscribed bus is lower than congested discrimination threshold, configure presently used data processing rate lower than the first corresponding data processing rate of the configuration moment, and, by current configured data processing rate notification data processing unit, and/or,
Described speed control module, be used for according to the generating rate of internal memory raw data, configure the generating rate that presently used data processing rate is not less than described raw data, particularly, if inscribe the generating rate of raw data in internal memory when the data processing rate that a upper configuration is used is constantly not less than current configuration, the data processing rate that the data processing rate of a upper configuration being used constantly is constantly used as current configuration, otherwise, increase the data processing rate that a upper configuration constantly used until inscribe the generating rate of raw data in internal memory while being not less than current configuration, the data processing rate that the data processing rate that a upper configuration after increasing is used constantly is constantly used as current configuration, and, by current configured data processing rate notification data processing unit, and/or,
Described speed control module, be used for according to the processing speed of internal memory result data, configure the processing speed that presently used data processing rate is not more than described result data, particularly, the processing speed of inscribing result data in internal memory when if the data processing rate that a upper configuration is used is constantly not more than current configuration, the data processing rate that the data processing rate of a upper configuration being used constantly is constantly used as current configuration, otherwise, reduce the data processing rate that a upper configuration constantly used until the processing speed of inscribing result data in internal memory while being not more than current configuration, the data processing rate that the data processing rate that a upper configuration after reducing is used constantly is constantly used as current configuration, and, by current configured data processing rate notification data processing unit.
6. install according to claim 5, it is characterized in that,
Described data processing unit comprises the first processing unit, and this first processing unit is provided with command interface; Described speed control module also comprises connecting sets up unit, for setting up being connected between speed control module and described the first processing unit,
Described speed control module, specifically for configuring presently used data processing rate, and, by described connection, to the first processing unit, send configuration order, by the first processing unit on current configured data processing rate notice hardware pipeline;
Described the first processing unit, receives configuration order by this command interface, knows current configured data processing rate.
7. install according to claim 6, it is characterized in that, described the first processing unit is data-reading unit, and described data processing unit also comprises Service Processing Unit and data write unit:
Described data-reading unit, be provided with command interface, for receiving configuration order by this command interface, according to indicated current the configured data processing rate of configuration order, by bus, from internal memory, read raw data, and this raw data is sent to Service Processing Unit;
Described Service Processing Unit, carries out corresponding service processing for the raw data to from data-reading unit, and the result data obtaining is sent to data write unit;
Described data write unit, for passing through bus write memory by described result data.
8. device according to claim 5, is characterized in that,
Described speed control module, also, specifically for when configuring presently used data processing rate, the maximum data processing speed in the data processing rate configuring is less than the maximum data processing speed of supporting on hardware pipeline.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110379988.3A CN102411492B (en) | 2011-11-25 | 2011-11-25 | Data processing method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110379988.3A CN102411492B (en) | 2011-11-25 | 2011-11-25 | Data processing method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102411492A CN102411492A (en) | 2012-04-11 |
| CN102411492B true CN102411492B (en) | 2014-04-23 |
Family
ID=45913581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110379988.3A Expired - Fee Related CN102411492B (en) | 2011-11-25 | 2011-11-25 | Data processing method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102411492B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103685890B (en) * | 2013-12-05 | 2017-04-05 | 华南理工大学 | The smart camera and its method for dynamic reconfiguration of dynamic recognition image processing function |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6081886A (en) * | 1997-04-03 | 2000-06-27 | Nec Corporation | Holding mechanism for changing operation modes in a pipelined computer |
| CN101464721A (en) * | 2007-12-19 | 2009-06-24 | 国际商业机器公司 | Method and system for controlling power consumption of pipeline processor |
| CN101520725A (en) * | 1999-12-23 | 2009-09-02 | 英特尔公司 | Microprocessor with digital power throttle |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW334546B (en) * | 1996-03-18 | 1998-06-21 | Hitachi Ltd | Data processor |
| JP3498678B2 (en) * | 2000-05-31 | 2004-02-16 | 日本電気株式会社 | Pipeline processing type shaping apparatus and method |
-
2011
- 2011-11-25 CN CN201110379988.3A patent/CN102411492B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6081886A (en) * | 1997-04-03 | 2000-06-27 | Nec Corporation | Holding mechanism for changing operation modes in a pipelined computer |
| CN101520725A (en) * | 1999-12-23 | 2009-09-02 | 英特尔公司 | Microprocessor with digital power throttle |
| CN101464721A (en) * | 2007-12-19 | 2009-06-24 | 国际商业机器公司 | Method and system for controlling power consumption of pipeline processor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102411492A (en) | 2012-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104160384B (en) | For the system and method for dynamic priority control | |
| CN1026733C (en) | Multi-media signal processor computer system | |
| CN111258737B (en) | Resource scheduling method and device and filter scheduler | |
| JP5270077B2 (en) | Arbitration circuit, crossbar, request selection method, and information processing apparatus | |
| CN101957800A (en) | Multichannel cache distribution method and device | |
| JP2006318139A (en) | Data transfer device, data transfer method and program | |
| CN102541779A (en) | System and method for improving direct memory access (DMA) efficiency of multi-data buffer | |
| CN103353851A (en) | Method and equipment for managing tasks | |
| JP2007524917A (en) | System and method for selectively influencing data flow to and from a memory device | |
| CN103107923A (en) | Fiber channel (FC) network data monitoring system and method based on system on chip (SOC) technology | |
| CN102411492B (en) | Data processing method and device | |
| CN107222357A (en) | A kind of device and method for configuring network interface card | |
| CN107066413A (en) | A kind of method and its bus system for being used to handle multiple bus apparatus data | |
| CN1477532A (en) | Device for controlling interior storage of chip and its storage method | |
| CN101860894A (en) | System, method and mobile terminal for communication between mobile terminal processors | |
| CN214586880U (en) | Information processing apparatus | |
| CN104461971A (en) | Data collecting control system and method | |
| CN114328350A (en) | Communication method, device and medium based on AXI bus | |
| CN103581050A (en) | Ethernet data aggregation method | |
| CN101324863B (en) | Device and method for controlling synchronous static memory | |
| CN105528319B (en) | FPGA-based accelerator card and acceleration method thereof | |
| CN115981893A (en) | Message queue task processing method and device, server and storage medium | |
| CN214205739U (en) | General type high definition display system based on FPGA for photoelectric platform | |
| CN109753459A (en) | A kind of high capacity data record device | |
| CN104486257A (en) | Graded sending dispatching circuit structure based on AFDX network switch chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20151020 Address after: 100080, Zhongguancun street, 11, Beijing world wealth center, A block, 12 floor Patentee after: BEIJING BOXIN SHITONG TECHNOLOGY CO., LTD. Patentee after: Beijing Chuangyi Vision Technology Co., Ltd. Address before: 100084, A, building 8, building 1, Tsinghua Science and Technology Park, No. Zhongguancun East Road, Haidian District, Beijing Patentee before: Beijing Chuangyi Vision Technology Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140423 Termination date: 20191125 |