CN101324863B - Device and method for controlling synchronous static memory - Google Patents
Device and method for controlling synchronous static memory Download PDFInfo
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- CN101324863B CN101324863B CN2007101109656A CN200710110965A CN101324863B CN 101324863 B CN101324863 B CN 101324863B CN 2007101109656 A CN2007101109656 A CN 2007101109656A CN 200710110965 A CN200710110965 A CN 200710110965A CN 101324863 B CN101324863 B CN 101324863B
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Abstract
The invention provides a control device of a synchronous static memory, and a method. The control device is connected with the synchronous static memory through a data wire, and comprises a memory interface unit, a timing unit, a time multiplexing controlling unit and a read-write source application queue, wherein the time multiplexing controlling unit is used for accepting the access of the read-write source application queue, and controls and selects the read-write source of the corresponding time slice in the read-write source application queue for performing data read-write operation according to the timing number sent by the timing unit; the timing unit is used for providing timing reference for the time multiplexing controlling unit, and notifies the time multiplexing controlling unit to enter next timing number, and the time slice of each read-write source is corresponding to different timing numbers. The control device and the method have the advantages that the read-write efficiency of the synchronous static memory is improved, the data bandwidth can be assigned according to the requirements of the data rate of each read-write source, and thereby the waiting time of the memory can be saved.
Description
Technical field
The present invention relates to data communication technology field, particularly a kind of control device of synchronous static memory and method.
Background technology
Along with the development of data communication technology, the particularly appearance of the data communication technology of high bandwidth and high speed degree, inner in data communications equipment; Various device such as central processing unit, network processing unit, interface special chip etc. to memory access require increasingly high; Big bit wide, high-speed visit make the deviser become increasingly complex to the Interface design of storer, and particularly to a plurality of access originators are arranged, a storer or access originator number are very many when having only; And when each access originator needs different bandwidth; At this moment memory access efficient is very low, even causes data to stop up, and storer can't be visited; Or dispatch, thereby the design complexities of writing debugging difficulty, hardware and the resource consumption of software have been increased through software or ppu.
At present, the existing memory control device normally designs to dynamic storage specially, like patented claim CN200510100661, does not design to static memory specially; Or must have the outside processor of controller to carry out assist control, and be the U.S. Patent application of US2005132145 like application number, must have at least a processor when memory access, to assist the method for designing of its visit exactly.
Summary of the invention
The objective of the invention is to, a kind of control device of synchronous static memory is provided, can improve mutiread and write the source a static memory read-write efficiency.
Another object of the present invention is to, propose a kind of control method of synchronous static memory, can improve mutiread and write the source a static memory read-write efficiency.
The control device of synchronous static memory of the present invention; Be connected through data line with synchronous static control store, comprise memory interface unit, timing unit, time division multiplex control module, read-write source application queue, wherein; Said memory interface unit; Be used for when write data, from said time division multiplex control module, obtain corresponding write data and address, send it to said synchronous static memory; When read data, obtain to read the address accordingly from said time division multiplex control module, send it to said synchronous static memory, and read corresponding data from said synchronous static memory and be sent to said time division multiplex control module; Said time division multiplex control module is used to accept the visit of said read-write source application queue, and the timing number that sends according to said timing unit, and the operation that reads and writes data accordingly of the read-write source of corresponding timeslice in the application queue of read-write source is selected in control; Said timing unit is used to said time division multiplex control module the timing reference is provided, and is every at a distance from the schedule time, notifies said time division multiplex control module to get into next timing number, the corresponding different timing number of timeslice in each read-write source; Said read-write source application queue; Comprise a plurality of First Input First Outputs; Be used for respectively to a plurality of read-writes source read and write data and/or buffer memory is carried out in the address, and under the control of said time division multiplex control module, the data in the respective queue are sent to said time division multiplex control module.
Wherein, the timeslice in said each read-write source is in advance according to the number in the total bandwidth of synchronous static memory and read-write source, distributes with mode impartial or that do not wait.
Wherein, said time division multiplex control module is further used for confirming whether in the read-write source application queue of its selection be empty, when formation is non-NULL, carries out the operation that reads and writes data accordingly.
The number of the First Input First Output that comprises in the application queue of said read-write source in addition, is corresponding with the number in read-write source.
The control device of synchronous static memory of the present invention may further include read-write source data interface, is used for the data and/or the address translation of different-format are become synchronous static memory ability recognition data form and/or address format.
Wherein, said memory interface unit, according to the sequential of synchronous static memory with corresponding write data and address and/or read the address and be sent to synchronous static memory.
The control method of synchronous static memory of the present invention comprises the following steps:
Steps A: respectively with a plurality of read-writes source read and write data and/or address caching in corresponding a plurality of First Input First Outputs; And the timeslice that read-write operation is carried out in each read-write source is set; And the timing number in the timing unit is provided with; Wherein, the corresponding different timing number of timeslice in each read-write source;
Step B: timing unit picks up counting; Every at a distance from next timing number of schedule time entering, according to the timing number in the timing unit, control the read-write source of corresponding timeslice and carry out corresponding read-write operation; When write data, corresponding write data and address are sent to synchronous static memory; When read data, will read the address accordingly and be sent to synchronous static memory, and read corresponding data from synchronous static memory.
Wherein, the timeslice in said each read-write source is in advance according to the number in the total bandwidth of synchronous static memory and read-write source, distributes with mode impartial or that do not wait.
Wherein, in said step B, before corresponding read-write operation is carried out in the read-write source of the corresponding timeslice of control, comprise the following steps: further to judge whether the buffer queue in corresponding read-write source is empty, if when be non-NULL, the execution operation that reads and writes data accordingly.
In addition, the number of the First Input First Output in said read-write source is corresponding with the number in read-write source.
In addition; In said steps A; Respectively with a plurality of read-writes source read and write data and/or address caching before corresponding a plurality of First Input First Outputs, further comprise the following steps: to become the synchronous static memory can recognition data form and/or address format the data of different-format and/or address translation.
Wherein, in said step B, when corresponding read-write operation is carried out in the read-write source, according to the sequential of synchronous static memory with corresponding write data and address and/or read the address and be sent to synchronous static memory.
The invention has the beneficial effects as follows: according to the control device and the method for synchronous static memory of the present invention; Solved the read-write bottleneck problem of a plurality of read-writes source to a static memory; Improved mutiread and write the source, reached and to have saved memory latency time according to each effect that needs the distribute data bandwidth of reading and writing source data rate a static memory read-write efficiency; Reduce the design of hardware and software difficulty of system, and improved the overall performance of system.
Description of drawings
Fig. 1 is the structural representation of the control device of synchronous static memory of the present invention;
Fig. 2 is a time division multiplex time slot distribution plan of the present invention;
Fig. 3 is the flow chart of data processing figure of the time division multiplexing controller of the embodiment of the invention.
Embodiment
Below, with reference to the control device and the method for figure 1～3 detailed description synchronous static memory of the present invention.
As shown in Figure 1; Structural representation for the control device of synchronous static memory of the present invention; This control device is connected through data line with synchronous static control store, comprises memory interface unit, timing unit, time division multiplex control module, read-write source application queue.
Wherein: memory interface unit, be used for when write data, from the time division multiplex control module, obtain corresponding write data and address, send it to synchronous static memory; When read data, obtain to read the address accordingly from the time division multiplex control module, send it to synchronous static memory, and read corresponding data from this synchronous static memory and be sent to the time division multiplex control module.
Wherein, memory interface unit, according to the sequential of synchronous static memory with corresponding write data and address and read the address and be sent to synchronous static memory.
Time division multiplex control module, the visit that is used to accept to read and write the source application queue, and the timing number that sends according to timing unit, control are selected in the application queue of read-write source the operation that reads and writes data of corresponding certain read-write source.
Wherein, According to design demand, for example the user is to the demands of different of bandwidth, in advance according to the total bandwidth of synchronous static memory and the number in read-write source; Distribute a plurality of timeslices for each read-write source with mode impartial or that do not wait, the timeslice in each read-write source is corresponding with the timing number in the timing unit.
For example, the bandwidth of synchronous static memory is 2.4Gbit/s, and the timing number remembers 24 from 0, comprises four read-write sources, and the timeslice scope in read-write source 1 is 0～3; The timeslice scope in read-write source 2 is 4～8; The timeslice scope in read-write source 3 is 9～15; The timeslice scope in read-write source 4 is 16～24; When timing unit timing number was 5, then corresponding read-write source was read-write source 2, carries out corresponding read-write operation; The timing number of treating timing unit is 9 o'clock, then selects read-write source 3 to carry out corresponding read-write operation; When the timing number of timing unit reaches 24, and read-write source 4 executes after its corresponding read-write operation, and timer makes zero, and starts from scratch and restarts the timing circulation.
In addition, according to shown in Figure 2, read-write source 1 occupied bandwidth 0.4Gbit/s; Read-write source 2 occupied bandwidth 0.5Gbit/s; Read-write source 3 occupied bandwidth 0.7Gbit/s; Read-write source 4 occupied bandwidth 0.8Gbit/s.Therefore, can arrange taking of bandwidth for it, avoid the very little read-write source of occupied bandwidth to take the synchronous static memory of high bandwidth, thereby improve read-write efficiency according to each size of reading and writing the source occupied bandwidth.
In addition, the time division multiplex control module is further used for also confirming whether in the read-write source application queue of its selection be empty, when formation is non-NULL, when the read-write application is promptly arranged in the formation, carries out the operation that reads and writes data accordingly.
Timing unit is used to the time division multiplex control module timing reference is provided, and is every at a distance from the schedule time, and notice time division multiplex control module gets into next timing number.
Read-write source application queue; Comprise a plurality of FIFOs (FIFO) formation; Be used for respectively to each read-write source reading and writing data and/or buffer memory is carried out in the address, and under the control of time division multiplex control module, the data in the respective queue are sent to the time division multiplex control module.
The number of the fifo queue that wherein, comprises in the application queue of read-write source is corresponding with the number in read-write source.
Because each read-write source has different data bit widths, different address is divided, and therefore need data in each read-write source and/or address be unified into data layout and/or the address format that meets above-mentioned synchronous static memory.
Therefore, based on as stated, the control device of synchronous static memory of the present invention also further comprises read-write source data interface, is used for becoming the synchronous static memory can recognition data form and/or address format the data of different-format and/or address translation.
Particularly; When the timing number of timing unit corresponded to a certain read-write source, the time division multiplex control module can judge whether the application queue in this read-write source is non-NULL, if formation is a non-NULL; Be that the read-write application is arranged in the formation; When carrying out write operation, from the application queue of read-write source, take out address and data to be written and send to memory interface unit, thereby execute this time write operation; When carrying out read operation; From the application queue of read-write source, take out address information to be read and send to memory interface unit; And the feedback of wait memory interface unit; When the memory interface unit feedback reads data, be sent to corresponding read-write source in the application queue of read-write source with reading the data of coming, thereby execute this time read operation.
More than, the control device of synchronous static memory of the present invention is described, describe the control method of synchronous static memory of the present invention below in detail, this method comprises the following steps:
Steps A: respectively with a plurality of read-writes source read and write data and/or address caching in corresponding a plurality of First Input First Outputs; And the timeslice that read-write operation is carried out in each read-write source is set; And the timing number in the timing unit is provided with; Wherein, the corresponding different timing number of timeslice in each read-write source.
Wherein, the number of the First Input First Output in read-write source is corresponding with the number in read-write source.
In addition, because each read-write source has different data bit widths, different address is divided, and therefore need data in each read-write source and/or address be unified into data layout and/or the address format that meets above-mentioned synchronous static memory.
Therefore; In said steps A; Respectively with a plurality of read-writes source read and write data and/or address caching before corresponding a plurality of First Input First Outputs, may further include the following step: become the synchronous static memory can recognition data form and/or address format the data of different-format and/or address translation.
Step B: timing unit picks up counting; Every at a distance from next timing number of schedule time entering, according to the timing number in the timing unit, control the read-write source of corresponding timeslice and carry out corresponding read-write operation; When write data, corresponding write data and address are sent to synchronous static memory; When read data, will read the address accordingly and be sent to synchronous static memory, and read corresponding data from synchronous static memory.
Wherein, the timeslice in each read-write source is in advance according to the number in the total bandwidth of synchronous static memory and read-write source, distributes with mode impartial or that do not wait.
In addition, in said step B, before corresponding read-write operation is carried out in the read-write source of the corresponding timeslice of control, comprise the following steps: further to judge whether the buffer queue in corresponding read-write source is empty, if when be non-NULL, the execution operation that reads and writes data accordingly.
In said step B, when corresponding read-write operation is carried out in the read-write source, according to the sequential of synchronous static memory with corresponding write data and address and/or read the address and be sent to synchronous static memory.
As shown in Figure 3, be the flow chart of data processing figure of the time division multiplexing controller of the embodiment of the invention.
In sum; Control device and method according to synchronous static memory of the present invention have solved the read-write bottleneck problem of a plurality of read-writes source to a static memory, have improved mutiread and have write the source to a static memory read-write efficiency; Reached the effect that needs the distribute data bandwidth that to read and write source data rate according to each; Save memory latency time, reduced the design of hardware and software difficulty of system, and improved the overall performance of system.
More than be in order to make those of ordinary skills understand the present invention; And to detailed description that the present invention carried out; But can expect; In the scope that does not break away from claim of the present invention and contained, can also make other variation and modification, these variations and revising all in protection scope of the present invention.
Claims (12)
1. the control device of a synchronous static memory is connected through data line with synchronous static control store, it is characterized in that, comprises memory interface unit, timing unit, time division multiplex control module, read-write source application queue, wherein,
Said memory interface unit is used for when write data, from said time division multiplex control module, obtains corresponding write data and address, sends it to said synchronous static memory; When read data, obtain to read the address accordingly from said time division multiplex control module, send it to said synchronous static memory, and read corresponding data from said synchronous static memory and be sent to said time division multiplex control module;
Said time division multiplex control module is used to accept the visit of said read-write source application queue, and the timing number that sends according to said timing unit, and the operation that reads and writes data accordingly of the read-write source of corresponding timeslice in the application queue of read-write source is selected in control;
Said timing unit is used to said time division multiplex control module the timing reference is provided, and is every at a distance from the schedule time, notifies said time division multiplex control module to get into next timing number, the corresponding different timing number of timeslice in each read-write source;
Said read-write source application queue; Comprise a plurality of First Input First Outputs; Be used for respectively to a plurality of read-writes source read and write data and/or buffer memory is carried out in the address, and under the control of said time division multiplex control module, the data in the respective queue are sent to said time division multiplex control module.
2. the control device of synchronous static memory as claimed in claim 1 is characterized in that, the timeslice in said each read-write source is in advance according to the number in the total bandwidth of synchronous static memory and read-write source, distributes with mode impartial or that do not wait.
3. the control device of synchronous static memory as claimed in claim 1; It is characterized in that said time division multiplex control module is further used for confirming whether in the read-write source application queue of its selection be empty; When formation is non-NULL, carry out the operation that reads and writes data accordingly.
4. like the control device of each described synchronous static memory in the claim 1 to 3, it is characterized in that the number of the First Input First Output that comprises in the application queue of said read-write source is corresponding with the number in read-write source.
5. like the control device of each described synchronous static memory in the claim 1 to 3; It is characterized in that; Further comprise read-write source data interface, be used for the data and/or the address translation of different-format are become synchronous static memory ability recognition data form and/or address format.
6. like the control device of each described synchronous static memory in the claim 1 to 3; It is characterized in that; Said memory interface unit, according to the sequential of synchronous static memory with corresponding write data and address and/or read the address and be sent to synchronous static memory.
7. a method of utilizing the said device of claim 1 to synchronous static memory control is characterized in that, comprises the following steps:
Steps A: respectively with a plurality of read-writes source read and write data and/or address caching in corresponding a plurality of First Input First Outputs; And the timeslice that read-write operation is carried out in each read-write source is set; And the timing number in the timing unit is provided with; Wherein, the corresponding different timing number of timeslice in each read-write source;
Step B: timing unit picks up counting; Every at a distance from next timing number of schedule time entering, according to the timing number in the timing unit, control the read-write source of corresponding timeslice and carry out corresponding read-write operation; When write data, corresponding write data and address are sent to synchronous static memory; When read data, will read the address accordingly and be sent to synchronous static memory, and read corresponding data from synchronous static memory.
8. the method for synchronous static memory as claimed in claim 7 control is characterized in that, the timeslice in said each read-write source is in advance according to the total bandwidth of synchronous static memory and the number in read-write source, distributes with mode impartial or that do not wait.
9. the method for synchronous static memory control as claimed in claim 7; It is characterized in that; In said step B, before corresponding read-write operation is carried out in the read-write source of the corresponding timeslice of control, comprise the following steps: further to judge whether the buffer queue in corresponding read-write source is empty; If when being non-NULL, carry out the operation that reads and writes data accordingly.
10. like the method for each described synchronous static memory control in the claim 7 to 9, it is characterized in that the number of the First Input First Output in said read-write source is corresponding with the number in read-write source.
11. method like each described synchronous static memory control in the claim 7 to 9; It is characterized in that; In said steps A; Respectively with a plurality of read-writes source read and write data and/or address caching before corresponding a plurality of First Input First Outputs, further comprise the following steps: to become the synchronous static memory can recognition data form and/or address format the data of different-format and/or address translation.
12. method like each described synchronous static memory control in the claim 7 to 9; It is characterized in that; In said step B; When corresponding read-write operation is carried out in the read-write source, according to the sequential of synchronous static memory with corresponding write data and address and/or read the address and be sent to synchronous static memory.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101729421B (en) * | 2009-12-11 | 2013-03-20 | 杭州华三通信技术有限公司 | Storage method and device based on time division multiplex |
| CN107924370A (en) * | 2015-09-29 | 2018-04-17 | 上海宝存信息科技有限公司 | Processing is associated with the method for the return entity of multiple requests and the device using this method in single Interrupt Service Routine thread |
| CN105589819B (en) * | 2015-12-20 | 2018-11-16 | 苏州长风航空电子有限公司 | A method of based on IIC interface operation eeprom chip |
| CN111782561B (en) * | 2020-09-07 | 2020-12-04 | 新华三半导体技术有限公司 | SRAM storage space allocation method, device and chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1477871A (en) * | 2002-07-19 | 2004-02-25 | 三星电子株式会社 | Image processing device and method |
| CN1524215A (en) * | 2001-06-20 | 2004-08-25 | Ħ��������˾ | First-in, first-out memory system and method thereof |
| CN1859282A (en) * | 2005-10-22 | 2006-11-08 | 华为技术有限公司 | Storage controller and control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1524215A (en) * | 2001-06-20 | 2004-08-25 | Ħ��������˾ | First-in, first-out memory system and method thereof |
| CN1477871A (en) * | 2002-07-19 | 2004-02-25 | 三星电子株式会社 | Image processing device and method |
| CN1859282A (en) * | 2005-10-22 | 2006-11-08 | 华为技术有限公司 | Storage controller and control method |
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