CN102403971A - Automatic gain control demodulation circuit - Google Patents

Automatic gain control demodulation circuit Download PDF

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CN102403971A
CN102403971A CN2010102863271A CN201010286327A CN102403971A CN 102403971 A CN102403971 A CN 102403971A CN 2010102863271 A CN2010102863271 A CN 2010102863271A CN 201010286327 A CN201010286327 A CN 201010286327A CN 102403971 A CN102403971 A CN 102403971A
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circuit
current mirror
variable gain
demodulation
gain amplifier
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CN102403971B (en
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陈龙
刘军华
李琛
廖怀林
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Peking University
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Abstract

The invention discloses an automatic gain control demodulation circuit, belonging to the field of radio frequency integrated circuit; the circuit of the invention comprises a variable gain amplifier, a demodulation loop, a buffer and a charge pump, wherein the output end of the variable gain amplifier is connected with the input end of the demodulation loop, the output end of the demodulation loop is connected with the input end of the buffer, the output end of the buffer is connected with the input end of the charge pump, and the control end of the variable gain amplifier is connected with the output end of the charge pump. Compared with the prior art, the automatic gain control demodulation circuit of the invention has the advantages of simple structure, low power dissipation, easiness in implementation and large power self-regulating range of input signals.

Description

A kind of Gain Automatic control demodulator circuit
Technical field
The present invention relates to a kind of demodulator circuit, relate in particular to a kind of Gain Automatic control demodulator circuit, belong to field of radio frequency integrated circuits.
Background technology
Along with integrated circuit (Integrated Circuits; IC) development of technology; Size of semiconductor device is constantly dwindled, and the performance of integrated circuit constantly promotes, and shows that mainly operating frequency is more and more faster, increasingly high, the attainable function of integrated level becomes increasingly complex.Dwindling of device itself can increase leakage current, and the lifting of operating frequency increases node capacitor and discharges and recharges the power consumption that causes, the complicated of function often is sacrifice especially with the power consumption.Especially when process node be developed to deep-submicron 130,90nm, the cut-off frequency f of device TRise to 70GHz, 100GHz and more than, circuit work frequency rises to GHz even 10GHz magnitude, high-performance and low-power consumption more and more become a pair of contradiction index that needs the compromise consideration.
The temperature rising that power consumption causes can make device performance degeneration even burn, and another even more serious problem is not have under the prerequisite of marked improvement at battery technology, and power consumption is with the service time of direct limiting mobile terminal.Radio frequency (Radio Frequency, RF) circuit is as a radio communication of not having lasting power supply supply and an important module in the personal data terminal, and its power consumption also increases day by day and becomes the key factor that influences in the system power dissipation.(Low Power, LP) design becomes an important consideration of IC design thereupon in low-power consumption.In digital circuit, various Low-power Technology are widely used already, like the multivoltage technology; The multi-Vt technology; Pipelining, concurrent technique, precomputation technology etc.; These technology are by system research and be widely used in system level design and the electric design automation of digital circuit (Electronic Design Automation is EDA) in the synthesis tool.Super low-power consumption design for simulation and radio circuit does not have systematized design cycle at present.Its low power dissipation design is removed in overall situation integral body with research and is considered power consumption, and the designer should be in each circuit details optimize power consumption index.
In digital communication, after the amplification of reception signal process RF front-end module and the filtering of filter and mirror image suppress,, and obtain final data " 1 ", " 0 " signal after giving the demodulation module reception in the further amplification of ABB part.Traditional ripple demodulation mode that unloads comprises two kinds of coherent demodulation and non-coherent demodulations.The former needs local the generation with the relevant local oscillated signal of carrier wave will receive signal mixing to Low Medium Frequency or zero intermediate frequency, and the latter generally only comprises the amplitude detection of waveform.Comparatively speaking, the former needs the local oscillated signal of local phase-locked loop generation and carrier frequency and phase place strict synchronism, so circuit implements comparatively complicacy, and when having interference and signal attenuation, more difficulty reaches requirement; And the latter generally only needs envelope detected (like frequency shift keying) or phase-detection (like differential phase keying (DPSK)), and cost is the 3dB loss of signal to noise ratio.No matter be traditional coherent demodulation method, or non-coherent demodulation method, generally realizing more complicated, power consumption is bigger.
Summary of the invention
To the power problems of current demodulation loop, the object of the present invention is to provide a kind of Gain Automatic control demodulator circuit, the present invention is applicable to the ultra-low power consumption wireless communication field.
Because the coherent demodulation circuit is realized complicated, power consumption is generally very big, and the present invention proposes a kind of new incoherent ripple demodulation mode that unloads.To pass through I, Q four road signals behind low noise amplifier, frequency mixer down-conversion, the filter filtering; Variable gain amplifier in circuit of the present invention (Variable Gain Amplifier; VGA) after the amplification; Realized unloading ripple and demodulation by squaring circuit, the gain of VGA is controlled by method provided by the invention.
Technical scheme of the present invention is:
A kind of Gain Automatic control demodulator circuit is characterized in that comprising variable gain amplifier, demodulation loop, buffer, charge pump; Wherein, the output of said variable gain amplifier is connected with the input of said demodulation loop, the output of said demodulation loop is connected with the input of said buffer, the output of said buffer is connected with the input of said charge pump, the control end of said variable gain amplifier is connected with said electric charge delivery side of pump.
Further, comprise the variable gain amplifier of the input of two groups of difference, difference output, said demodulation loop is for square unloading ripple demodulation loop; The output of two groups of said variable gain amplifiers is connected with said square of input that unloads ripple demodulation loop respectively, and two groups of said amplifier's gain control ends are connected with said electric charge delivery side of pump respectively.
Further, said square is unloaded ripple demodulation loop and comprises current mirror 1, current mirror 2, metal-oxide-semiconductor M1, M2, M3, M4, M5, M6, M7 and a resistance R; Wherein M1, M2, M3, M4 are that the breadth length ratio of measure-alike 4 metal-oxide-semiconductors and M5 is 4 times of M1 breadth length ratio; The grid of said M1, M2, M3, M4 is connected with an output of said variable gain amplifier respectively; And the source electrode of said M1, M2, M3, M4 is connected, drains with ground wire respectively and is connected with the source electrode of said M6 respectively; The drain electrode of said M6 is connected with an end of said current mirror 1, and the grid of said M6 is connected with the grid of said M7, and the drain electrode of said M7 is connected with the other end of said current mirror 1; And the source electrode of said M7 is connected with the drain electrode of said M5; The grid of said M5 is connected with a bias current end, and its source electrode is connected with ground wire, and the drain electrode of said M6 is connected with an end of said current mirror 2; The other end of said current mirror 2 is connected with an end of said resistance R and the input of said buffer respectively, and the other end of said resistance R is connected with ground wire.
Further, said current mirror 1 is the current mirror of PMOS cascade.
Further, said current mirror 2 is the current mirror of PMOS cascade.
Further, said M1, M2, M3, M4, M5 are the NMOS pipe.
Further, said variable gain amplifier is difference input, the difference output variable gain amplifier of three-stage cascade.
Further, said buffer is made up of two inverter cascades.
Further, said demodulation loop is the non-coherent demodulation loop.
Compared with prior art, the present invention has following advantage:
(1) simple in structure.Main modular of the present invention is that the basic degenerative VGA of source class, novel square of demodulator circuit unload ripple demodulator circuit and charge pump (Charge Pump).The circuit entire area is little, clear principle.
(2) super low-power consumption, the present invention adopts, and square to unload ripple demodulation loop power consumption extremely low, and other modules such as VGA and charge pump also adopt the most simply structure or improvement as far as possible.Be merely about 300 μ A at current drain under the 1.8V supply voltage, be fit to long-time radio communication requirement.
(3) low to the intermediate frequency accuracy requirement; Utilization of the present invention is operated in MOS device current and the square law characteristic of voltage and square complementary characteristic of sine and cosine of saturation region; Little with the big or small correlation of IF-FRE itself, reduced the index and the design difficulty requirement of local oscillated signal;
(4) dynamic range is big, and the present invention is big for the power self-regulation scope of input signal, for input power range for-45dBm～-signal of 5dBm all has demodulation effect preferably, dynamic range can reach 40dB and higher in theory.
Description of drawings
Fig. 1 is the Gain Automatic control demodulator circuit of a present invention sketch map.
Fig. 2 is the VGA circuit diagram of three-stage cascade.
Fig. 3 square unloads ripple demodulator circuit figure.
Fig. 4 is Fig. 1 charge pump circuit figure.
Specific embodiments
The specific embodiments of super low-power consumption of the present invention square demodulation loop and gain controlling mode is following:
Fig. 1 is the Gain Automatic control demodulator circuit of a present invention sketch map.The importation of whole loop is VGA, and its input signal is radio-frequency front-end and frequency mixer down-conversion, amplify and filtered I, Q difference totally four road signals, and its phase place is respectively 0, pi/2, π and 3 pi/2s.As shown in Figure 1; VGA amplifies filtered baseband signal with a suitable gain; Unload ripple through a square demodulation module again; Unload signal behind the ripple and be shaped as by buffer and be similar to short digital baseband data of square wave time, buffer is made up of two inverter cascades, promptly gets final duty ratio in theory and be 50% demodulating data.The automatic control process of loop gain is mainly accomplished through charge pump.If the gain of VGA is too high, then have partial data 0 be demodulated into 1 or the duty ratio of demodulating data surpass 50%, vice versa.The effect of charge pump is to detect whether the duty ratio of dateout is 50%.If the dateout duty ratio is less than 50%; It is low to mean that VGA gained, and the ON time of NMOS will be short than PMOS in the charge pump, on the whole; The integrating capacitor of charge pump will be by charging gradually; Voltage on the integrating capacitor will raise, and this voltage is the gain control signal V_Ctrl of VGA, so the VGA gain will become big; Vice versa.Behind the output voltage stabilization of charge pump, it is stable that system gain also reaches, thereby realize the gain controlling of loop.
Fig. 2 is the general structure of three-stage cascade VGA.The VGA amplifying signal makes it enough amplitudes arranged by the demodulation module demodulation, and the correct control of its gain size directly has influence on the judgement of demodulation module to data " 1 ", " 0 ".In the present invention, adopt the structure of three-stage cascade VGA to gain, and the gain of VGA is controlled automatically through corresponding gain control loop to improve cascade.The gain that provides of VGA is very big, need influence the dc point of late-class circuit to prevent the prime dc shift with the capacitance AC coupled between every grade of VGA.Thereby the gain controlling of every grade of VGA is to change its equivalent resistance through the grid voltage that changes input stage source end feedback metal-oxide-semiconductor to realize; Every grade of the highest gain that about 0～20dB is provided of VGA; Integral body provides about 0～60dB gain altogether, makes it can satisfy the dynamic range of input 40dB.Whole VGA's is simple in structure, realizes high-gain with less electric current.
Shown in Figure 3 is novel square of sketch map that unloads the ripple demodulator circuit, for ease of this circuit working principle is described, with f cExpression receives the carrier frequency after the signal down-conversion, and differing between the I behind the mixing LPF, Q difference four tunnel is pi/2, and this four road signal can be expressed as respectively
v 1＝V mA scos(2πf ct)；
v 2＝V mA scos(2πf ct+π)；
v 3 = V m A s cos ( 2 πf c t + π 2 ) ;
v 4 = V m A s cos ( 2 πf c t + 3 π 2 ) .
Wherein, A mThe signal amplitude of expression after VGA amplifies, A sExpression binary data signal (" 1 " or " 0 ").Above-mentioned 4 road ac small signals are carried on the NMOS pipe M1～M4 grid voltage that works in the saturation region, and electric current is separately sued for peace:
I d = K ( v 1 + V 0 ) 2 + K ( v 2 + V 0 ) 2 + K ( v 3 + V 0 ) 2 + K ( v 4 + V 0 ) 2
= K { [ V m A s cos ( 2 πf c t ) + V 0 ) ] 2 + [ V m A s cos ( 2 πf c t + π ) + V 0 ] 2
+ [ V m A s cos ( 2 πf c t + π 2 ) + V 0 ] 2 + [ V m A s cos ( 2 πf c t + 3 π 2 ) + V 0 ] 2 }
= 4 KV 0 2 + 2 KV m 2 A g 2
Wherein K is the conduction factor of the input pipe M1～M4 of same size, V 0Poor for M1～M4 direct current grid voltage biasing and threshold voltage.I dMiddle first is a flip-flop, and second portion has then comprised binary data signal A sAlternating component.Other designs 4 times the NMOS pipe M5 that breadth length ratio is M1, and itself and M1～M4 are biased under the identical DC environment, and on M1～M4 and M5, connecting altogether, bank tube equates with M1～M4 direct current sum to guarantee the M5 direct current.Electric current after the same M1 of the electric current of M5～M4 summation is connected through the PMOS common-source common-gate current mirror, like this, at the tie point of M1～M4 branch road and PMOS current mirror, the electric current I of M1～M4 pipe dWill with the M5 tube current
Figure BSA00000276711200047
Differ from, thereby obtain electric current I dAC portion I_DATA, that is 2KV m 2A s 2This AC portion duplicates and acts on the resistance R through the PMOS current mirror of cascade, promptly gets the restituted signal behind the ripple that unloads tentatively.This signal promptly gets restituted signal finally through the data buffer shaping of the inverter formation of cascade.For reducing dimensional mismatch and metal-oxide-semiconductor second-order effects, bigger to the long value of the grid of asking square input pipe.The resistance R value is bigger, and entire circuit can obtain the enough discriminations to primary signal 0,1 under lower electric current, thereby power consumption is extremely low.
Fig. 4 is the electric charge pump structure, and its effect is the duty ratio of 0,1 data after the detection demodulation, thus the gain of FEEDBACK CONTROL VGA.For saving power consumption, charge pump is taked the simplest structure, but can't acute exacerbation influence circuit performance.The pull-up current of supposing charge pump PMOS be NMOS pull-down current (1+ α) doubly; Then for burning voltage on the integrating capacitor; Charging interval is merely 1/ (the 1+ α) of discharge time; This means that 1 length is 1/ (1+ α) with respect to 0 length in the demodulating data after the loop stability, duty ratio is 1/ (2+ α) in other words.After the clock and data recovery that connects (Clock Data Recovery, the duty cycle deviations that CDR) can correctly sample on the Circuit theory is 25%, this means, can tolerate the current mismatch of charge pump 100%.It is thus clear that gain control method provided by the invention is less demanding to the currents match of charge pump, simplified the charge pump design, thus can its power consumption compression is to the utmost point low.
In a word, novel square of the present invention design unloads the ingenious complementary characteristic of sine and cosine functions square that utilized of ripple demodulation module and has removed carrier wave.Whole demodulating process is very succinct, and the design of circuit all launches based on the requirement of super low-power consumption, and the power consumption of whole demodulation module is about 300 μ A.It should be noted that this square of demodulation method that unloads ripple do not have direct requirement for IF-FRE, this will reduce the requirement for the phase-locked loop frequency precision greatly, thereby give the bigger design margin that stays of other modules, comprise power consumption.

Claims (9)

1. a Gain Automatic control demodulator circuit is characterized in that comprising variable gain amplifier, demodulation loop, buffer, charge pump; Wherein, the output of said variable gain amplifier is connected with the input of said demodulation loop, the output of said demodulation loop is connected with the input of said buffer, the output of said buffer is connected with the input of said charge pump, the control end of said variable gain amplifier is connected with said electric charge delivery side of pump.
2. circuit as claimed in claim 1 is characterized in that comprising the variable gain amplifier of two groups of difference inputs, difference output, and said demodulation loop is for square unloading ripple demodulation loop; The output of two groups of said variable gain amplifiers is connected with said square of input that unloads ripple demodulation loop respectively, and two groups of said amplifier's gain control ends all are connected with said electric charge delivery side of pump.
3. circuit as claimed in claim 2 is characterized in that said square is unloaded ripple demodulation loop and comprise current mirror 1, current mirror 2, metal-oxide-semiconductor M1, M2, M3, M4, M5, M6, M7 and a resistance R; Wherein M1, M2, M3, M4 are that the breadth length ratio of measure-alike 4 metal-oxide-semiconductors and M5 is 4 times of M1 breadth length ratio; The grid of said M1, M2, M3, M4 is connected with an output of said variable gain amplifier respectively; And the source electrode of said M1, M2, M3, M4 is connected, drains with ground wire respectively and is connected with the source electrode of said M6 respectively; The drain electrode of said M6 is connected with an end of said current mirror 1, and the grid of said M6 is connected with the grid of said M7, and the drain electrode of said M7 is connected with the other end of said current mirror 1; And the source electrode of said M7 is connected with the drain electrode of said M5; The grid of said M5 is connected with a bias current end, and its source electrode is connected with ground wire, and the drain electrode of said M6 is connected with an end of said current mirror 2; The other end of said current mirror 2 is connected with an end of said resistance R and the input of said buffer respectively, and the other end of said resistance R is connected with ground wire.
4. circuit as claimed in claim 3 is characterized in that said current mirror 1 is the current mirror of PMOS cascade.
5. circuit as claimed in claim 3 is characterized in that said current mirror 2 is the current mirror of PMOS cascade.
6. circuit as claimed in claim 3 is characterized in that said M1, M2, M3, M4, M5 are the NMOS pipe.
7. like claim 1 or 2 or 3 described circuit, it is characterized in that said variable gain amplifier is difference input, the difference output variable gain amplifier of three-stage cascade.
8. like claim 1 or 2 or 3 described circuit, it is characterized in that said buffer is made up of two inverter cascades.
9. like claim 1 or 2 or 3 described circuit, it is characterized in that said demodulation loop is the non-coherent demodulation loop.
CN201010286327.1A 2010-09-17 2010-09-17 Automatic gain control demodulation circuit Expired - Fee Related CN102403971B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825239A (en) * 1997-05-06 1998-10-20 Texas Instruments Incorporated Peak detector for automatic gain control
JPH10341267A (en) * 1997-06-06 1998-12-22 Nec Corp Agc circuit
CN1901401A (en) * 2006-07-07 2007-01-24 广东鼎威经济发展有限公司 Realizing two-way conversion integrated circuit between RF signals and medium frequency wired signal

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825239A (en) * 1997-05-06 1998-10-20 Texas Instruments Incorporated Peak detector for automatic gain control
JPH10341267A (en) * 1997-06-06 1998-12-22 Nec Corp Agc circuit
CN1901401A (en) * 2006-07-07 2007-01-24 广东鼎威经济发展有限公司 Realizing two-way conversion integrated circuit between RF signals and medium frequency wired signal

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