CN102385545A - BIOS (Basic Input Output System) debugger and debugging method - Google Patents
BIOS (Basic Input Output System) debugger and debugging method Download PDFInfo
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- CN102385545A CN102385545A CN2010102668156A CN201010266815A CN102385545A CN 102385545 A CN102385545 A CN 102385545A CN 2010102668156 A CN2010102668156 A CN 2010102668156A CN 201010266815 A CN201010266815 A CN 201010266815A CN 102385545 A CN102385545 A CN 102385545A
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Abstract
The invention relates to a BIOS (basic input output system) debugger and a BIOS debugging method. The BIOS debugging method comprises a single chip microcomputer, an FPGA (field programmable gate array) chip, an RAM (random access memory) and two seven-segment digital tubes, wherein the FPGA chip is connected with the single chip microcomputer, the RAM and the two seven-segment digital tubes. BIOS burning data signals in a series transmission format output by a control computer is converted into the BIOS burning data signals in a parallel transmission format to be output to the FPGA chip by the single chip microcomputer. The BIOS burning data signals in the parallel transmission format is stored into the RAM by the FPGA chip, the BIOS burning data signals read in RAM 30 are converted into data signals in an SPI (serial peripheral interface) communication protocol format and then are output to a computer to be tested, so that the POST (power on self test) of the computer to be tested is conducted. The POST data signals output by the computer to be tested are also converted into two-digit hexadecimal data to be output to the two seven-segment digital tubes for displaying.
Description
Technical field
The present invention relates to a kind of BIOS debugger and adjustment method.
Background technology
At present; Basic Input or Output System (BIOS) (basic input/output system; BIOS) method of developing department's debugging BIOS mainly may further comprise the steps: with needing the BIOS chip of debugging to pull up on the computing machine to be measured; This BIOS chip that need debug is mounted to the computing machine of an operate as normal, through burning program burning data (for example BIOS source document or BIOS updating file) is burned onto the BIOS chip that this need be debugged again.Afterwards, this BIOS chip that need debug is pulled up from said computing machine, turned back to computing machine to be measured, computing machine to be measured is powered on, and (power on self test POST), checks whether this each assembly of computing machine to be measured is in proper working order in the execution startup self-detection.
The weak point of this adjustment method is repeatedly taking off to put relatively and losing time of BIOS chip.Because gradually becoming strong of BIOS function, the BIOS chip capacity of different computing machines to be measured is also increasing, and recordable time increases thereupon.In addition; If computing machine to be measured is also to opening the screen display stage or key fault occurring; Do not have when demonstration on the screen, the designer can't learn the POST stage of living in or can't judge computer failure to be measured place, need utilize the POST diagnostic card; Codelookup POST code table according to showing on the POST diagnostic card is learnt computing machine POST to be measured stage of living in or failure cause and trouble location, makes troubles and loses time to test.
Summary of the invention
In view of above content, the present invention provides a kind of BIOS debugger and adjustment method, can save debug time, improves replication rate, and does not rely on POST diagnostic card demonstration debugging progress and state.
A kind of BIOS debugger, this BIOS debugger comprise single-chip microcomputer, on-site programmable gate array FPGA chip, random access memory ram and two seven segment digital tubes.Said fpga chip is connected with single-chip microcomputer, RAM and two seven segment digital tubes.Said single-chip microcomputer connects control computer through the general-purpose serial bus USB interface.This single-chip microcomputer receives the BIOS burning data signal of the serial transmission form of control computer output through USB interface, exports said fpga chip to after the BIOS burning data conversion of signals of serial transmission form being become the BIOS burning data signal of parallel transmission form.Said fpga chip is connected with computing machine to be measured through SPI SPI and low pin number interface LPC.This fpga chip with the BIOS burning data signal storage of parallel transmission form to RAM; After the BIOS burning data transmission of the parallel transmission form that will from RAM, read converts the data-signal of SPI communications protocol format to; Export computing machine to be measured to through the SPI interface, so that computing machine to be measured is carried out POST.This fpga chip also receives the POST data-signal of computing machine to be measured output through the LPC interface, convert this POST data-signal to a double-digit hexadecimal data after, export said two seven segment digital tubes to.Said two seven segment digital tubes show said double-digit hexadecimal data; From the POST code table, search the implication of the hexadecimal data of this two double figures for the designer, thereby locate the fault that occurs in POST stage or the POST process of computing machine to be measured.
A kind of BIOS adjustment method, this method may further comprise the steps: (A) utilize single-chip microcomputer to pass through the BIOS burning data signal that USB interface receives the serial transmission form of control computer output; (B) utilize this single-chip microcomputer that the BIOS burning data conversion of signals of serial transmission form is become the BIOS burning data signal of parallel transmission form, and export the BIOS burning data signal of parallel transmission form to fpga chip; (C) utilize fpga chip with the BIOS burning data signal storage of parallel transmission form to RAM; (D) utilize fpga chip from RAM, to read the BIOS burning data signal of parallel transmission form; After the BIOS burning data conversion of signals of parallel transmission form become the data-signal of SPI communications protocol format; Export computing machine to be measured to through the SPI interface, so that computing machine to be measured is carried out POST; (E) utilize fpga chip to pass through the POST data-signal that the LPC interface receives computing machine to be measured output, and after converting this POST data-signal to a double-digit hexadecimal data, export two seven segment digital tubes to; And (F) utilize these two seven segment digital tubes to show said double-digit hexadecimal data; From the POST code table, search the implication of this double-digit hexadecimal data for the designer, thereby locate the fault that occurs in POST stage or the POST process of computing machine to be measured.
Compared to prior art; BIOS debugger provided by the invention and adjustment method; Substitute the BIOS chip with jumbo RAM; Do not carry out the POST test so the BIOS chip is installed on computing machine to be measured, substitute the POST state that the POST diagnostic card shows computing machine to be measured with seven segment digital tubes, testing cost is low and speed is fast.
Description of drawings
Fig. 1 is the functional block diagram of BIOS debugger of the present invention preferred embodiment.
Fig. 2 is the process flow diagram of BIOS adjustment method of the present invention preferred embodiment.
The main element symbol description
| The BIOS debugger | ?100 |
| Control computer | ?200 |
| Single-chip microcomputer | ?10 |
| Fpga chip | ?20 |
| RAM | ?30 |
| Seven segment digital tubes | ?40 |
| USB interface | ?11 |
| The SPI interface | ?21 |
| The LPC interface | ?22 |
| Computing machine to be measured | ?300 |
Embodiment
Consulting shown in Figure 1ly, is Basic Input or Output System (BIOS) of the present invention (basic input/outputsystem, BIOS) functional block diagram of debugger preferred embodiment.This BIOS debugger 100 comprises single-chip microcomputer 10, field-programmable gate array (field-programmable gatearray, FPGA) chip 20, RAS (random access memory, RAM) 30 and two seven segment digital tubes 40.Fpga chip 20 is connected with single-chip microcomputer 10, RAM30 and two seven segment digital tubes 40.(universal serial bus, USB) interface 11 connects control computer 200 to single-chip microcomputer 10, and receives the BIOS burning data signal of the serial transmission form of control computer 200 outputs through usb 11 through USB.Afterwards, single-chip microcomputer 10 becomes the BIOS burning data signal of parallel transmission form with the BIOS burning data conversion of signals of serial transmission form, improving message transmission rate, and exports the BIOS burning data signal of parallel transmission form to fpga chip 20.For example, single-chip microcomputer 10 can be the parallel transmission form by the serial transmission format conversion with the data-signal that receives in the files such as " xxx.bin ", " xxx.rom " in the BIOS burning data, " xxx.hex ".
The designer can be provided with the logical block of fpga chip 20 as required, makes fpga chip 20 have the different logical function.In the present embodiment, fpga chip 20 has following logic function:
Seven segment digital tubes 40 shows these double-digit hexadecimal datas, and the designer can search the implication of this double-digit hexadecimal data from the POST code table, with the fault that occurs in POST stage of locating computing machine 300 to be measured or the POST process.For example on behalf of the POST current generation, " 00 " be " configuration of display system ", and it is the processor test that the POST current generation is represented in " 01 ".Seven segment digital tubes 40 is on the insulating material of definite shape; Utilize light emitting diode (light-emitting diode; LED) assembled arrangement becomes the charactron of " 8 " font, and the electrode of drawing LED is respectively lighted corresponding dot-dash and demonstrated the numeral of 0-9 or the character of A-F.
In the present embodiment, said single-chip microcomputer 10, fpga chip 20, RAM30 and seven segment digital tubes 40 are to supply power through said usb 11.
Consulting shown in Figure 2ly, is the process flow diagram of BIOS adjustment method of the present invention preferred embodiment.It is pointed out that before carrying out following method, at first will power on that each ingredient to BIOS debugger 100 after powering on carries out initialization action, confirms that each ingredient can operate as normal through 1 pair of BIOS debugger 100 of usb 1.
Step S201, single-chip microcomputer 10 receive the BIOS burning data signal of the serial transmission form of control computer 200 outputs through usb 11.
Step S203, single-chip microcomputer 10 becomes the BIOS burning data signal of parallel transmission form with the BIOS burning data conversion of signals of serial transmission form, and exports the BIOS burning data signal of parallel transmission form to fpga chip 20.
Step S205, fpga chip 20 with the BIOS burning data signal storage of parallel transmission form to RAM 30.
Step S207, fpga chip 20 read the BIOS burning data signal of parallel transmission form from RAM 30, the BIOS burning data conversion of signals of parallel transmission form is become the data-signal of SPI communications protocol format.
Step S209, fpga chip 20 exports the data-signal of SPI communications protocol format to computing machine 300 to be measured through SPI interface 21, so that computing machine 300 to be measured is carried out POST.
Step S211, fpga chip 20 receives the POST data-signal that computing machine 300 to be measured is exported through LPC interface 22, converts this POST data-signal to a double-digit hexadecimal data and (after 00～FF), exports two seven segment digital tubes 40 to.
Step S213, two seven segment digital tubes 40 show said double-digit hexadecimal data.
Step S215, designer search the implication of this double-digit hexadecimal data from the POST code table, with the fault that occurs in POST stage of locating computing machine 300 to be measured or the POST process.
What should explain at last is; Above embodiment is only unrestricted in order to technical scheme of the present invention to be described; Although the present invention is specified with reference to preferred embodiment; Those of ordinary skill in the art should be appreciated that and can make amendment or be equal to replacement technical scheme of the present invention, and do not break away from the spirit and the scope of technical scheme of the present invention.
Claims (8)
1. BIOS debugger; It is characterized in that; This BIOS debugger comprises single-chip microcomputer, on-site programmable gate array FPGA chip, random access memory ram and two seven segment digital tubes, and said fpga chip is connected with single-chip microcomputer, RAM and two seven segment digital tubes, wherein:
Said single-chip microcomputer; Connect control computer through the general-purpose serial bus USB interface; Receive the BIOS burning data signal of the serial transmission form of control computer output through USB interface, export said fpga chip to after the BIOS burning data conversion of signals of serial transmission form being become the BIOS burning data signal of parallel transmission form;
Said fpga chip; Be connected with computing machine to be measured through SPI SPI and low pin number interface LPC; To random access memory ram, after the BIOS burning data conversion of signals of the parallel transmission form that will from RAM, read becomes the data-signal of SPI communications protocol format, export the BIOS burning data signal storage of parallel transmission form to computing machine to be measured through the SPI interface; So that computing machine to be measured is carried out startup self-detection POST; And receive the POST data-signal of computing machine to be measured output through the LPC interface, convert this POST data-signal to a double-digit hexadecimal data after, export said two seven segment digital tubes to; And
Said two seven segment digital tubes show said double-digit hexadecimal data, from the POST code table, search the implication of this double-digit hexadecimal data for the designer, thereby locate the fault that occurs in POST stage or the POST process of computing machine to be measured.
2. BIOS debugger as claimed in claim 1 is characterized in that, said double-digit hexadecimal data is any data in " 00 " to " FF ".
3. BIOS debugger as claimed in claim 1; It is characterized in that; Said seven segment digital tubes is on the insulating material of definite shape; Utilize light emitting diode LED assembled arrangement to become the charactron of " 8 " font, the electrode of drawing LED respectively demonstrates 0 to 9 numeral or the character of A to F through lighting corresponding dot-dash.
4. BIOS debugger as claimed in claim 1 is characterized in that, this BIOS debugger is to supply power through said USB interface.
5. a BIOS adjustment method is characterized in that, this method may further comprise the steps:
Utilize single-chip microcomputer to pass through the BIOS burning data signal that the general-purpose serial bus USB interface receives the serial transmission form of control computer output;
Utilize this single-chip microcomputer that the BIOS burning data conversion of signals of serial transmission form is become the BIOS burning data signal of parallel transmission form, and export the BIOS burning data signal of parallel transmission form to the on-site programmable gate array FPGA chip;
Utilize fpga chip with the BIOS burning data signal storage of parallel transmission form to random access memory ram;
Utilize fpga chip from RAM, to read the BIOS burning data signal of parallel transmission form; After the BIOS burning data conversion of signals of parallel transmission form become the data-signal of SPI SPI transmission format protocol; Export computing machine to be measured to through the SPI interface, so that computing machine to be measured is carried out startup self-detection POST;
Utilize fpga chip to pass through the POST data-signal that low pin number interface LPC interface receives computing machine output to be measured, and after converting this POST data-signal to a double-digit hexadecimal data, export two seven segment digital tubes to; And
Utilize these two seven segment digital tubes to show said double-digit hexadecimal data; From the POST code table, search the implication of this double-digit hexadecimal data for the designer, thereby locate the fault that occurs in POST stage or the POST process of computing machine to be measured.
6. BIOS adjustment method as claimed in claim 5 is characterized in that, its said double-digit hexadecimal data is any data in " 00 " to " FF ".
7. BIOS adjustment method as claimed in claim 5; It is characterized in that; Said seven segment digital tubes is on the insulating material of definite shape; Utilize light emitting diode LED assembled arrangement to become the charactron of " 8 " font, the electrode of drawing LED respectively demonstrates 0 to 9 numeral or the character of A to F through lighting corresponding dot-dash.
8. BIOS adjustment method as claimed in claim 5 is characterized in that, said single-chip microcomputer, fpga chip, RAM and seven segment digital tubes are to supply power through said USB interface.
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| CN2010102668156A CN102385545A (en) | 2010-08-30 | 2010-08-30 | BIOS (Basic Input Output System) debugger and debugging method |
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| CN2010102668156A CN102385545A (en) | 2010-08-30 | 2010-08-30 | BIOS (Basic Input Output System) debugger and debugging method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103049380A (en) * | 2012-12-22 | 2013-04-17 | 中国船舶重工集团公司第七0九研究所 | VBIOS (video basic input output system) debugging method for special display controller |
| CN103729221A (en) * | 2013-12-30 | 2014-04-16 | 合肥联宝信息技术有限公司 | Method and device for writing BIOS debugging information into hard disk |
| CN104063297A (en) * | 2014-07-16 | 2014-09-24 | 合肥联宝信息技术有限公司 | Method and device capable of diagnosing computer hardware through USB interfaces |
| CN105718338A (en) * | 2014-12-05 | 2016-06-29 | 联想(北京)有限公司 | Information processing method and electronic device |
| CN110399596A (en) * | 2019-07-26 | 2019-11-01 | 浪潮电子信息产业股份有限公司 | A kind of file layout change-over method, system and associated component |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103049380A (en) * | 2012-12-22 | 2013-04-17 | 中国船舶重工集团公司第七0九研究所 | VBIOS (video basic input output system) debugging method for special display controller |
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| CN103729221A (en) * | 2013-12-30 | 2014-04-16 | 合肥联宝信息技术有限公司 | Method and device for writing BIOS debugging information into hard disk |
| CN104063297A (en) * | 2014-07-16 | 2014-09-24 | 合肥联宝信息技术有限公司 | Method and device capable of diagnosing computer hardware through USB interfaces |
| CN105718338A (en) * | 2014-12-05 | 2016-06-29 | 联想(北京)有限公司 | Information processing method and electronic device |
| CN105718338B (en) * | 2014-12-05 | 2019-08-27 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| CN110399596A (en) * | 2019-07-26 | 2019-11-01 | 浪潮电子信息产业股份有限公司 | A kind of file layout change-over method, system and associated component |
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Application publication date: 20120321 |