CN103049380B

CN103049380B - A kind of VBIOS adjustment method of special display controller

Info

Publication number: CN103049380B
Application number: CN201210561700.9A
Authority: CN
Inventors: 刘天玥; 秦信刚; 高齐; 黄亮
Original assignee: 709th Research Institute of CSIC
Current assignee: Wuhan Lingjiu Microelectronics Co ltd; 709th Research Institute of CSSC
Priority date: 2012-12-22
Filing date: 2012-12-22
Publication date: 2016-02-17
Anticipated expiration: 2032-12-22
Also published as: CN103049380A

Abstract

A VBIOS adjustment method for special display controller, be a kind of FPGA Qualify Phase hardware and software at display controller combine debugging VBIOS method.Be made up of following steps, (1) sets up the FPGA engineering of special display controller at main frame, the signal one_to_one corresponding in VBIOS register parameters and fpga logic design; (2) main frame completes initialization to FPGA by jtag interface; (3) main frame is read by jtag interface and obtains from FPGA debug platform the data needed, and the seven segment digital tubes be simultaneously connected with FPGA also can show these data; (4) designer judges the executing state of VBIOS according to parameter value and to interpretation of result, the problem in the VBIOS design of location also solves.The method can simplify VBIOS debug process, thus it is simple efficient that VBIOS is debugged, and saves cost of development and time.

Description

A kind of VBIOS adjustment method of special display controller

Technical field

The present invention relates to special display controller technical field, specifically a kind of method of debugging VBIOS combined at the FPGA Qualify Phase hardware and software of special display controller.

Background technology

VBIOS(VideoBasicInputOutputSystem) be the display control program that a group and display controller are combined closely, be solidificated in ROM, become a part for video card.Even to this day, often kind of display controller has the special VBIOS of oneself to support, but all VBIOS support VGA (Videographicsarray) standard and VBE (VESABIOSExtension) standard bar none.VGA standard is that IBM Corporation in 1987 formulates video card standard, comprise VGA register standard and VGABIOS standard, later stage is due to the development of display technique, VGA standard cannot meet application demand, video electronics standard association VESA (VideoElectronicsStandardsAssociation) proposes the VBIOS funcall interface standard of one group of expansion, i.e. VBE (VESABIOSExtension), software interface level achieves the compatibility between various video card.VBIOS function comprises the interrupt service routine of video card initialization program and INT10H.Operating system or driver pass through VIBOS interface to the basic operation of display controller, as adjustment resolution, color depth, refresh rate etc.

VBIOS design is closely related with display controller bottom hardware, and deviser wishes to identify FPGA hardware design mistake and VBIOS design software mistake.But VBIOS designs complexity, and only has software interface standard, traditional hardware debug method is difficult to identify VBIOS design problem.Meanwhile, VBIOS debugging faces the problem that display terminal can not show any information, and limit the use of traditional software debugging method, conventional debugger means are fewer.

In order to solve above-mentioned problems of the prior art, the present invention utilizes the feature of VBIOS funcall, proposes a kind of adjustment method combined based on the software and hardware of FPGA.

Summary of the invention

The object of this invention is to provide a kind of VBIOS adjustment method of special display controller, involved special display controller and VBIOS be compatible with VGA standard and VBE standard.The present invention realizes simply, by jtag interface, the parameter that be concerned about VBIOS calls can be sent to main frame, locates VBIOS executing location and executing state easily.

A VBIOS adjustment method for special display controller, described debugging enironment comprise an integrated FPGA, jtag interface, seven segment digital tubes, VBIOS chip special display controller FPGA debug platform and accept the main frame of sampled data.

A VBIOS adjustment method for special display controller, its step is as follows:

(1) set up the FPGA engineering of special display controller at main frame, the signal one_to_one corresponding during VBIOS register parameters and fpga logic are designed also sets sampling condition, and then logic compiler generates FPGA configuration file;

(2) FPGA configuration file downloads to the FPGA debug platform of special display controller from main frame by jtag interface, and the signal during VBIOS register parameters and fpga logic design sets up corresponding relation, completes FPGA initialization;

(3) after powering on, the FPGA debug platform of display controller is started working, and according to sampling condition, main frame is read by jtag interface and obtains from FPGA debug platform the data needed, and the seven segment digital tubes be simultaneously connected with FPGA also can show these data;

(4) the VBIOS register parameters value that obtains according to main frame of designer, according to parameter value judge VBIOS executing state and to interpretation of result, thus problem in the VBIOS design of location solving.

Cardinal principle of the present invention is as follows: the fpga logic project engineering that designer sets up at main frame, the signal one_to_one corresponding in VBIOS register parameters and fpga logic design, by JTAG technology, to FPGA initialization, main frame just can access the internal register of FPGA and the VBIOS register parameters of loading by jtag interface.VBIOS funcall is unified simultaneously uses INT10H function, inputs one group of register parameters, then return parameters value, realizes various Presentation Function.Therefore, designer is easy to VBIOS executing location location according to the VBIOS register parameters value that main frame obtains, and analyzes hardware or Software for Design produced problem.

The advantage of the VBIOS adjustment method of the special display controller of the present invention is: (1) this VBIOS adjustment method can correctly identify VBIOS practice condition, accurate location VBIOS executing location, solves the difficult problem that conventional hardware adjustment method is difficult to identify VBIOS design problem; (2) when VBIOS debugging face display terminal can not show any information, this VBIOS adjustment method still can obtain the data of needs and obtain VBIOS practice condition, breaches traditional software adjustment method and needs the just operable restriction of display information; (3) this VBIOS adjustment method is simple and convenient, just can be obtained the data of needs by jtag interface, does not need other debugging acids, saves expensive expense and time.This VBIOS adjustment method has solved the VBIOS design problem of a special display controller well, and this special display controller is working properly at present.

Accompanying drawing explanation

Fig. 1 VBIOS adjustment method logical organization schematic diagram;

Fig. 2 VBIOS adjustment method process schematic.

embodiment:

Root Ju Fig. 1, shown in Fig. 2 ,a VBIOS adjustment method for special display controller, its step is as follows :

1. loading parameters and sampling condition

Designer sets up the FPGA engineering of special display controller at main frame, in this FPGA engineering, load specific logic signals simultaneously, the register parameters one_to_one corresponding such as these logical signals and AX, BX, CX, DX, ES, DI used by VBIOS function, set sampling condition simultaneously.Sampling condition is set to and there occurs INT10H funcall, and the register parameters such as such AX, BX, CX, DX, ES, DI have just had its meaning, for lower surface analysis VBIOS is ready.After above condition is established, designer forms FPGA configuration file to the compiling of fpga logic project engineering.

2. by jtag interface, parameter is outputted to the FPGA debug platform of special display controller

FPGA configuration file downloads to FPGA by jtag interface, and the signal during VBIOS register parameters and fpga logic design establishes corresponding relation, completes FPGA initialization.

The seven segment digital tubes that 3.VBIOS parameter value outputs to main frame or is connected with FPGA

Main frame reads from the FPGA debug platform of special display controller the sampling condition arranged according to main frame by jtag interface and obtains the data needed, and the seven segment digital tubes be simultaneously connected with FPGA also can show these data.

4. analyze VBIOS parameter value

The logical design of special display controller FPGA and VBIOS design compatible with VGA standard and VBE standard.VGA funcall specifies: AH equals the function number of VGA; AH < 13H; Call INT10H.VBE funcall specifies: AH must equal 4Fh, illustrates and calls VBE function; AL equals the function number of VBE; BL equals subfunction number, also can not have subfunction; Call INT10H; Rreturn value is all in AX.The implementation status analyzing VBIOS is easy to according to above regulation.

If sampling condition does not occur, illustrate that the VBIOS function of specifying does not perform, analyze VBIOS program and whether jumped out.If sampling condition there occurs, judge to have invoked which function from register parameters values such as AX, BX, CX, DX, ES, DI, finally whether these functions correctly perform, and whether rreturn value meets the requirements, and from returning AX parameter location VBIOS executing location.If rreturn value AX value is 0, illustrate that this interruption IO function correctly performs, if fruit AX value is 1, illustrate that interrupting IO function does not correctly perform.

Claims

1. a VBIOS adjustment method for special display controller, is characterized in that, its step is as follows:

(2) FPGA configuration file generated is downloaded to the FPGA debug platform of special display controller above from main frame by jtag interface, the signal during VBIOS register parameters and fpga logic design sets up corresponding relation;

(3) main frame is read by jtag interface and obtains from the FPGA debug platform of special display controller the data needed, and the seven segment digital tubes be simultaneously connected with FPGA can show these data;

(4) the VBIOS register parameters value that designer obtains according to main frame is located VBIOS executing location, and analyzes hardware or Software for Design produced problem;

If sampling condition does not occur, illustrate that the VBIOS function of specifying does not perform, analyze VBIOS program and whether jumped out; If sampling condition there occurs, judge to have invoked which function from AX, BX, CX, DX, ES, DI register parameters value, finally whether these functions correctly perform, and whether rreturn value meets the requirements, and from returning AX parameter location VBIOS executing location.

2. the VBIOS adjustment method of a kind of special display controller as claimed in claim 1, it is characterized in that, in described step (1), be loaded into the logical signal of special display controller FPGA engineering, be one to one with VBIOS register parameters, make logical signal have specific meaning.

3. the VBIOS adjustment method of a kind of special display controller as claimed in claim 1, it is characterized in that, in described step (2), be by jtag interface to FPGA initialization, FPGA debug platform FPGA configuration file being downloaded to special display controller has come.

4. the VBIOS adjustment method of a kind of special display controller as claimed in claim 1, it is characterized in that, in described step (3), it is obtained by jtag interface that main frame obtains from the FPGA debug platform of special display controller the parameter information be concerned about.