201211761 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種BIOS調試器及調試方法。 [先前技術3 [0002] 目前，基本輸入輸出系統（basic input/output sys- tem ’ BIOS)開發部門調試BIOS的方法主要包括以下步 驟：將待測電腦上需要調試的BIOS晶片拔下，將該需要 調試的BIOS晶片安裝至一台正常工作的電腦，再透過燒 錄程式將燒錄資料（例如BIOS原始檔或BIOS更新檔）燒 錄至該需要調試的BIOS晶片。之後，將該需要調試的 BIOS晶片從所述電腦拔下，插回待測電腦，.對待測電腦 上電執行開機自檢（power. .on sel f. test ’ POST )， 檢查該待測電腦各元件是否工作正常。 [0003] 這種調試方法的不足之處在於BIOS晶片的多次取下放上 比較浪費時間。由於BIOS功能的不斷強大不同待測電 腦的BIOS晶片容量也越來越大，燒錄時間隨之增長。此 外’如果待測電腦還未到開啟螢幕顯示階段或者是出現 關鍵性故障，螢幕上無顯示時，設計人員無法得知POST 所處階段或是無法判斷待測電腦故障所在，需要利用 P0ST診斷卡’根據POST診斷卡上顯示的代碼查找POST代 碼表得知待夠電腦POST所處階段或故障原因和故障部位 ，給測試帶來不便且浪費時間。 【發明内容】201211761 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a BIOS debugger and a debugging method. [Prior Art 3 [0002] At present, the basic input/output system (BIOS) development department debugs the BIOS mainly includes the following steps: unplugging the BIOS chip to be tested on the computer to be tested, The BIOS chip to be debugged is installed on a working computer, and then burned data (such as BIOS original file or BIOS update file) is burned to the BIOS chip to be debugged through a burning program. After that, the BIOS chip that needs to be debugged is unplugged from the computer, and inserted into the computer to be tested. The computer to be tested is powered on to perform a power-on self-test (power. .on sel f. test ' POST ), and the computer to be tested is checked. Whether each component is working properly. [0003] A disadvantage of this method of debugging is that it is a waste of time to remove the BIOS chip multiple times. Due to the ever-increasing power of the BIOS, the BIOS chip size of the computer to be tested is also increasing, and the programming time is increasing. In addition, if the computer to be tested has not yet turned on the screen display stage or there is a critical fault, there is no display on the screen, the designer can not know the stage of the POST or can not judge the fault of the computer to be tested, need to use the P0ST diagnostic card 'Find the POST code table according to the code displayed on the POST diagnostic card to know the stage of the PC POST or the cause of the fault and the fault location, which is inconvenient and time consuming. [Summary of the Invention]
[0004] 冑於以上内容，本發明提供—種BIGS調試器及調試方法 ，可以希省調試時間，提高燒錄速度且不依賴於p〇ST 099130051 表單編號A0101 第4頁/共15頁 0992052724-0 201211761 診斷卡顯示調試進度及狀態。 [0005] Ο ❹ -種則㈣試器，該BI〇S調試器包括微控制器、現場可 編程閘陣册GAW、隨機麵儲存现M及兩個七段數 位管。所述FPGA晶片與微控制器、RAM及兩個七段數位管 相連接。所述微控制器，透過通用串列匯流排USB介面連 接控制電腦。該微控制器透過USB介面接收控制電腦輸出 的串列傳輸格式的BIOS燒錄資料訊號，將串列傳輸格式 的B10S燒錄資料訊號轉換成並列傳輸格式的B丨〇s燒錄資 料訊號後輸出至所述FPGA晶片。所述FPGA晶片透過串列 週邊介面SPI及低腳位數介面lpc與待測電腦相連接。該 FPGA晶片將並列傳輸格式的B〗0S燒錄資料訊號儲存至 RAM ’將從RAM中讀取的並列傳輸格式的bios燒錄資料傳 輸轉換成SPI通信協定格式的資料訊號後，透過spi介面 輸出至待測電腦，以對待測電腦進行POST。該FPGA晶片 還透過LPC介面接收待測電腦輸出的POST資料訊號，將該 POST資料訊號轉換成一個兩位數的十六進位資料後，輸 出至所述兩個七段數位管0 r所述兩個七段數位管顯示所 述兩位數的十六進位資料，以供設計人員從POST代碼表 中查找該兩位數的十六進位資料的含義，從而定位待測 電腦的POST階段或POST過程中出現的故障。 [0006] 一種BIOS調试方法’該方法包括以下步驟.（A)利用微 控制器透過USB介面接收控制電腦輸出的串列傳輸格式的 BIOS燒錄資料訊號；（B)利用該微控制器將串列傳輸格 式的BIOS燒錄資料訊號轉換成並列傳輸格式的BIOS燒錄 資料訊號，並將並列傳輸格式的BIOS燒錄資料訊號輸出 099130051 表單編號A0101 第5頁/共15頁 0992052724-0 201211761 至FPGA晶片；（C)利用FPGA晶片將並列傳輸格式的 BIOS燒錄資料訊號儲存至RM; (D)利用叩以晶片從 RAM中讀取並列傳輪格式的BI0S燒錄資料訊號，將並列傳 輸格式的B10S燒錄資料訊號轉換成SP丨通信協定格式的資 料訊號後，透過SPI介面輸出至待測電腦，以對待測電腦 進行POST; (E)利用FPGA晶片透過LPC介面接收待測電 腦輸出的POST資料訊號，並將該P0ST資料訊號轉換成一 個兩位數的十六進位資料後，輸出至兩個七段數位管； 及（F)利用該兩個七段數位管顯示所述兩位數的十六進 位資料，以供設計人員從P0ST代碼表中查找該兩位數的 十六進位資料的含義，從而定位待測電腦的p〇ST階段或 POST過程中出現的故障。 [0007] [0008][0004] In view of the above, the present invention provides a BIGS debugger and a debugging method, which can save debugging time and improve programming speed without depending on p〇ST 099130051 Form No. A0101 Page 4 / Total 15 Page 0992052724- 0 201211761 The diagnostic card shows the progress and status of the commissioning. [0005] Ο ❹ - (4) tester, the BI〇S debugger includes a microcontroller, a field programmable gatebook GAW, a random surface storage M and two seven-segment digital tubes. The FPGA chip is connected to a microcontroller, a RAM, and two seven-segment digital tubes. The microcontroller is connected to the control computer via a universal serial bus USB interface. The microcontroller receives the BIOS burning data signal of the serial transmission format controlled by the computer through the USB interface, and converts the B10S burning data signal of the serial transmission format into a B丨〇s burning data signal of the parallel transmission format and outputs the data. To the FPGA chip. The FPGA chip is connected to the computer to be tested through the serial peripheral interface SPI and the low-digit bit interface lpc. The FPGA chip stores the B_0S programming data signal in the parallel transmission format to the RAM. The bios programming data transmission in the parallel transmission format read from the RAM is converted into the data signal in the SPI communication protocol format, and then output through the spi interface. Go to the computer to be tested and perform POST on the computer to be tested. The FPGA chip also receives the POST data signal outputted by the computer to be tested through the LPC interface, converts the POST data signal into a two-digit hexadecimal data, and outputs the two to the two seven-segment digital tube 0 r The seven-segment digital tube displays the two-digit hexadecimal data for the designer to look up the meaning of the two-digit hexadecimal data from the POST code table to locate the POST phase or POST process of the computer to be tested. A failure that occurred in the middle. [0006] A BIOS debugging method includes the following steps: (A) using a microcontroller to receive a BIOS programming data signal in a serial transmission format that controls a computer output through a USB interface; (B) using the microcontroller The BIOS burning data signal of the serial transmission format is converted into the BIOS burning data signal of the parallel transmission format, and the BIOS burning data signal output of the parallel transmission format is 099130051. Form number A0101 Page 5 / 15 pages 0992052724-0 201211761 FPGA chip; (C) use the FPGA chip to store the BIOS burning data signal of the parallel transmission format to the RM; (D) use the chip to read the BI0S programming data signal in the parallel transmission format from the RAM, and the parallel transmission format The B10S burned data signal is converted into the data signal of the SP丨 communication protocol format, and then output to the computer to be tested through the SPI interface to perform POST on the computer to be tested; (E) use the FPGA chip to receive the POST output of the computer to be tested through the LPC interface. Data signal, and convert the P0ST data signal into a two-digit hexadecimal data, and output to two seven-segment digital tubes; and (F) use the two seven-segment The bit tube displays the two-digit hexadecimal data for the designer to look up the meaning of the two-digit hexadecimal data from the P0ST code table, thereby locating the p〇ST phase or POST process of the computer to be tested A failure has occurred. [0007] [0008]
相較於習知技術，本發明所提供之8103調試器及調試方 法，以大容量的RAM替代BIOS晶片，故不需要在待測電腦 上安裝BIOS晶片進行P0ST挪試，以七段數位管替代p〇ST 診斷卡顯示制電腦賴ST狀態，賴成本低且速度快 〇 【實施方式】 參閱圖1所示’是本發明基本輸入輸出系統（basic in-Compared with the prior art, the 8103 debugger and the debugging method provided by the present invention replace the BIOS chip with a large-capacity RAM, so it is not necessary to install a BIOS chip on the computer to be tested for P0ST stealing test, and replace the seven-segment digital tube with a seven-segment digital tube. The p〇ST diagnostic card shows that the computer is in the ST state, and the cost is low and the speed is fast. [Embodiment] Referring to Figure 1 is the basic input/output system of the present invention (basic in-
Put/〇Utput system，BI〇s)調試器較佳實施例的功能 模組圖。該BIOS調試器1〇〇包括微控制器1〇、現場可編 ίΐηρ+^'j ( f ield~programmable gate array, FPGA )3^20 (rand〇m access mem〇ry ’ RAM) 30及兩個七段數位管40。FPGA晶片20與微控制 器10 RAM 30及兩個七段數位管樹目連接。微控制器 099130051 表單編號A0101 第6頁/共15頁 0992052724-0 201211761 Ο [0009] 透過通用串列匯流排（universal serial bus，USB) 介面11連接控制電腦200，並透過USB介面n接收控制電 腦200輸出的串列傳輸格式的^⑽燒錄資料訊號。之後， 微控制器10將串列傳輸格式的BIOS燒錄資料訊號轉換成 並列傳輸格式的BIOS燒錄資料訊號，以提高資料傳輪速 率，並將並列傳輸格式的BIOS燒錄資料訊號輸出至FPga 晶片20。例如，微控制器1〇可以將接收到61仍燒錄資料 中的 xxx.bln” 、 “xxx.rom” 、 “xxx.hex” 等檔案 中的資料訊號由串列傳輸格式轉換為並列傳輸格式。 FPGA晶片20透過串列週邊介面（serial peripheral interface ’ SPI ) 21 及低腳位數（i〇w pin count， LPC)介面22與待測電腦3〇0相連接。 [0010] 設計人員可以根據需要設置FPGA晶片2仏的邏輯單元，使 FPGA晶片20具有不同的邏輯功能。在本貪施例中，fpga 晶片20具有以下邏輯功能： 0 _ FPGA晶片2〇將並列身_格武^BI〇s燒縴資料訊號儲存至 RAM 30。當需要對待測電腦3〇〇進行測試時，fpga晶片 20從RAM 30中讀取並列傳輸格式的81〇8燒錄資料訊號， 將並列傳輸格式的BIOS燒錄資料訊號轉換成spi通訊協定 格式的資料訊號，透過SPI介面21輸出至待測電腦3〇〇， 以對待測電腦300進行開機自檢（p0wer⑽self test ’ POST)。FPGA晶片20透過LPC介面22接收待測電腦 300輸出的post資料訊號，將該P0ST資料訊號轉換成一 個兩位數的十六進位資料（從〇〇〜FF)後，輸出至兩個七 段數位管40。 099130051 表單編號A0101 第7頁/共15頁 0992052724-0 201211761 [0012] [0013] [0014] [0015] [0016] [0017] 七段數位管4 0顯+ 4 τ 頌不该兩位數的十六進位資料，設計人員 可以從POST代碼表巾查找該兩位數的十六進位資料的含 義以定位待'則電腦3〇〇的POST階段或POST過程中出現 的故障。例如“ 〇 n，，+ υ〇代表POST當前階段為“已顯示系統 的配置”，“ m，，化士 η υι代表post當前階段為處理器測試。七 #又數位官4〇是在—定形狀的絕緣材料上，利用發光二級 吕（light-emitting diode，LED)組合排列成 “8” Μ的數位管’分別引出LED的電極，點亮相應的點來顯 示出〇-9的數字或是A_F的字元。 在本實施例中’所述微控制器10、FPGA晶片20、RAM30 及七^又數位管4〇是透過所述|^技介 面11進行供電。 參閱圖2所示’係本發明BI〇s調試方法較佳實施例的流程 圖°需要指出的是，在執行以下方法之前'，首先要透過 USB介面11對BI〇S調試器1〇〇進行上電，上電後對BIOS 調试器100的各組成部分進行初始化動作，確認各組成部 分能夠正常工作。 步驟S201 ’微控制器10透過USB介面11接收控制電腦200 輸出的串列傳輸格式的BIOS燒錄資料訊號。 步驟S203 ’微控制器10將串列傳輸格式的^㈧燒錄資料 讯號轉換成並列傳輸格式的BI〇s燒錄資料訊號，並將並 列傳輪格式的BIOS燒錄資料訊號輸出至FPGA晶片2〇。 步驟S205 ’ FPGA晶片20將並列傳輸格式的BIOS燒錄資料 訊號儲存至RAM 30。 [0018]Put/〇Utput system, BI〇s) The function of the preferred embodiment of the debugger module diagram. The BIOS debugger 1 includes a microcontroller 1 现场, a field programmable ΐρ+^'j (f ield~programmable gate array, FPGA) 3^20 (rand〇m access mem〇ry 'RAM) 30 and two Seven-segment digital tube 40. The FPGA chip 20 is connected to the micro controller 10 RAM 30 and two seven-segment digital tube trees. Microcontroller 099130051 Form No. A0101 Page 6 of 15 0992052724-0 201211761 Ο [0009] Connect the control computer 200 through the universal serial bus (USB) interface 11 and receive the control computer via the USB interface n 200 output serial transmission format ^ (10) burn data signal. After that, the microcontroller 10 converts the BIOS burning data signal of the serial transmission format into a BIOS burning data signal of the parallel transmission format to improve the data transmission rate, and outputs the BIOS burning data signal of the parallel transmission format to the FPga. Wafer 20. For example, the microcontroller 1 can convert the data signals in the files of xxx.bln", "xxx.rom", "xxx.hex", etc., which are still in the 61 still burning data, from the serial transmission format to the parallel transmission format. The FPGA chip 20 is connected to the computer to be tested 3〇0 through a serial peripheral interface 'SPI' 21 and a low pin count (LPC) interface 22. [0010] The designer can It is necessary to set the logic unit of the FPGA chip to make the FPGA chip 20 have different logic functions. In the embodiment, the fpga chip 20 has the following logic functions: 0 _ FPGA chip 2〇 will be side by side _格武^BI〇 s burnt fiber data signal is stored in RAM 30. When it is necessary to test the computer to be tested, the fpga chip 20 reads the 81〇8 burn data signal of the parallel transmission format from the RAM 30, and burns the parallel formatted BIOS. The data signal converted into the spi communication protocol format is output to the computer to be tested through the SPI interface 21, and the PC 300 is subjected to a self-test (p0wer(10) self test 'POST). The FPGA chip 20 is connected through the LPC interface 22. The post data signal outputted by the test computer 300 is received, and the P0ST data signal is converted into a two-digit hexadecimal data (from 〇〇 to FF), and then output to two seven-segment digital tubes 40. 099130051 Form No. A0101 [0017] [0017] [0017] [0017] Seven-segment digital tube 4 0 display + 4 τ 颂 not the two-digit hexadecimal data The designer can look up the meaning of the two-digit hexadecimal data from the POST code table to locate the fault that occurs during the POST phase or POST of the computer. For example, "〇n,, + υ〇 On behalf of the current stage of POST is "configured system configuration", "m,, 士士 η υι represents the current stage of the post for the processor test. Seven #又数官4〇 is on the shape of the insulating material, using the light two The light-emitting diode (LED) is arranged in a combination of "8" Μ digital tube's respectively lead to the LED electrode, and the corresponding point is illuminated to display the 〇-9 number or the A_F character. In the example, the microcontroller 10, the FPGA chip 20, the RAM 30, and the seven The bit tube 4 is powered by the ^^ technology interface 11. Referring to Figure 2, a flow chart of a preferred embodiment of the BI〇s debugging method of the present invention. It should be noted that before performing the following method, First, the BI〇S debugger 1 is powered on through the USB interface 11. After power-on, the components of the BIOS debugger 100 are initialized to confirm that each component can work normally. Step S201' The microcontroller 10 receives the BIOS programming data signal of the serial transmission format outputted by the control computer 200 via the USB interface 11. Step S203: The microcontroller 10 converts the (8) programming data signal of the serial transmission format into the BI〇s programming data signal of the parallel transmission format, and outputs the BIOS burning data signal of the parallel transmission format to the FPGA chip. 2〇. Step S205' The FPGA chip 20 stores the BIOS burn data signal in the parallel transfer format to the RAM 30. [0018]
步驟S207，FPGA晶片20從RAM 30讀取並列傳輸格式的 099130051 表單編號A0101 第8頁/共15頁 0992052724-0 201211761Step S207, the FPGA chip 20 reads the parallel transmission format from the RAM 30. 099130051 Form No. A0101 Page 8 of 15 0992052724-0 201211761
[0019] [0020] Ο [0021] [0022] [0023] G[0020] [0023] [0023] G
[0024] [0025] BIOS燒錄資料訊號’將並列傳輸格式的BI0S燒錄資料訊 號轉換成SPI通信協定格式的資料訊號。 步驟S209，FPGA晶片20將SPI通信協定格式的資料訊號 透過SPI介面21輸出至待測電腦3 〇 〇，以對待測電腦3 0 0 進行POST。 步驟S211，FPGA晶片20透過LPC介面22接收待測電腦 300輸出的POST資料訊號’將該p〇ST資料訊號轉換成一 個兩位數的十六進位資料（從〇〇〜FF)後，輸出至兩個七 段數位管40。 步驟S213，兩個七段數位管40顯示所述兩位數的十六進 位資料。 ：…Ϊ. 步驟S215，設計人員從POST代碼表中查找該兩位數的十 六進位資料的含義’以定位待測電腦3〇〇的POST階段或 POST過程中出現的故障。 最後應說明的是，以Ji實施方式僅用以說明本發明的技 術方案而非限制，儘管參照較:佳i實.施方式對本發明進行 了詳細說明，本領域的普通技術人員應當理解，可以對 本發明的技術方案進行修改或等同替換，而不脫離本發 明技術方案的精神和範圍。 【圖式簡單說明】 圖1係本發明BIOS調試器較佳實施例之功能模組圖。 圖2係本發明BIOS調試方法較佳實施例之流程圖。 【主要元件符號說明】 099130051 表單編號Α0101 第9頁/共15頁 0992052724-0 201211761 [0026] BIOS調試器：100 [0027] 控制電腦：2 0 0 [0028] 微控制器：10 [0029] FPGA晶片：20 [0030] RAM ： 30 [0031] 七段數位管：40 [0032] USB介面：11 [0033] SPI 介面：21 [0034] LPC介面：22 [0035] 待測電腦：300 099130051 表單編號A0101 第10頁/共15頁 0992052724-0[0025] The BIOS burning data signal 'converts the BI0S programming data signal in the parallel transmission format into the data signal in the SPI communication protocol format. In step S209, the FPGA chip 20 outputs the data signal of the SPI communication protocol format to the computer to be tested 3 〇 through the SPI interface 21, and performs POST on the computer to be tested 300. In step S211, the FPGA chip 20 receives the POST data signal output by the computer 300 to be tested through the LPC interface 22, and converts the p〇ST data signal into a two-digit hexadecimal data (from 〇〇 to FF), and then outputs the result to Two seven-segment digital tubes 40. In step S213, the two seven-segment digital tubes 40 display the two-digit hexadecimal data. :...Ϊ. In step S215, the designer looks up the meaning of the two-digit hexadecimal data from the POST code table to locate the fault in the POST phase or the POST process of the computer to be tested. Finally, it should be noted that the Ji embodiment is only used to explain the technical solution of the present invention and is not limited thereto, although the present invention is described in detail with reference to the preferred embodiment, those skilled in the art should understand that Modifications or equivalents of the technical solutions of the present invention are made without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a functional block diagram of a preferred embodiment of the BIOS debugger of the present invention. 2 is a flow chart of a preferred embodiment of the BIOS debugging method of the present invention. [Main component symbol description] 099130051 Form number Α0101 Page 9/15 page 0992052724-0 201211761 [0026] BIOS debugger: 100 [0027] Control computer: 2 0 0 [0028] Microcontroller: 10 [0029] FPGA Wafer: 20 [0030] RAM: 30 [0031] Seven-segment digital tube: 40 [0032] USB interface: 11 [0033] SPI interface: 21 [0034] LPC interface: 22 [0035] Computer to be tested: 300 099130051 Form number A0101 Page 10 of 15 0992052724-0