TW202004501A - Memory inspecting system, memory inspecting method, and error mapping table building method for memory inspecting - Google Patents

Abstract

The present invention provides a memory inspecting system, the method thereof, and an error mapping table building method. The memory inspecting method is used for inspecting a memory of a device under test. The memory inspecting method includes: retrieving an error mapping table corresponding to the device under test, the error mapping table including a set of mapping address data and a set of data line data, in which the set of mapping address includes a plurality of mapping addresses of the memory, and the set of data line data includes a plurality of data line designators of the data lines of the memory, each data line designator is mapped to a bit of each mapping address; writing a test pattern to each mapping address using the control unit; retrieving the address value of each mapping address using the control unit; determining bit by bit whether the address value is the same as the test pattern.

Description

Memory detection system, memory detection method, and method for establishing error mapping table for memory detection

The invention relates to a detection system and method, in particular to a memory detection system, a memory detection method, and a method for establishing an error mapping table for memory detection.

Generally speaking, the memory of the embedded system is designed to be directly soldered to the motherboard. Therefore, if the general module type memory has been tested at the factory, the memory test of the embedded system is matched with the motherboard The test is completed together.

Generally, the methods used to test assembled circuit boards are mainly divided into electrical test (In-Circuit Test, ICT), function test (FVT), automatic optical inspection (AOI), etc. The embodiment of the electrical test is to design a probe jig, and each probe on the probe corresponds to a pre-set component test point on the main board to be tested. In the actual test, the probe is connected to a single part or multiple parts through the test point, and the equivalent resistance, capacitance, inductance and voltage of the circuit in each region are used as the basis to determine whether the main board to be tested has bad soldering, Process errors such as missing parts and reverse electrical properties. In-Circuit Test (ICT) can be tested without turning on the motherboard, and does not need to be tested by professional circuit designers, so it can increase test speed and reduce costs. However, probe fixtures are costly and require regular maintenance and replacement. In addition, the electrical test method requires additional test points between the CPU and the memory, which affects the signal quality and also reduces the motherboard wiring utilization rate. In addition, when the motherboard is equipped with multiple memories, this test method will eventually lengthen the overall test time.

The function test is implemented by booting the motherboard to be tested and interpreting the boot output message of the boot program (Bootloader, or Boot code). However, the output information of the boot program needs to be interpreted by professionals, so the cost will increase. In addition, when the motherboard requires an encryption mechanism, the central processing unit (CPU) on the motherboard needs to support the encryption mechanism, and related boot information will also be turned off by default, which increases the difficulty of interpretation.

Based on the above, the technical problem to be solved by the present invention is to provide a memory detection system, a memory detection method, and an error mapping table creation method for memory detection to check the specific address of the memory Whether the address value after writing into the check byte is the same as the check byte, and when not the same, check the error mapping table to determine the fault condition of the memory.

In order to achieve the above object, one of the technical solutions adopted by the present invention is to provide a memory detection method to detect the memory of a device under test, wherein the memory detection method includes: reading an error corresponding to the device under test A mapping table, wherein the error mapping table includes: a set of mapped address data and a set of data line data, the set of mapped address data includes a plurality of mapped addresses of the memory, and the set of data line data includes the memory The plurality of data line names of the plurality of data lines of the body, where each data line name is mapped to each bit of each mapping address in the error mapping table; Write a check byte to the mapped address; read the bit value of the checked byte for each mapped address; determine the bit value of each bit of the address and the check Whether the bit value of the corresponding bit in the byte is the same; and if it is judged that at least one mapped address should check the bit value of at least one bit of the address value of the bit and the check byte The bit value of the corresponding bit in is different, and the memory is judged to be faulty.

In order to achieve the above object, another technical solution adopted by the present invention is to provide an error mapping table creation method for detecting a memory of a device under test. The error mapping table creation method includes: providing a fault-free device under test , The fault-free device under test includes a fault-free memory; a test fixture is provided, the test fixture includes: a test probe module; a switch module; and a micro-control unit, wherein the switch module Connected between the test probe module and the micro control unit; connecting the test probe module to one of the data lines of the fault-free memory of the fault-free device under test; controlled by the micro-control unit The switch module, so that one of the data lines of the fault-free memory, the test probe module and the switch module forms a short circuit; the micro-control unit All the addresses in the test address interval are written into a full 1-byte; the micro-control unit is used to determine whether all the addresses in the test address interval should be the full 1-byte address value. 1 byte; and if the address value of one of the addresses in the test address interval is not all 1 byte, the micro control unit creates an error mapping table corresponding to the device under test, One of the addresses, the address value of the one of the addresses, and the data line name of the one of the short-circuited data lines are stored in the error mapping table, and the one of them is created in the error mapping table The mapping relationship between the address, the address value of one of the addresses, and the data line name of the one of the short-circuited data lines.

In order to achieve the above object, another technical solution adopted by the present invention is to provide a memory detection system including a device to be tested and an electronic device. The device under test includes a memory. The electronic device includes a control unit, the device under test is connected to the electronic device, wherein the electronic device stores an error mapping table corresponding to the device under test, the error mapping table includes a set of mapping address data and a set of Data line data, the set of mapped address data includes a plurality of mapped addresses of the memory, a set of data line data, the set of data line data includes the names of the plurality of data lines of the memory, each of the data line names is in The error mapping table is mapped to each bit of each mapping address separately. The control unit is used to read the error mapping table and write a check byte to the plurality of mapping addresses of the memory according to the set of mapping address data of the error mapping table, and determine each The mapping address should check whether the bit value of each bit of the bit address value of the byte is the same as the bit value of the corresponding bit in the check byte, where, if the address value is The bit value of at least one bit is different from the bit value of the corresponding bit in the check bit group, the control unit determines that at least one of the data lines mapped to the at least one bit is faulty according to the error mapping table .

In order to further understand the mapping and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and explanation only, and are not intended to limit the present invention.

The following describes the implementation of the memory detection system, memory detection method, and error mapping table creation method disclosed by the present invention through specific specific examples and FIG. 1 to FIG. 6. Those skilled in the art can understand the content disclosed in this specification Understand the advantages and effects of the present invention. However, the content disclosed below is not intended to limit the protection scope of the present invention. Without departing from the spirit of the inventive concept, those skilled in the art can implement the present invention in other different embodiments based on different viewpoints and applications. In addition, it should be stated in advance that the drawings of the present invention are only schematic illustrations, and are not drawn according to actual sizes. In addition, although terms such as first, second, and third may be used herein to describe various elements, these elements should not be limited by these terms. These terms are mainly used to distinguish components.

First embodiment

1 and 2, the first embodiment of the present invention provides a memory detection system U as shown in FIG. 1 and a memory detection method using the memory detection system U as shown in FIG. 2. First, the components of the memory detection system U of this embodiment will be described based on FIG. 1. The memory detection method of this embodiment will be disclosed together with the description of FIG. 2.

As shown in FIG. 1, the memory detection system U of this embodiment includes a device under test 1 and an electronic device 2. The device under test 1 has a central processing unit 10 and a memory 11. The electronic device 2 has an input unit 20, a control unit 21, and an output unit 22. Specifically, in this embodiment, the device under test 1 may be a computer motherboard to be tested, and the electronic device 2 may be a desktop computer or a notebook computer, which has a control unit 21 to implement the above-mentioned memory detection method, and The output unit 22 (for example, a screen) is used for the inspection personnel to supervise the inspection situation. However, the present invention is not limited to the above. In addition, in this embodiment, the number of the memory 11 is two, however, the present invention does not limit the number of the memory 11. In other embodiments, the device under test 1 may be installed with only one memory 11 or with more than two memories 11.

The present embodiment takes the embedded memory 11 (embedded memory) as an example to describe the present invention, however, the present invention does not limit this. In other embodiments, the present invention may use an external memory or an internal memory device under test. In addition, the present invention also does not limit the connection method between the device under test 1 and the electronic device 2. The suitable adapter connection can be determined between the device under test 1 and the electronic device 2 according to the interface type of the device under test 1. For example, if the device under test 1 is a motherboard using an SPI interface, an SPI-USB adapter can be used to connect the device under test 1 and the electronic device 2; the present invention is not limited to the above example, in other embodiments, the device under test The device 1 can also use interfaces such as USB and I2C.

Referring to FIG. 2, the memory detection method in this embodiment includes step S100: the control unit 21 receives the information of the device under test, so that the control unit 21 reads the error mapping table corresponding to the device under test 1 according to the information of the device under test; steps S102: Read an error mapping table corresponding to the device under test 1 through the control unit 21, wherein the error mapping table includes a set of mapping address data and a set of data line data, and the mapping address data includes a plurality of mappings of the memory 11 Address, data line data includes a plurality of data line names of a plurality of data lines of the memory 11 (Data line). In the error mapping table, each data line name is mapped to each bit of each mapping address.

In this embodiment, the information of the device under test can be, for example, the model of the device under test 1, for example, the information of the device under test can be input by the maintenance personnel using the electronic device 2 to operate the input unit 20 (eg, a keyboard), and then, the control unit 21 Extract the error mapping table corresponding to the model according to the information of the device under test. However, the present invention is not limited to this. In other embodiments, for example, when the electronic device 2 is preset as the device under test 1 for detecting a specific model, step S100 may be omitted.

The error mapping table includes at least the mapping address and data line name of each memory 11. In this embodiment, the mapping address is the address where the access to the content value will be affected when any data line in the memory 11 is damaged. The name of each data line of each memory 11 is also stored in the error mapping table. Specifically, the name of the data line is the designator of the memory data line. In addition, in this embodiment, the error mapping table also has a component name (Component Reference Designator) in the circuit of each memory 11 of the device under test 1, however, the present invention is not limited to this.

Each data line name in the error mapping table is mapped to each bit of each mapping address in the error mapping table. In detail, since each data line corresponds to one bit of data, the error mapping table records which bit in each mapped address corresponds to each data line of each memory 11. The following will describe one embodiment of the error mapping table of the present invention with Table 1.

Table I

As shown in Table 1, the error mapping table of this embodiment stores the part names (U2001, U2002) of each memory 11 of the device under test 1, and the corresponding mapping address (0x80000001 to 0x80000015, 0x80000002 to 0x8000002A), each data line name (1D0 to 1D7, 2D0 to 2D7) of each memory 11 and the correspondence relationship between the data line name and the bit number in each memory 11. For example, as can be seen from Table 1, the data line 1D7 of the memory 11 with the part name U2001 corresponds to the 0th bit of the mapping address 0x80000001 to 0x80000015. For another example, in the memory with the part name U2002, the data line 2D5 corresponds to the third bit of the mapping address 0x80000002 to 0x8000002A.

Specifically, U2001, U2002, 1D0 to 1D7 and 2D0 to 2D7 are part names given to each memory 11 and each data line by the control unit 21. In this embodiment, 1D0 represents the 0th data line of the memory U2001, and 2D3 represents the 3rd data line of the memory U2002. However, the present invention is not limited to this. For example, the names of the parts of the memory or the data line can be set to the same or corresponding names according to the names of the parts actually given to the circuit diagram of the device under test 1, and due to different embodiments In the circuit diagram of the device under test 1, the part name setting method may be different, so it is not limited to this embodiment; the part name setting method of the memory and its data line in the error mapping table is better, so that the maintenance personnel can judge according to the circuit diagram Mistakes dominate. In addition, in other implementations, the error mapping table can separate the mapping addresses and data line names of different memories 11 through the arrangement of the table and the setting method of the data line specifier, so that the error mapping table need not include Memory specifier.

Next, referring to FIG. 2, the memory detection method of this embodiment performs step S104: the control unit 21 reads the mapped address data; step S106: the control unit 21 writes one to each mapped address read Check the byte; Step S108: Use the control unit 21 to read each mapped address corresponding to the bit value of the checked byte; Step S110: Use the control unit 21 to determine the bit of each bit of each address value The bit value is the same as the bit value of the corresponding bit in the check bit group; and Step S112: The control unit 21 determines that at least one data line mapped to at least one bit is faulty according to the error mapping table.

Taking the error mapping table in Table 1 as an example, in step S106, after reading all the mapping addresses in Table 1, the control unit 21 writes a check byte to all the mapping addresses, respectively. In this embodiment, the check byte is all 1 byte or all 0 bytes, that is, 11111111 or 00000000. There are two types of memory data line failures, namely open circuit and short circuit. When a data line forms an open circuit, the writing of 0 or 1 will fail for the address it affects, and the address value is always 1. In other words, when a data line is open, even if 0 is written to the address affected by it, when the address value is read back, the return value will still be 1. Therefore, when using the check byte of all 0s and writing the mapping address, it can be judged whether the data line is open. Conversely, when a data line forms a short circuit, for the address it affects, the action of writing 0 or 1 will be invalid, and the address value is always 0. That is, when a data line is short-circuited, even if a 1 is written to the address affected by it, when the address value is read back, the returned value will still be 0. Therefore, the use of all 1 check bytes can determine whether there is a short circuit in the data line.

Therefore, after performing steps S108 and S110, if the address value returned by the device under test 1 does not match the written check byte, the control unit 21 determines that the data line corresponding to the bit that does not meet the expected value is short-circuited or Open circuit (step 112). The following is further illustrated in Table 2.

Table II

Please refer to Table 2. When the control unit 21 writes all 0 bytes to the mapped address 0x80000009 of the memory 11 designated by U2001, the expected value of the control unit 21 for the mapped address will be all 0 bytes, in other words When the control unit 21 reads the address value of the check byte corresponding to the mapped address, it expects that the read back address value is all 0s. The reason why the expected value is set to be the same as the check byte is that if the data line of the memory U2001 is not faulty, the address value of the mapped address 0x80000009 after writing all 0 bytes should be all 0s. At this time, if the control unit 21 reads the address value after the mapped address 0x80000009 is written to all 0 bytes, and the returned value is 00100000, the data corresponding to the fifth bit of the memory U2001 can be determined The line is open. Next, the control unit 21 looks up the error mapping table. It can be seen from Table 1 that the fifth bit of the memory U2001 corresponds to the sixth data line of the memory U2001, and the control unit 21 determines that the sixth data line of the memory U2001 is an open circuit.

Please refer to Table 2 for details. Similarly, when the control unit 21 writes all 1-bytes to the mapping address 0x8000000A of the memory 11 designated by U2002, the control unit 21 expects the address value of the mapping address to be all ones. When the return value read by the control unit 21 from the mapped address is 11110111, it can be determined that the data line corresponding to the third bit of the memory U2002 is short-circuited. At this time, the control unit 21 looks up the error mapping table, and from Table 1, it can be seen that the data line corresponding to the third bit of the memory U2002 is the fifth data line of the memory U2002, then the control unit 21 will determine the memory The fifth data line of U2002 is short circuit.

In this embodiment, the control unit 21 can first write all the mapping addresses in the error mapping table to all 1 bytes, determine whether the memory 11 of the device under test 1 is short-circuited, and then write to all the mapping addresses All 0 bytes to determine whether the memory 11 of the device under test 1 has an open circuit. However, the present invention is not limited to this. For example, in the case where it is only necessary to judge the short circuit, only one byte can be written to the mapped address.

Further, as shown in FIG. 2, after step S112, this embodiment may further include step S114: the control unit 21 displays an error status of at least one data line corresponding to at least one bit through the output unit 22. After step S114, the memory test ends. For example, the output unit 22 may be a screen, and the control unit 21 uses the screen to display the memory detection result, where the detection result includes: the sixth data line of the memory U2001 is an open circuit, and the fifth data line of the memory U2002 Is a short circuit. The present invention is not limited to the above. In other embodiments, maintenance personnel test results can also be provided in other ways.

As shown in FIG. 2, in this embodiment, if the control unit 21 determines that the bit value of each bit of each address value is the same as the bit value of the corresponding bit in the check bit group, for example, If the expected value of the mapped address is the same as the return value, the control unit 21 determines that the memory 11 is fault-free and executes step S116: the control unit 21 indicates that the memory 11 is fault-free through the output unit 22, and the memory test is completed.

It is worth mentioning that, in other embodiments of the present invention, the memory detection method of this embodiment can be integrated with the boot file of the device under test 1, in this embodiment, the device under test 1 can be disposed in the electronic device 2 And step S100 can be omitted. When the device under test 1 encounters an error condition when it is turned on, the control unit 21 of the electronic device 2 directly starts the detection of the memory 11 from step S102.

In addition, in this embodiment, the control unit 21 of the electronic device 2 performs the reading of the error map, the writing operation of the check byte, and the judgment of the address value. However, the present invention is not limited thereto. In other embodiments, the above steps may be performed by, for example, but not limited to, the micro control unit built in the device under test 1 or the micro control unit built in the device under test 1 and the control unit of the electronic device 2 may be implemented together.

In addition, it should be noted that a data line failure is taken as an example in Table 2 to describe the manner in which the control unit 21 determines the data line failure situation according to the address value. However, the present invention is not limited to this. For example, in the embodiment of Table 1, when the mapped address of the memory U2001 is 0x80000001 and the return value after writing all 1 byte is 10111110, the table 4 can be judged to determine the fourth position of the memory U2001 The data line and the seventh data line are short-circuited at the same time.

In addition, it should be understood that Tables 1 and 2 are only examples of the implementation of the memory detection method and system U of the present invention. The actual mapped addresses of the memory 11, the number of mapped addresses, and the correspondence between the data lines and the bits Not limited to the table. In addition, in this embodiment, a memory with eight data lines is used as an example, however, the invention is not limited thereto. In other embodiments, the memory testing method and memory testing system of the present invention can also be applied to a memory having, for example, 16 data lines. In other words, the memory testing method and memory testing system of the present invention do not limit the data width of the memory 11 of the device under test 1.

With the above technical solution, the memory test method and the memory detection system U of this embodiment do not need to use costly probe fixtures and do not need to be on the motherboard as compared with the conventional electrical memory test In addition to the additional test points, it is only necessary to use a computing device to connect to the motherboard and perform the above-mentioned memory test method, thus reducing the cost of memory test and improving the test efficiency. In addition, the memory test method of the present invention can directly present the faulty data line and the fault condition (for example: open circuit or short circuit) to the maintenance personnel through the output unit 22, therefore, compared to the conventional technology memory function test method The memory testing method of the present invention does not require R&D personnel to interpret the test results, which further reduces personnel costs.

Second embodiment

The second embodiment of the present invention will be described below with reference to FIGS. 3 to 6. 3 and 4 show the memory test system U'provided by the second embodiment of the present invention, and FIG. 5 shows the method for creating an error mapping table provided by this embodiment. First, the constituent elements of this embodiment will be described with reference to FIGS. 3 and 4, and the method of creating an error map using these constituent elements will be disclosed with reference to FIG. 5.

Fig. 3 shows a functional block diagram of the memory test system U'of this embodiment. As shown in the figure, the memory test system U'of this embodiment includes a fault-free device under test 1', a test fixture 3, and an electronic device 2. The trouble-free device 1'includes a central processing unit 10' and a trouble-free memory 11'. The implementation of the electronic device 2 is the same as that of the first embodiment, and will not be repeated here. The central processing unit 10' of the non-faulty device under test 1'is the same as the central processor 10 of the device 1 under test, that is, the non-faulty device 1'has the same processing circuit as the device 1 under test. In addition, the fault-free memory 11' and the memory 11 have the same data width, and in this embodiment, the number of the fault-free memory 11' is the same as the number of the memory 11 in the first embodiment. Specifically, the device under test 1 and the device under test 1'are products of the same model manufactured by the same manufacturer, but the device under test 1'is a known good product that has been tested.

The memory detection system U'' shown in Fig. 4 is a modified embodiment of the memory detection system U'of Fig. 3. As shown in FIG. 4, each data line of the fault-free memory 11' is connected to the test point P with a trace 110. The test fixture 3 has a test probe module 30, a switch module 31, and a micro control unit 32. The test probe module 30 has at least one thimble 301, and the test probe module 30 is connected to one of the data lines of the fault-free memory 11' through the thimble 301. In this embodiment, the test probe module 30 has two thimble pins 301, each corresponding to each trouble-free memory 11'. However, the present invention is not limited to this. In other embodiments, the number of thimble pins 301 of the test probe module 30 may be equal to the total number of data lines of the fault-free memory 11 ′, and each thimble pin 301 is connected to each pin through a test point P and a trace 110 respectively. A data line.

In this embodiment, the switch module 31 is a digital or analog switch, and is connected between the test probe module 30 and the micro control unit 32. However, the present invention is not limited to this; in other embodiments, the switch module 31 may also be implemented with a single-pole multi-throw switch, for example. In this embodiment, the micro control unit 32 is a microcontroller (microcontroller). Since the microcontroller can operate independently and can complete the error mapping table creation method of this embodiment, in this modified embodiment, the memory test system U'only has a fault-free device under test 1'and a test fixture 3, Does not include the electronic device 2. In the second embodiment, the electronic device 2 is mainly used to display the test result to the operator and provide the operator with other test-related operations.

Referring to FIG. 5, the method for creating an error mapping table in this embodiment includes step S200: providing a device 1′ to be tested without failure, which includes a memory 11′ to be tested, and in step S200, to be tested without failure The device under test 1'has the same CPU 10 as the device under test 1, the fault-free memory 11' has the same data width as the memory 11, and the number of fault-free memories 11' is the same as the number of memories 11; step S202 : Provide a test fixture, which includes: a test probe module 30, a switch module 31, and a micro control unit 32, wherein the switch module 31 is connected between the test probe module 30 and the micro control unit 32; step S204 : Connect the test probe module 30 to one of the data lines of the fault-free memory 11' of the fault-to-be-tested device 1'; Step S206: Control the switch module 31 through the micro-control unit 32 to make the fault-free memory One of the data lines of the body 11', the test probe module 30 and the switch module 31 form a short circuit; Step S208: the micro control unit 32 is used to test the fault-free memory 11' within a test address interval All of the addresses are written in one full bit; and step S210: the micro control unit 32 is used to determine whether all the addresses in the test address interval correspond to the full one bit or not.

Step S206 is used to simulate the situation when one of the data lines forms a short circuit. When the data line is short-circuited, the operation of writing all 1 bits in step S208 will not be able to write a value of 1 in the address affected by the short-circuited data line, and as long as the short-circuited data line is still in In the short-circuit state, the bit value of this bit will always be 0. Therefore, when the micro control unit 32 executes step S210, the micro control unit 32 determines that the address value of the address affected by the short-circuited data line in the test address interval is not all ones. In other words, the function of step S210 is to find the mapping address described in the first embodiment, that is, the address affected when the data line is faulty.

Next, as shown in FIG. 5, the method for creating an error map in this embodiment further includes step S212: if the address value of one of the addresses in the test address interval is not all 1 bit, the micro control unit 32 creates Corresponding to the error mapping table of the device under test 1, and storing one of the address and the data line name of one of the data lines after short-circuit processing in the error mapping table, and creating the one of the address in the error mapping table , The mapping relationship between the bit value of the address value of one of the addresses that is not 1 and the name of the data line of one of the data lines that has been short-circuited.

In detail, in step S212, the micro control unit 32 recognizes the mapping address by comparing the address values and creates an error mapping table, which can be stored in the micro control unit 32 or the electronic device of FIG. 3 In 2, it is used for detection when the device under test 1 has a power-on error or other fault conditions (steps S100 to S116 in FIG. 2). Next, the micro control unit 32 stores all the addresses determined in step S210 that are not all ones (ie, mapped addresses) and the names of the data lines that have been short-circuited in the error mapping table, and establishes a mapping relationship between the two. Furthermore, in this step, the micro-control unit 32 simultaneously maps the short-circuited data lines to the bits whose address value is not 1 among the addresses that are not all ones. The steps S204 to S212 will be further described below in conjunction with Tables 3 and 4.

Table 3

Please refer to Table 3. Table 3 shows a test address interval of the fault-free memory 11'. For convenience of description, this embodiment uses the specifier corresponding to the first embodiment to describe the trouble-free memory 11' and its data line of this embodiment. For example, in step S204, the test probe module 30 is connected to the fourth data line 1D4 of the fault-free memory U2001 with a thimble 301. In step S206, the switch module 31 is controlled by the micro control unit 32, and the The fourth data line 1D4 forms a short circuit. Next, in step S208, the micro-control unit 32 writes all 1-byte bytes to all the addresses in Table 3, which is expressed as FF in hexadecimal. In step S210, the micro control unit 32 reads all the address values in the test address interval, and obtains the results shown in Table 3. Among them, the address values of some addresses are not all 1 (in Table 3, the Bold slashes indicate address values that are not all ones). For example, the address value of 0x000000211 is 7F. In Table 3, all addresses whose address values are not all 1s are the mapped addresses corresponding to the data line 1D4. The address values of the mapped addresses in Table 3 are all 7F. In binary, it is 01111111, which means that the data line 1D4 of the fault-free memory U2001 corresponds to the 7th bit of all mapped addresses in Table 3.

Table 4

Next, please refer to Table 4. In step S212, the micro control unit 32 establishes an error mapping table as shown in Table 4, and sets all the test address interval address values that are not all ones (that is, the addresses in Table 3 The address with a value of 7F) and the data line 1D4 are stored in Table 4, where the data line 1D4 is stored in the field corresponding to the 7th bit, and thus, step S212 is completed.

Please refer to FIG. 5. After the step S212, the method for creating an error mapping table further includes step S214: determining whether all the data lines of the fault-free memory 11' have been tested. The "test" here means that steps S204 to S210 are performed on the data line. If not, return to step 204, and perform steps S204 to S210 on the data lines that have not yet completed the test, until each remaining data line (1D0, 1D2, 1D3, 1D5, 1D6, 1D0, 1D2, 1D3, 1D6, 1D7) and each data line (2D0 to 2D7) of the fault-free memory 11' with the part name U2002 is completed until the test, and the error mapping table of the device under test 1 in the form shown in Table 5 is completed. For convenience of description, only a part of the mapped addresses are listed in Table 5 as an illustration. It should be understood that the actual mapped addresses, the number of actual mapped addresses, and the correspondence between the data lines and the bit numbers depend on the device under test and the memory of the device under test in actual application, not in the table As shown.

Table 5

It is worth mentioning that in another embodiment of the present invention, the number of thimble pins 301 of the test probe module 30 may be the same as the number of data lines, and each thimble pin 301 is connected to each data line through the test point P, and The switch module 31 is implemented using digital or analog switches. In this embodiment, steps S200 to S214 can be completed individually by the micro control unit 32 in a fully automatic manner, further improving the test efficiency.

In addition, in other embodiments of the present invention, after step S210, the short-circuited data line, the address affected by the short-circuit data line and whose address value is not all 1 and its bit value other than 1 can be recorded in other ways. The mapping relationship between bits is not limited to the establishment of an error mapping table. For example, the mapping relationship between the data line and the bit can be established by establishing a tag.

Please refer to FIG. 6. Further, the memory detection method according to another modified embodiment of the present invention may further include the method for selecting the test address interval described above. The method for selecting the test address interval includes step S300: the micro-control unit 32 starts the fault-free device under test 1': step S302: the micro-control unit 32 reads the one-bit content value table of the fault-free memory; and step S304: The micro control unit 32 selects a one-bit address section of the non-faulty memory as the test address section according to the address content value table, wherein the content value of all addresses in the address section is 0.

In detail, in this modified embodiment, after confirming that the trouble-free device 1'is turned on, the one-bit address interval with the content value of the zero-fault memory 11' as 0 is selected as the test address interval. In this way, it is possible to avoid erasing the boot data in the memory 11 and affecting the operation of the memory 11 when executing the memory test method in FIG. 2.

In summary, by the above technical means, the memory detection method, the error mapping table creation method and the memory detection system provided by the present invention are achieved by "reading the error mapping table corresponding to the device under test through the control unit", " The control unit writes a check byte to each mapped address read", and "uses the control unit to determine the bit value of each bit of each address value corresponding to the check byte Whether the bit value of the bit is the same” to achieve “if the bit value of at least one bit in the address value is different from the bit value of the corresponding bit in the check bit group, the control unit The error mapping table determines that the data line mapped to the at least one bit is defective."

In this way, the memory detection method, the error mapping table creation method and the memory detection system of the present invention can save the costly probe fixture compared to the prior art memory electrical test method, and do not need to be on the motherboard Another test point. It only needs to use the computing device to connect to the motherboard and execute the memory testing method of the present invention through the control unit of the computing device, thereby reducing the cost of memory testing and improving the testing efficiency. In addition, the memory test method of the present invention can directly present the faulty data line and the fault situation to the maintenance personnel through the output unit 22. Therefore, compared with the memory function test method of the conventional technology, the memory test of the present invention The method does not require professionals to interpret the boot program, which further reduces personnel costs.

The content disclosed above is only a preferred and feasible embodiment of the present invention, and therefore does not limit the scope of the patent application of the present invention, so any technical changes made by using the description and drawings of the present invention fall into the application of the present invention. Within the scope of the patent.

U, U’, U’’‧‧‧ memory test system 1‧‧‧ device under test 10, 10’‧‧‧ CPU 11‧‧‧Memory 2‧‧‧Electronic device 20‧‧‧Input unit 21‧‧‧Control unit 22‧‧‧Output unit 1’‧‧‧Fault-free device under test 11’‧‧‧Fault free memory 111‧‧‧Trace P‧‧‧Test point 3‧‧‧Test fixture 30‧‧‧Test probe module 301‧‧‧Thimble 31‧‧‧Switch module 32‧‧‧Micro Control Unit

FIG. 1 is a functional block diagram of a memory detection method according to a first embodiment of the invention. 2 is a flowchart of a memory detection system according to a first embodiment of the invention. 3 is a functional block diagram of a memory detection system according to a second embodiment of the invention. 4 is a schematic diagram of a memory detection system according to a second embodiment of the invention. 5 is a flowchart of a memory detection method according to a second embodiment of the invention. 6 is a flowchart of a modified embodiment of the memory detection method according to the second embodiment of the present invention.

The designated representative diagram of the present invention is a flowchart, so there is no symbol for a simple description.

Claims (15)

A memory detection method for detecting a memory of a device under test, wherein the memory detection method includes: reading an error mapping table corresponding to the device under test, wherein the error mapping table includes a set of mappings Address data and a set of data line data, the set of mapped address data includes a plurality of mapped addresses of the memory, the set of data line data includes a plurality of data line names of the plurality of data lines of the memory, each The name of the data line is mapped to each bit of each mapping address in the error mapping table; a check byte is written to each mapping address; reading each mapping address corresponds to Check the bit value of the byte; determine whether the bit value of each bit of each address value is the same as the bit value of the corresponding bit in the check byte; and if judge at least one The mapped address determines that the memory is defective because the bit value of at least one bit of the address value of the check byte group is different from the bit value of the corresponding bit in the check byte group. The memory detection method according to claim 1, wherein the check byte is all 1 byte, and if it is judged that at least one mapped address should check at least one bit of the address value of the byte The bit value of is different from the bit value of the corresponding bit in the check bit group, and the step of determining that the memory is a failure further includes: the control unit determines to map to the at least one according to the error mapping table At least one of the data lines of one bit is short-circuited. The memory detection method according to claim 1, wherein the check byte is all 0 bytes, and if it is determined that at least one mapped address should check at least one bit of the address value of the byte The bit value of is different from the bit value of the corresponding bit in the check bit group, and the step of determining that the memory is a failure further includes: the control unit determines to map to the at least one according to the error mapping table At least one of the data lines of one bit is open. The memory detection method according to claim 1, wherein the step of reading the error mapping table corresponding to the device under test further comprises: receiving information about a device under test through an input unit to enable the control The unit reads the error mapping table corresponding to the device under test according to the information of the device under test. The memory detection method according to claim 1, wherein before the step of reading the error mapping table corresponding to the device under test, the method further comprises: providing a test fixture, the test fixture including a test probe module Group, a switch module and a micro-control unit, wherein the switch module is connected between the test probe module and the micro-control unit; the test probe module is connected to a fault-free device under test One of the data lines of a fault-free memory; the switch module is controlled by the micro-control unit so that one of the data lines of the fault-free memory, the test probe module and the switch module A short circuit is formed between them; the micro-control unit writes a full 1-byte address to all addresses in a test address section of the fault-free memory; and the micro-control unit determines the test address section All the addresses within should be based on whether the address value of all 1-byte is all 1-byte. The memory detection method according to claim 5, wherein the micro-control unit is used to determine whether all the addresses in the test address interval should correspond to all 1-byte address values The step further includes: if the address value of one of the addresses in the test address interval is not all 1 byte, the micro control unit establishes the error mapping table corresponding to the device under test, and Store one of the addresses and the data line name of the one of the short-circuited data lines in the error mapping table, and create the one of the address and the one of the bits in the error mapping table The mapping relationship between the bit value of the address that is not 1 and the name of the data line of one of the data lines that have been short-circuited. The memory detection method according to claim 5, wherein in the step of writing all the 1-bytes in the test address section of the non-faulty memory through the micro control unit, The method further includes: starting the fault-free device under test with the micro-control unit; reading the one-bit content value table of the non-faulty memory with the micro-control unit; and using the micro control unit according to the address content value table The one-bit address interval of the memory is selected as the test address interval, wherein the content value of all addresses in the address interval is 0. The memory detection method according to claim 5, wherein the non-faulty device under test and the device under test each have a processing circuit, and the processing circuit of the non-faulty device under test and the processing of the device under test The circuits have the same circuit structure, and the fault-free memory and the memory have the same data width. A method for creating an error mapping table is used to detect a memory of a device under test. The method for establishing an error mapping table includes: providing a test fixture, the test fixture including a test probe module, a switch module and A micro-control unit, wherein the switch module is connected between the test probe module and the micro-control unit; the test probe module is connected to a fault-free memory of a fault-free device under test One of the data lines; the switch module is controlled by the micro control unit so that one of the data lines of the fault-free memory, the test probe module and the switch module forms a short circuit; by the micro The control unit writes an entire 1-byte address to all addresses in a test address section of the fault-free memory; the micro-control unit determines whether all addresses in the test address section should be Whether the address value of 1 byte is all 1 byte; and if the address value of one of the addresses in the test address interval is not all 1 byte, the micro control unit establishes the corresponding value An error mapping table of the device under test, storing the one of the addresses, the address value of the one of the addresses, and the data line name of the one of the short-circuited data lines in the error mapping table, and A mapping relationship between the one of the addresses, the address value of the one of the addresses, and the data line name of the one of the short-circuited data lines is established in the error mapping table. A memory detection system includes: a device to be tested, the unit to be tested includes a memory; and an electronic device, the electronic device includes a control unit, the device to be tested is connected to the electronic device, wherein the electronic device An error mapping table corresponding to the device under test is stored. The error mapping table includes: a set of mapped address data, the set of mapped address data includes a plurality of mapped addresses of the memory; and a set of data line data, The set of data line data includes the names of a plurality of data lines of the memory, wherein each data line name is mapped to each bit of each mapping address in the error mapping table, and the control unit Used to read the error mapping table and write a check byte to the plurality of mapping addresses of the memory according to the set of mapping address data of the error mapping table, and determine each of the mapping addresses It should be checked whether the bit value of each bit of the bit address value of the byte is the same as the bit value of the corresponding bit in the check byte, where, if at least one bit in the address value The bit value of the bit is different from the bit value of the corresponding bit in the check bit group, and the control unit determines that at least one of the data lines mapped to the at least one bit is faulty according to the error mapping table. The memory detection system according to claim 10, wherein the electronic device further includes an output unit through which the control unit displays a fault state of at least one of the data lines corresponding to the at least one bit. The memory detection system according to claim 10, wherein the electronic device further comprises a receiving unit for receiving information of a device under test, so that the control unit reads information corresponding to the device according to the information of the device under test The error mapping table of the test device. The memory detection system according to claim 10, further comprising: a fault-free device under test, the fault-free device under test includes a fault-free memory; and a test fixture, the test fixture includes: a test Probe module; a switch module; and a micro control unit, wherein the switch module is connected between the test probe module and the micro control unit, and the test probe module is connected to the fault-free One of the data lines of the memory, wherein the micro-control unit is used to control the switch unit so that one of the data lines of the fault-free memory, the test probe module and the switch module are formed Short circuit, in which the micro control unit writes all 1-bytes to all addresses in a test address interval of the fault-free memory, and judges that all addresses in the test address interval should be Whether the address value of 1 byte is all 1 byte. The memory detection system according to claim 13, wherein the micro-control unit is further used to establish if the address value of one of the addresses in the test address interval is not all 1 byte Corresponding to the error mapping table of the device under test, storing one of the address and the data line name of the one of the short-circuited data lines in the error mapping table, and creating the error mapping table The mapping relationship between one of the addresses, the bits of which the address value of the one of the addresses is not 1, and the name of the data line of the one of the short-circuited data lines. The memory detection system according to claim 13, wherein the non-faulty device under test and the device under test each have a processing circuit, and the processing circuit of the non-faulty device under test and the processing of the device under test The circuits have the same circuit structure, and the fault-free memory and the memory have the same data width.

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