CN116994633A - Easy-maintenance and regeneration design system, method and equipment for memory bank - Google Patents

Easy-maintenance and regeneration design system, method and equipment for memory bank Download PDF

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Publication number
CN116994633A
CN116994633A CN202311096677.5A CN202311096677A CN116994633A CN 116994633 A CN116994633 A CN 116994633A CN 202311096677 A CN202311096677 A CN 202311096677A CN 116994633 A CN116994633 A CN 116994633A
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China
Prior art keywords
memory
control mechanism
memory bank
strip
easy
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CN202311096677.5A
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Chinese (zh)
Inventor
王择珑
吴伟波
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Shenzhen Juhor Precision Technology Co ltd
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Shenzhen Juhor Precision Technology Co ltd
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Priority to CN202311096677.5A priority Critical patent/CN116994633A/en
Publication of CN116994633A publication Critical patent/CN116994633A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The application discloses a design system, a method and equipment for easy maintenance and regeneration of a memory bank, wherein the system comprises the memory bank, a control mechanism and a plurality of memory chips, wherein a base plate of the memory bank is provided with pin holes for detachably inserting pins of the memory chips corresponding to the memory chips, the hole wall of each pin hole is provided with a conductive metal layer, and when pins of the memory chips are inserted into the pin holes, the memory chips are electrically connected with the conductive metal layers; the control mechanism is connected with the memory strip and the memory chips, and when detecting that at least one memory chip on the memory strip fails, the control mechanism automatically shields the corresponding memory chip with the failure and enables the memory strip to be used normally. The intelligent shielding design for the memory chips is added, so that when a certain memory chip of the memory strip is detected to have faults, the system automatically shields the memory chip, and the normal use of the whole memory strip is not influenced; therefore, the application provides the effect of the memory bank which is convenient to maintain.

Description

Easy-maintenance and regeneration design system, method and equipment for memory bank
Technical Field
The application relates to the technical field of memory banks, in particular to a system, a method and equipment for designing easy maintenance and recycling of memory banks.
Background
The memory bar is a computer component in which a CPU can address and perform read-write operation through a bus. With the continuous updating demands of computer software and hardware technology, the memory bank becomes the whole of the read-write memory.
In the related art, a plurality of memory chips are welded on the memory strips, and the memory strips with larger capacity have more memory chips; if a certain memory chip on the memory bar fails, the whole memory bar is damaged and cannot be used continuously, so that the loss is large for users.
The memory bar damage of the welding fixation can be maintained, but the memory bar is to be repaired, and a professional maintenance master uses a professional tool to maintain and replace the memory bar, so that the maintenance period is longer, and the maintenance cost is higher; therefore, there is a defect that it is inconvenient to repair the memory bank, and there is room for improvement.
Disclosure of Invention
In order to provide a memory bank convenient to maintain, the application provides a design system, a method and equipment for easily maintaining and recycling the memory bank.
The first technical scheme adopted by the application is as follows:
the easy-to-repair and recycling design system of the memory bank comprises the memory bank, a control mechanism and a plurality of memory chips, wherein a base plate of the memory bank is provided with pin holes for detachably inserting pins of the memory chips corresponding to the memory chips, the hole wall of each pin hole is provided with a conductive metal layer, and when pins of the memory chips are inserted into the pin holes, the memory chips are electrically connected with the conductive metal layers;
the control mechanism is connected with the memory strips and the memory chips, and when detecting that at least one memory chip on the memory strips fails, the control mechanism automatically shields the corresponding memory chip with the failure and enables the memory strips to be normally used.
By adopting the technical scheme, the fixing mode of the memory chip on the memory strip is changed from a welding mode to a pin plugging mode, so that a user can automatically replace the memory chip; the abandoned memory strips are regenerated and utilized to the greatest extent, a recovery mechanism or a user can replace the damaged memory chips by himself, and the whole memory strips can be used continuously; in the internal driving program design of the memory strip, an intelligent shielding design of the memory chip is added, so that when a certain memory chip of the memory strip is detected to be faulty, the memory chip is automatically shielded by the design system which is easy to maintain and recycle, and the normal use of the whole memory strip is not influenced; therefore, the application provides the memory strip which is convenient to maintain.
The present application is in a preferred example: the control mechanism comprises an information output module and at least one microcontroller; the control mechanism is connected with a memory strip electric connection test module, and the memory strip electric connection test module comprises at least one constant voltage source, a plurality of voltage dividing resistors, a plurality of analog multiplexers and at least one analog-to-digital converter;
the voltage dividing resistors and the analog multiplexers are arranged in a one-to-one correspondence manner, one end of each voltage dividing resistor is electrically connected with one constant voltage source, and the other end of each voltage dividing resistor is electrically connected with a pin of a golden finger in the memory bank; the output end of the voltage dividing resistor is also electrically connected with the analog multiplexer;
the input end of the analog-to-digital converter is electrically connected with the output end of the analog multiplexer; the output end of the analog-to-digital converter is electrically connected with the input end of the microcontroller;
and the output end of the microcontroller is electrically connected with the information output module.
By adopting the technical scheme, the memory bank electrical connection testing module is a device for automatically diagnosing electrical connection of a memory bank circuit, a constant voltage source applies voltage to each pin of the memory bank circuit to be tested through a voltage dividing resistor, and when electrical abnormality such as open circuit, short circuit, cold joint and the like occurs in the electrical of the circuit to be tested, the voltage dividing voltage in each channel of the analog multiplexer is different due to different impedance; the microcontroller displays the measured voltage values in all channels to a tester through the information output module; the tester compares the actual voltage value with the normal voltage value to determine whether the voltage abnormality occurs in the pin of a golden finger in the memory bank beside the actual voltage value and the normal voltage value, so that the measurement is more accurate and rapid.
The present application is in a preferred example: the control mechanism comprises a voltage value reading module for reading the voltage value of each channel of the plurality of analog multiplexers;
the microcontroller correspondingly matches a voltage normal threshold value based on each channel of the plurality of analog multiplexers;
and the microcontroller compares the voltage values of the channels of the analog multiplexers with the corresponding normal voltage thresholds and outputs the comparison result through the information output module.
By adopting the technical scheme, the microcontroller controls the analog multiplexer to switch each channel, and the voltage signals of each channel are collected through the analog-to-digital converter and sent to the microcontroller; the microcontroller compares the voltages in each channel of the analog multiplexer with the corresponding normal threshold values, and displays the comparison results to a user through the information output module, so that the automatic diagnosis of the electrical abnormality of the golden finger pins on the memory bank circuit is realized, the measurement is quick and accurate, the labor and material resources are saved, and the memory bank is convenient to maintain.
The present application is in a preferred example: the conductive metal layer comprises a soft metal layer, and the soft metal layer is coated and arranged at intervals along the hole wall of the pin hole.
By adopting the technical scheme, the soft metal layer has elasticity, which is beneficial to improving the contact area of the pins of the memory strip, the pins of the memory chip and the conductive metal layer and improving the electrical connection performance of the memory strip and the memory chip.
The present application is in a preferred example: the conductive metal layers comprise elastic metal rings, a plurality of pairs of elastic metal rings are arranged corresponding to each stitch hole, the elastic metal layers of the plurality of pairs are vertically arranged at intervals along the hole walls of the stitch holes, and the elastic metal rings of the same pair are positioned on the hole walls of the two opposite sides of the stitch holes.
By adopting the technical scheme, the elastic metal layer has elasticity, and the contact areas of the pins of the memory strip, the pins of the memory chip and the conductive metal layer are improved by a plurality of pairs of elastic metal rings, so that the electric connection performance of the memory strip and the memory chip is enhanced.
The present application is in a preferred example: the system also comprises a plurality of DIMM slots provided with status indicator lamps; the control mechanism comprises a programmable logic device and a register; the status indicator lamp is connected with the programmable logic controller; the programmable logic controller is connected with a system south bridge PCH through the register;
the programmable logic device decodes the signals of the registers to the corresponding DIMM slot states and controls the display states of the status indicators of the corresponding DIMM slots.
By adopting the technical proposal, the utility model has the advantages that,
the present application is in a preferred example: the control mechanism also comprises a memory controller; the control mechanism automatically processes the fault memory bank according to the following steps:
the control mechanism starts a BIOS and initializes the register; the control mechanism initializes the SMI and the memory controller;
storing the current state of the register into a storage area, and paying attention to detecting whether the memory bank in each DIMM slot is in place or not; if the memory bar of the DIMM slot is in place, a state indicator lamp corresponding to the DIMM slot is lightened; registering a periodic SIM program, and initializing a memory bank of the DIMM slot; if the memory bar of the DIMM slot is not in place, the state indicator lamp corresponding to the DIMM slot is not lightened;
if the memory initialization in the DIMM slot is normal, the programmable logic device controls the state indicator lamp corresponding to the DIMM slot to be in a lighting state, clears the register state data stored in the storage area, and unloads the SMI program of periodic memory processing;
if the memory initialization is not completed when the periodic time interval of the SMI program arrives, the memory bank initialization is considered to have a fault, the periodic SMI interrupt is triggered, the SMI program of periodic memory processing is executed, the memory of the fault DIMM slot is forbidden, the next DIMM slot is pointed, the data of the register state in the memory area is read, the SMI program is exited, and all register values are restored to the values of the registers read by the memory area;
a check is made for memory in the next DIMM socket.
By adopting the technical scheme, aiming at the condition that the memory bank cannot be initialized and completed, and the downtime of a computer system is caused, the initialized memory bank is controlled, the problems of memory bank faults, unsupported memory bank types and the like are found, a software program inhibits the failed memory bank, meanwhile, a status indicator lamp is arranged to indicate that the corresponding DIMM memory bank fails, and a control mechanism initializes the next memory bank until all the memory banks are initialized and the computer system is started; therefore, the computer system cannot be down due to the existence of the fault memory bank, normal use of the computer system is not affected, the fault memory bank is marked through the status indicator lamp, a user can conveniently check the fault memory bank and replace the fault memory bank, technical difficulty in checking the main board errors is greatly reduced, and the computer system is simple and convenient.
The second object of the application is realized by the following technical scheme:
the design method for easy maintenance and recycling of the memory bank is applied to the design system for easy maintenance and recycling of the memory bank, and comprises the following steps: the method comprises the steps of testing and acquiring the use state of each storage chip on the memory strip, wherein the use state comprises a normal use state and a fault state;
when detecting that at least one memory chip on the memory bar fails, automatically shielding the corresponding memory chip with failure and enabling the memory bar to be used normally.
By adopting the technical proposal, the utility model has the advantages that,
the third object of the application is realized by the following technical scheme:
a computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the method for designing easy repair and recycling of a memory bank as described above when executing the computer program.
The fourth object of the application is realized by the following technical scheme:
a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the above-described easy-repair recycling design method for a memory bank.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the fixing mode of the memory chip on the memory strip is changed from a welding mode to a pin plugging mode, so that a user can automatically replace the memory chip; the abandoned memory strips are regenerated and utilized to the greatest extent, a recovery mechanism or a user can replace the damaged memory chips by himself, and the whole memory strips can be used continuously; in the internal driving program design of the memory strip, an intelligent shielding design of the memory chip is added, so that when a certain memory chip of the memory strip is detected to be faulty, the memory chip is automatically shielded by the design system which is easy to maintain and recycle, and the normal use of the whole memory strip is not influenced; therefore, the application provides a memory strip convenient to maintain;
2. the microcontroller controls the analog multiplexer to switch each channel, and the voltage signals of each channel are collected through the analog-to-digital converter and sent to the microcontroller; the microcontroller compares the voltages in each channel of the analog multiplexer with the corresponding normal threshold values, and displays the comparison results to a user through the information output module, so that the automatic diagnosis of the electrical abnormality of the golden finger pins on the memory bank circuit is realized, the measurement is quick and accurate, the labor and material resources are saved, and the memory bank is convenient to maintain;
3. aiming at the condition that the memory bank cannot be initialized and completed, and the computer system is down, the initialized memory bank is controlled, the problems that the memory bank has a fault, the type of the memory bank is not supported and the like are found, a software program prohibits the faulty memory bank, meanwhile, a status indicator lamp is set to indicate that the corresponding DIMM memory bank has a fault, and a control mechanism initializes the next memory bank until all the memory banks are initialized and the computer system is started; therefore, the computer system cannot be down due to the existence of the fault memory bank, normal use of the computer system is not affected, the fault memory bank is marked through the status indicator lamp, a user can conveniently check the fault memory bank and replace the fault memory bank, technical difficulty in checking the main board errors is greatly reduced, and the computer system is simple and convenient.
Drawings
FIG. 1 is a schematic diagram of a memory bank and a memory chip mounting structure in an easy-to-repair recycling design system for memory banks according to an embodiment of the present application;
FIG. 2 is a schematic diagram showing the connection between a memory bank and a memory bank electrical connection test module in an easy-to-repair recycling design system for memory banks according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating the connection of a memory bank and a control mechanism in an easy-to-repair recycling design system for memory banks according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a connection between a control mechanism and DIMM slots in an easy-to-repair recycling design system for memory banks in accordance with one embodiment of the present application;
fig. 5 is a schematic diagram of an apparatus in an embodiment of the application.
Reference numerals illustrate:
1. a memory bank; 11. stitch holes; 12. a conductive metal layer; 2. and a memory chip.
Detailed Description
The present application will be described in further detail with reference to the accompanying drawings.
In an embodiment, as shown in fig. 1, the application discloses an easy-to-repair recycling design system of a memory bank 1, the easy-to-repair recycling design system of the memory bank 1 comprises the memory bank 1, a control mechanism and a plurality of memory chips 2, wherein a substrate of the memory bank 1 is provided with pin holes 11 corresponding to the memory chips 2 for detachably inserting pins of the memory chips 2, the hole wall of each pin hole 11 is provided with a conductive metal layer 12, and when pins of the memory chips are inserted into the pin holes 11, the memory chips 2 are electrically connected with the conductive metal layers 12; the control mechanism is connected with the memory strip 1 and the plurality of memory chips 2, and when detecting that at least one memory chip 2 on the memory strip 1 fails, the control mechanism automatically shields the corresponding memory chip 2 with the failure and enables the memory strip 1 to be used normally; according to the application, the fixing mode of the memory chip 2 on the memory strip 1 is changed from a welding mode to a pin plugging mode, and when the memory chip 2 is damaged, a user can automatically replace the memory chip 2; the abandoned memory bank 1 is regenerated and utilized to the greatest extent, and the whole memory bank 1 can be used continuously; in the circulation and sales link, the capacity of the memory bank 1 can be adjusted according to the demands of users.
Fig. 1 is a schematic diagram showing a structure in which pins of a memory chip 2 are plugged into a circuit board of a memory bank 1; in actual use, the conductive metal layer 12 is a soft metal layer, and the soft metal layer is coated and arranged at intervals along the hole wall of the pin hole 11; or arranging the conductive metal layers 12 into elastic metal rings, wherein the elastic metal rings are provided with a plurality of pairs corresponding to each stitch hole 11, the plurality of pairs of elastic metal layers are vertically arranged at intervals along the hole walls of the stitch holes 11, and the elastic metal rings of the same pair are positioned on the hole walls of the two opposite sides of the stitch holes 11; the soft metal layer and the elastic metal ring are elastic, which is beneficial to improving the contact area of the pins of the memory strip 1, the pins of the memory chip 2 and the conductive metal layer 12 and improving the electrical connection performance of the memory strip 1 and the memory chip 2.
As shown in fig. 2, the control mechanism includes an information output module and at least one Microcontroller (MCU); the microcontroller is STM32F103C8T6, and the information output module is a display screen of a mobile phone end, an IPAD, a computer end and the like; the control mechanism is connected with a memory strip electric connection test module, and the memory strip electric connection test module comprises at least one constant voltage source, a plurality of voltage dividing resistors, a plurality of analog multiplexers and at least one analog-to-digital converter (ADC); the voltage dividing resistors and the analog multiplexers are arranged in a one-to-one correspondence manner, one end of each voltage dividing resistor is electrically connected with one constant voltage source, and the other end of each voltage dividing resistor is electrically connected with a pin of one golden finger in the memory strip 1; the output end of the divider resistor is also electrically connected with an analog multiplexer; the input end of the analog-to-digital converter is electrically connected with the output end of the analog multiplexer; the output end of the analog-to-digital converter is electrically connected with the input end of the microcontroller; the output end of the microcontroller is electrically connected with the information output module.
Taking DDR type memory strip 1 as an example, the voltage based on a constant voltage source is low, and the semiconductor devices on the memory strip 1 are not damaged when voltage is applied to each pin of the circuit of the memory strip 1 to be tested through a voltage dividing resistor array; and the electrical anomalies of the circuit to be tested such as open circuit, short circuit, cold joint and the like can react to the difference of the divided voltage of the corresponding channels due to the difference of the impedance.
In one embodiment, as shown in fig. 3, for DDR type memory banks, the constant voltage source may use an LDO power chip, the model of which is LT3080EMS8e#pbf; the low-voltage power supply has the characteristics of low ripple and low output voltage of 0V, and meets the requirement that the voltage is low enough to not damage semiconductor devices on a computer main board and a memory strip.
The analog multiplexer can select an SN74LV4051APWR chip, which is an 8-to-1 analog multiplexer, and is switched by 3 channel selection pins and 1 enable pin control channels, namely 4 digital signals are needed for each SN74LV4051APWR chip to control gating.
As shown in fig. 3, the DDR memory chip has 288 gold finger pins, and when all pins are measured, 288 channels need 36 SN74LV4051APWR, so 36×4=144 digital signals are needed to control switching, and since the number of these digital signals exceeds the maximum IO number of the MCU controller, the serial-parallel converter needs to perform IO expansion to control. The serial-to-parallel converter is of the model SN74HC595PWR, also called a shift register, and a plurality of shift registers can be used in series to achieve the purpose of expanding a large number of pins by a small number of pins.
The control mechanism includes a voltage value reading module (not shown) for reading the voltage value of each channel of the plurality of analog multiplexers; the voltage value reading module is a measuring instrument for measuring the voltage value; the microcontroller correspondingly matches a voltage normal threshold value based on each channel of the plurality of analog multiplexers; the microcontroller compares the voltage values of the channels of the analog multiplexers with corresponding voltage normal thresholds and outputs comparison results through the information output module.
The microcontroller displays the measured voltage values in all channels to a tester through the information output module; the tester compares whether the voltage abnormality occurs on the pin of a golden finger in the memory bank beside the actual voltage value and the normal voltage value, so that the measurement is more accurate and rapid; the microcontroller compares the voltage in each channel of the analog multiplexer with the corresponding normal threshold value, and displays the comparison result of the voltage value to a user through the information output module, so that the automatic diagnosis of the electrical abnormality of the golden finger pin on the memory bank circuit is realized.
In one embodiment, as shown in fig. 4, in this embodiment, a host circuit board with DIMM slots is taken as an example, and a computer motherboard is provided with multiple DIMM slots, where one DIMM slot is used for plugging a memory bank; DIMM slots typically use DDR SDRAM memory banks, including DDR1, DDR2, DDR3, DDR4, etc. types of memory banks; different DIMM socket types and memory bank types supported by the motherboard are distinguished, and the corresponding memory banks need to be selected according to specific hardware configurations.
A control mechanism in a memory bank easy-to-repair recycling design system includes: comprises a plurality of DIMM slots provided with status indicator lamps; the status indicator lamp is an LED lamp; the control mechanism comprises a programmable logic device (CPLD) and a register (GPIO); the status indicator lamp is connected with the programmable logic controller; the programmable logic controller is connected with a system south bridge PCH through a register; the programmable logic device decodes the signals of the register to the corresponding DIMM slot states and controls the display states of the state indicator lamps of the corresponding DIMM slots; namely, a system south bridge PCH is connected with a register through a programmable logic device; in the starting process of the computer system, the programmable logic device decodes GPIO signals of the register to the corresponding DIMM slot state and controls the state of the indicator lamp of the corresponding DIMM slot, so that when the problems of memory bank faults, unsupported memory bank types and the like are found, the control mechanism prohibits the faulty memory bank, and the corresponding faulty DIMM memory bank is indicated through the set indicator lamp.
Specifically, the control mechanism is connected with an operation and maintenance management system in which an SMI (simple network management protocol) program is provided. The control mechanism also comprises a memory controller; the control mechanism automatically processes the fault memory bank according to the following steps:
s1: the control mechanism starts the BIOS to initialize the register; the control mechanism initializes the SMI and the memory controller;
s2: storing the current state of the register into a storage area, and paying attention to detecting whether the memory bank in each DIMM slot is in place or not; if the memory bar of the DIMM slot is in place, a state indicator lamp corresponding to the DIMM slot is lightened; registering a periodic SIM program, and initializing a memory bank of the DIMM slot; if the memory bar of the DIMM slot is not in place, the state indicator lamp corresponding to the DIMM slot is not lightened;
s3: if the memory initialization in the DIMM slot is normal, the programmable logic device controls the state indicator lamp corresponding to the DIMM slot to be in a lighting state, clears the register state data stored in the storage area, and unloads the SMI program of periodic memory processing;
s4, if the memory initialization is not completed when the periodic time interval of the SMI program arrives, the memory bank initialization is considered to have a fault, the periodic SMI interrupt is triggered, the operation and maintenance management system is entered, the SMI program of periodic memory processing is executed, and the memory of the fault DIMM slot is forbidden; distinguishing a plurality of DIMM slots by a number n, wherein n is greater than 1; the number n of the DIMM slot is increased by 1, the next DIMM slot is pointed, the data of the register state in the storage area is read, the SMI program is exited, and all register values are restored to the register values read out by the storage area.
Aiming at the condition that the memory bank cannot be initialized and completed, and the computer system is down, the initialized memory bank is controlled, the problems that the memory bank has a fault, the type of the memory bank is not supported and the like are found, a software program prohibits the faulty memory bank, meanwhile, a status indicator lamp is set to indicate that the corresponding DIMM memory bank has a fault, and a control mechanism initializes the next memory bank until all the memory banks are initialized and the computer system is started; therefore, the computer system cannot be down due to the existence of the fault memory bank, normal use of the computer system is not affected, the fault memory bank is marked through the status indicator lamp, a user can conveniently check the fault memory bank and replace the fault memory bank, technical difficulty in checking the main board errors is greatly reduced, and the computer system is simple and convenient.
In an embodiment, an easy-to-repair recycling design method of a memory bank is provided, which is applied to an easy-to-repair recycling design system of a memory bank as described above.
The easy-to-repair and regeneration design method for the memory bank comprises the following steps:
s100: the method comprises the steps of testing and acquiring the use state of each memory chip on a memory strip, wherein the use state comprises a normal use state and a fault state;
s200: when detecting that at least one memory chip on the memory strip fails, automatically shielding the corresponding memory chip with the failure and enabling the memory strip to be used normally.
Specifically, the fixing mode of the memory chip on the memory strip is changed from a welding mode to a pin plugging mode, so that a user can replace the memory chip automatically; the abandoned memory strips are regenerated and utilized to the greatest extent, a recovery mechanism or a user can replace the damaged memory chips by himself, and the whole memory strips can be used continuously; in the internal driving program design of the memory strip, an intelligent shielding design of the memory chip is added, so that when a certain memory chip of the memory strip is detected to be faulty, the memory chip is automatically shielded by the design system which is easy to maintain and recycle, and the normal use of the whole memory strip is not influenced; therefore, the application provides the memory strip which is convenient to maintain.
It should be understood that the sequence number of each step in the above embodiment does not mean the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not be construed as limiting the implementation process of the embodiment of the present application.
In one embodiment, a computer device is provided, which may be a server, the internal structure of which may be as shown in fig. 5. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is used for storing the storage data of the memory and the memory bank. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by the processor, implements a method for designing easy repair and reuse of the memory bank.
In one embodiment, a computer device is provided comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the following steps when executing the computer program:
s100: the method comprises the steps of testing and acquiring the use state of each memory chip on a memory strip, wherein the use state comprises a normal use state and a fault state;
s200: when detecting that at least one memory chip on the memory strip fails, automatically shielding the corresponding memory chip with the failure and enabling the memory strip to be used normally.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of:
s100: the method comprises the steps of testing and acquiring the use state of each memory chip on a memory strip, wherein the use state comprises a normal use state and a fault state;
s200: when detecting that at least one memory chip on the memory strip fails, automatically shielding the corresponding memory chip with the failure and enabling the memory strip to be used normally.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that; the technical scheme described in the foregoing embodiments can be modified or some of the features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (10)

1. The design system is characterized by comprising a memory bar (1), a control mechanism and a plurality of memory chips (2), wherein a substrate of the memory bar (1) is provided with pin holes (11) for detachably inserting pins of the memory chips (2) corresponding to the memory chips (2), the hole wall of each pin hole (11) is provided with a conductive metal layer (12), and when the pins of the memory chips (2) are inserted into the pin holes (11), the memory chips (2) are electrically connected with the conductive metal layers (12);
the control mechanism is connected with the memory strips (1) and the memory chips (2), and when detecting that at least one memory chip (2) on the memory strips (1) fails, the control mechanism automatically shields the corresponding memory chip (2) which fails and enables the memory strips (1) to be normally used.
2. The easy-repair recycling design system of memory bank according to claim 1, wherein said control mechanism comprises an information output module and at least one microcontroller; the control mechanism is connected with a memory strip electric connection test module, and the memory strip electric connection test module comprises at least one constant voltage source, a plurality of voltage dividing resistors, a plurality of analog multiplexers and at least one analog-to-digital converter;
the voltage dividing resistors and the analog multiplexers are arranged in a one-to-one correspondence manner, one end of each voltage dividing resistor is electrically connected with one constant voltage source, and the other end of each voltage dividing resistor is electrically connected with a pin of a golden finger in the memory strip (1); the output end of the voltage dividing resistor is also electrically connected with the analog multiplexer;
the input end of the analog-to-digital converter is electrically connected with the output end of the analog multiplexer; the output end of the analog-to-digital converter is electrically connected with the input end of the microcontroller;
and the output end of the microcontroller is electrically connected with the information output module.
3. The easy-repair recycling design system of memory bank according to claim 2, wherein said control mechanism comprises a voltage value reading module for reading a voltage value of each channel of the plurality of analog multiplexers;
the microcontroller correspondingly matches a voltage normal threshold value based on each channel of the plurality of analog multiplexers;
and the microcontroller compares the voltage values of the channels of the analog multiplexers with the corresponding normal voltage thresholds and outputs the comparison result through the information output module.
4. The system according to claim 1, wherein the conductive metal layer (12) comprises a soft metal layer, and the soft metal layer is coated and arranged along the hole wall of the pin hole (11) at intervals.
5. The easy-to-repair recycling design system of the memory bank according to claim 1, wherein the conductive metal layer (12) comprises an elastic metal ring, a plurality of pairs of elastic metal rings are arranged corresponding to each pin hole (11), the plurality of pairs of elastic metal layers are vertically arranged at intervals along the hole walls of the pin holes (11), and the elastic metal rings of the same pair are positioned on the hole walls of the two opposite sides of the pin holes (11).
6. The easy repair recycling design system for memory sticks of claim 1, further comprising a plurality of DIMM sockets provided with status indicators; the control mechanism comprises a programmable logic device and a register; the status indicator lamp is connected with the programmable logic controller; the programmable logic controller is connected with a system south bridge PCH through the register;
the programmable logic device decodes the signals of the registers to the corresponding DIMM slot states and controls the display states of the status indicators of the corresponding DIMM slots.
7. The easy repair recycling design system for memory sticks of claim 6, wherein said control mechanism further comprises a memory controller; the control mechanism automatically processes the fault memory bank according to the following steps:
the control mechanism starts a BIOS and initializes the register; the control mechanism initializes the SMI and the memory controller;
storing the current state of the register into a storage area, and paying attention to detecting whether the memory bank in each DIMM slot is in place or not; if the memory bar of the DIMM slot is in place, a state indicator lamp corresponding to the DIMM slot is lightened; registering a periodic SIM program, and initializing a memory bank of the DIMM slot; if the memory bar of the DIMM slot is not in place, the state indicator lamp corresponding to the DIMM slot is not lightened;
if the memory initialization in the DIMM slot is normal, the programmable logic device controls the state indicator lamp corresponding to the DIMM slot to be in a lighting state, clears the register state data stored in the storage area, and unloads the SMI program of periodic memory processing;
if the memory initialization is not completed when the periodic time interval of the SMI program arrives, the memory bank initialization is considered to have a fault, the periodic SMI interrupt is triggered, the SMI program of periodic memory processing is executed, the memory of the fault DIMM slot is forbidden, the next DIMM slot is pointed, the data of the register state in the memory area is read, the SMI program is exited, and all register values are restored to the values of the registers read by the memory area;
a check is made for memory in the next DIMM socket.
8. An easy-to-repair recycling design method for a memory bank, characterized by being applied to an easy-to-repair recycling design system for a memory bank according to any one of claims 1 to 7, comprising:
s1, testing and acquiring the use state of each memory chip on the memory bank, wherein the use state comprises a normal use state and a fault state;
s2, when detecting that at least one memory chip on the memory strip fails, automatically shielding the corresponding memory chip with the failure and enabling the memory strip to be used normally.
9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the easy repair recycling design method for memory sticks as claimed in claim 8.
10. A computer-readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the steps of the easy-repair recycling design method for memory banks according to claim 8.
CN202311096677.5A 2023-08-28 2023-08-28 Easy-maintenance and regeneration design system, method and equipment for memory bank Pending CN116994633A (en)

Priority Applications (1)

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CN202311096677.5A CN116994633A (en) 2023-08-28 2023-08-28 Easy-maintenance and regeneration design system, method and equipment for memory bank

Applications Claiming Priority (1)

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CN202311096677.5A CN116994633A (en) 2023-08-28 2023-08-28 Easy-maintenance and regeneration design system, method and equipment for memory bank

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CN116994633A true CN116994633A (en) 2023-11-03

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