CN102384995A - Template trigger digital oscilloscope - Google Patents

Template trigger digital oscilloscope Download PDF

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Publication number
CN102384995A
CN102384995A CN201010273041XA CN201010273041A CN102384995A CN 102384995 A CN102384995 A CN 102384995A CN 201010273041X A CN201010273041X A CN 201010273041XA CN 201010273041 A CN201010273041 A CN 201010273041A CN 102384995 A CN102384995 A CN 102384995A
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China
Prior art keywords
data
measured
template waveforms
template
wave data
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Pending
Application number
CN201010273041XA
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Chinese (zh)
Inventor
吴晓北
徐凯
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HENAN UREIKA SYSTEM ENGINEERING Co Ltd
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HENAN UREIKA SYSTEM ENGINEERING Co Ltd
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Priority to CN201010273041XA priority Critical patent/CN102384995A/en
Publication of CN102384995A publication Critical patent/CN102384995A/en
Pending legal-status Critical Current

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Abstract

The invention relates to an oscilloscope, in particular to a template trigger digital oscilloscope, which comprises a channel analog amplification circuit. The channel analog amplification circuit is connected with a channel analog-digital converter, the channel analog-digital converter is in parallel connection with a comparator, and the analog-digital converter and the comparator are connected with a field programmable gate array (FPGA) processing module. The FPGA processing module is connected with a central processing unit (CPU), the CPU is connected with a flash program memorizer and an inner memorizer, the FPGA processing unit is connected with an outer memorizer, and a trigger software runs on the CPU. The template trigger digital oscilloscope can effectively display waveform state of accidental false signals.

Description

Template triggered digital oscillograph
Technical field
The present invention relates to a kind of oscillograph, relate in particular to a kind of template triggered digital oscillograph.
Background technology
Oscillograph plays an important role in the application in fields such as industrial automation, computing machine, Aero-Space as a kind of universal test surveying instrument.Along with the signal clock speed of system is more and more faster; Every profession and trade is used oscillographic requirement also in continuous development; Except require higher bandwidth on the performance, faster sampling rate and the darker memory length; Just be applied to the testing complex signal more and more continually from the application point oscillograph, comprised fields such as analog-and digital-circuit design, communication, automotive electronics.
In the oscillograph use, when measuring irregular data or in a large amount of periodic functions clocklike, comprise accidental rub-out signal, use traditional edge-triggered can't observe valid data accurately.
Summary of the invention
The object of the invention provides a kind of template triggered digital oscillograph, and it can effectively show the waveform state of accidental rub-out signal.
For solving above-mentioned technical matters; The present invention includes: the channel signal Acquisition Circuit; Described channel signal Acquisition Circuit connects the FPGA processing module, and the FPGA processing module connects CPU, and CPU connects Flash program storage and internal storage; The FPGA processing module connects external storage, the triggering software of the last operation of CPU following steps:
(1) the template waveforms data that prestore;
(2) will prestore template waveforms data and Wave data to be measured compares, if template waveforms data and Wave data to be measured coupling are then sent trigger pip.
Described step (2) compares for tested point is prestored template waveforms data and Wave data to be measured; If this template waveforms data and Wave data to be measured coupling; Then carry out the comparison of next tested point,, send trigger pip until all tested points are relatively finished.
Described channel signal Acquisition Circuit comprises: analog amplify circuit, analog amplify circuit connection mode number converter, analog to digital converter parallel connection comparer.
Described template waveforms data are meant that with Wave data to be measured coupling the template waveforms data are identical with Wave data to be measured, or the template waveforms data are mated gap in the scope of setting with Wave data to be measured.
Described template waveforms data and Wave data trigger matched condition to be measured comprise: mate successfully or mate failure.
Described template waveforms data and Wave data trigger matched condition to be measured comprise: mate successfully or mate failure.
The present invention promptly imports or preserves the template of a waveform in advance, and pre-sets coupling project and redundance.When in irregular waveform, matching predefined waveform, when perhaps in periodic function, finding unmatched waveform, send trigger pip, make the user very easily observe the waveform state of accidental rub-out signal.
Description of drawings
Fig. 1 is a system construction drawing of the present invention.
Fig. 2 and 3 is for the triggering waveform synoptic diagram of first kind of embodiment of the present invention.
Fig. 4 is the program flow diagram of second kind of embodiment of the present invention.
Fig. 5 is the triggering waveform synoptic diagram of second kind of embodiment of the present invention.
Embodiment
First kind of embodiment of the present invention as shown in Figure 1 comprises: the channel signal Acquisition Circuit; Be used to gather the Wave data of input signal; The channel signal Acquisition Circuit comprises: analog amplify circuit; Analog amplify circuit connection mode number converter, analog to digital converter parallel connection comparer, described analog to digital converter is connected the FPGA processing module with comparer.The FPGA processing module connects CPU, and CPU connects Flash program storage and internal storage, and the FPGA processing module connects external storage, and CPU connects display.CPU is ARM9; The FPGA processing module adopts the field programmable gate array LatticeXP2 of a kind of low-power consumption, high-performance and the low price of Lattice company to handle, and channel modulus converter is selected the modulus switching device AD9288 of two 8 bit port 80MSPS of AD company for use.The triggering software of the last operation of CPU following steps:
(1) prestores the template waveforms data in the FPGA processing module;
(2) will prestore template waveforms data and Wave data to be measured compares, if template waveforms data and Wave data to be measured coupling are sent trigger pip when both template waveforms data and Wave data to be measured are inequality.
Shown in Fig. 2 and 3, this waveform is the one-period of normal periodic waveform, is being mingled with some accidental undesired signals in this waveform, needs now clutter is wherein detected.For this reason at first will be by the waveform of user's intercepting one-period, choose wherein part or all as template, redundant numerical value is set, project such as voltage, the time of concern is set; The cycle and the template that are provided with this user then are the basis; Begin to mate the data that the AD analog to digital converter is adopted because be the accidental ripple of making an uproar, so can be very fast synchronously; Then according to the data of the Data Detection relevant position of template; If discovery shown in Figure 2 is not inconsistent, then send synchronizing signal, then the user can observe the unusual waveform constantly that takes place.
Second kind of embodiment of the present invention comprises: the channel signal Acquisition Circuit; Be used to gather the Wave data of input signal; The channel signal Acquisition Circuit comprises: analog amplify circuit; Analog amplify circuit connection mode number converter, analog to digital converter parallel connection comparer, described analog to digital converter is connected the FPGA processing module with comparer.The FPGA processing module connects CPU, and CPU connects Flash program storage and internal storage, and the FPGA processing module connects external storage, and CPU connects display.CPU is ARM9; The FPGA processing module adopts the field programmable gate array LatticeXP2 of a kind of low-power consumption, high-performance and the low price of Lattice company to handle, and channel modulus converter is selected the modulus switching device AD9288 of two 8 bit port 80MSPS of AD company for use.The triggering software of the last operation of CPU following steps:
(1) prestores the template waveforms data in the FPGA processing module;
(2) prestore template waveforms data and Wave data to be measured of tested point compared,,, send trigger pip until all tested points are relatively finished if this template waveforms data and Wave data to be measured coupling are then carried out the comparison of next tested point.Its concrete steps are as shown in Figure 4, and Wave data to be measured is gathered at first counter O reset; In the FPGA processing module, take out the template waveforms data; Wave data to be measured and template waveforms data are mated, and see that promptly whether numerical value equate, if equate then counter adds 1 accomplishes until whole couplings.
As shown in Figure 5 in some application scenario, data waveform is not stable periodic waveform, and the waveform that the user needs is mixed in other central appearance of waveform; Use FPGA to mate fast; When detecting identical waveform, then send synchronizing signal, make the user can observe waveform at that time.
As a kind of improvement of the present invention; Also can be the coupling failure in template waveforms data and Wave data trigger matched condition to be measured; Be that described template waveforms data and Wave data to be measured are inequality, or template waveforms data and Wave data gap to be measured are outside the scope of setting.Thereby under the situation of template waveforms data and the failure of Wave data to be measured coupling, trigger oscillograph and scan, show the waveform under this state.

Claims (6)

1. template triggered digital oscillograph; Comprise: the channel signal Acquisition Circuit; It is characterized in that: described channel signal Acquisition Circuit connects the FPGA processing module, and the FPGA processing module connects CPU, and CPU connects Flash program storage and internal storage; The FPGA processing module connects external storage, the triggering software of the last operation of CPU following steps:
(1) the template waveforms data that prestore;
(2) will prestore template waveforms data and Wave data to be measured compares, if template waveforms data and Wave data to be measured coupling are then sent trigger pip.
2. the compound triggered digital oscillograph of hyperchannel according to claim 1; It is characterized in that: described step (2) compares for tested point is prestored template waveforms data and Wave data to be measured; If this template waveforms data and Wave data to be measured coupling; Then carry out the comparison of next tested point,, send trigger pip until all tested points are relatively finished.
3. the compound triggered digital oscillograph of hyperchannel according to claim 1 and 2 is characterized in that: described channel signal Acquisition Circuit comprises: analog amplify circuit, analog amplify circuit connection mode number converter, analog to digital converter parallel connection comparer.
4. according to claim 1, the compound triggered digital oscillograph of 2 or 3 described hyperchannels; It is characterized in that: described template waveforms data are meant that with Wave data to be measured coupling the template waveforms data are identical with Wave data to be measured, or the template waveforms data are mated gap in the scope of setting with Wave data to be measured.
5. according to claim 1, the compound triggered digital oscillograph of 2 or 3 described hyperchannels, it is characterized in that: described template waveforms data and Wave data trigger matched condition to be measured comprise: mate successfully or mate failure.
6. the compound triggered digital oscillograph of hyperchannel according to claim 4 is characterized in that: described template waveforms data and Wave data trigger matched condition to be measured comprise: mate successfully or mate failure.
CN201010273041XA 2010-09-06 2010-09-06 Template trigger digital oscilloscope Pending CN102384995A (en)

Priority Applications (1)

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CN201010273041XA CN102384995A (en) 2010-09-06 2010-09-06 Template trigger digital oscilloscope

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104374975A (en) * 2014-11-25 2015-02-25 苏州立瓷电子技术有限公司 Oscilloscope based on low-power dissipation dual-amplification circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101067630A (en) * 2007-05-17 2007-11-07 王悦 Oscilloscope with higher wave-form refresh rate
CN101126771A (en) * 2007-09-11 2008-02-20 电子科技大学 Digital storage oscilloscope intelligent triggering method and system
CN101131403A (en) * 2006-08-23 2008-02-27 王悦 Digital oscillograph and its waveshape displaying method
US7519874B2 (en) * 2002-09-30 2009-04-14 Lecroy Corporation Method and apparatus for bit error rate analysis

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7519874B2 (en) * 2002-09-30 2009-04-14 Lecroy Corporation Method and apparatus for bit error rate analysis
CN101131403A (en) * 2006-08-23 2008-02-27 王悦 Digital oscillograph and its waveshape displaying method
CN101067630A (en) * 2007-05-17 2007-11-07 王悦 Oscilloscope with higher wave-form refresh rate
CN101126771A (en) * 2007-09-11 2008-02-20 电子科技大学 Digital storage oscilloscope intelligent triggering method and system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104374975A (en) * 2014-11-25 2015-02-25 苏州立瓷电子技术有限公司 Oscilloscope based on low-power dissipation dual-amplification circuit

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Application publication date: 20120321