CN201811988U

CN201811988U - Moldboard trigger digital oscilloscope

Info

Publication number: CN201811988U
Application number: CN2010205179689U
Authority: CN
Inventors: 吴晓北; 徐凯
Original assignee: HENAN UREIKA SYSTEM ENGINEERING Co Ltd
Current assignee: HENAN UREIKA SYSTEM ENGINEERING Co Ltd
Priority date: 2010-09-06
Filing date: 2010-09-06
Publication date: 2011-04-27
Anticipated expiration: 2020-09-06

Abstract

The utility model relates to an oscilloscope, in particular to a moldboard trigger digital storage oscilloscope, which comprises a channel simulating amplifying circuit, wherein the channel simulating amplifying circuit is connected with a channel analog-to-digital converter, the channel analog-to-digital converter and a comparator are connected in parallel, the channel analog-to-digital converter and the comparator are connected with an FPGA (Field Programmable Gata Array) processing module, the FPGA processing module is connected with a CPU (Central Processing Unit), the CPU is connected with a Flash program storage and an inner storage, the FPGA processing module is connected with an outer storage, and a trigger software operates on the CPU. The utility model can effectively display the wave form of a false signal accidentally sent.

Description

Template triggered digital oscillograph

Technical field

The utility model relates to a kind of oscillograph, relates in particular to a kind of template triggered digital oscillograph.

Background technology

Oscillograph plays an important role in the application in fields such as industrial automation, computing machine, Aero-Space as a kind of universal test surveying instrument.Along with the signal clock speed of system is more and more faster, every profession and trade is used oscillographic requirement also in continuous development, except require higher bandwidth on the performance, faster sampling rate and the darker memory length, just be applied to the testing complex signal more and more continually from the application point oscillograph, comprised fields such as analog-and digital-circuit design, communication, automotive electronics.

In the oscillograph use, when measuring irregular data or in a large amount of periodic functions clocklike, comprise accidental rub-out signal, use traditional edge-triggered can't observe valid data accurately.

The utility model content

The utility model purpose provides a kind of template triggered digital oscillograph, and it can effectively show the waveform state of accidental rub-out signal.

For solving above-mentioned technical matters, the utility model comprises: the channel signal Acquisition Circuit, described channel signal Acquisition Circuit connects the FPGA processing module, the FPGA processing module connects CPU, CPU connects Flash program storage and internal storage, the FPGA processing module connects external storage, the triggering software of the last operation of CPU following steps:

(1) the template waveforms data that prestore;

(2) will prestore template waveforms data and Wave data to be measured compares, if template waveforms data and Wave data to be measured coupling are then sent trigger pip.

Described step (2) compares for tested point is prestored template waveforms data and Wave data to be measured, if this template waveforms data and Wave data to be measured coupling, then carry out the comparison of next tested point,, send trigger pip until all tested points are relatively finished.

Described channel signal Acquisition Circuit comprises: analog amplify circuit, analog amplify circuit connection mode number converter, analog to digital converter comparer in parallel.

Described template waveforms data are meant that with Wave data to be measured coupling the template waveforms data are identical with Wave data to be measured, or the template waveforms data are mated gap in the scope of setting with Wave data to be measured.

The trigger condition of described template waveforms data and Wave data to be measured coupling comprises: the match is successful or it fails to match.

The template of a waveform is promptly imported or preserve to the utility model in advance, and pre-set coupling project and redundance.When in irregular waveform, matching predefined waveform, when perhaps in periodic function, finding unmatched waveform, send trigger pip, make the user very easily observe the waveform state of accidental rub-out signal.

Description of drawings

Fig. 1 is a system construction drawing of the present utility model.

Fig. 2 and 3 is the triggering waveform synoptic diagram of first kind of embodiment of the utility model.

Fig. 4 is the program flow diagram of second kind of embodiment of the utility model.

Fig. 5 is the triggering waveform synoptic diagram of second kind of embodiment of the utility model.

Embodiment

First kind of embodiment of the present utility model as shown in Figure 1 comprises: the channel signal Acquisition Circuit, be used to gather the Wave data of input signal, the channel signal Acquisition Circuit comprises: analog amplify circuit, analog amplify circuit connection mode number converter, analog to digital converter comparer in parallel, described analog to digital converter is connected the FPGA processing module with comparer.The FPGA processing module connects CPU, and CPU connects Flash program storage and internal storage, and the FPGA processing module connects external storage, and CPU connects display.CPU is ARM9, the FPGA processing module adopts the field programmable gate array LatticeXP2 of a kind of low-power consumption, high-performance and the low price of Lattice company to handle, and channel modulus converter is selected the modulus switching device AD9288 of two 8 bit port 80MSPS of AD company for use.The triggering software of the last operation of CPU following steps:

(1) prestores the template waveforms data in the FPGA processing module;

(2) will prestore template waveforms data and Wave data to be measured compares, if template waveforms data and Wave data to be measured coupling are sent trigger pip when both template waveforms data and Wave data to be measured are inequality.

Shown in Fig. 2 and 3, this waveform is the one-period of normal periodic waveform, is being mingled with some accidental undesired signals in this waveform, needs now clutter is wherein detected.At first to intercept the waveform of one-period for this reason by the user, choose wherein part or all, redundant numerical value is set, the project of concern such as voltage, time are set as template; Cycle and the template that is provided with based on this user then, begin to mate the data that the AD analog to digital converter is adopted, because be the accidental ripple of making an uproar, so can be very fast synchronously, then according to the data of the Data Detection relevant position of template, if discovery shown in Figure 2 is not inconsistent, then send synchronizing signal, then the user can observe the unusual waveform constantly that takes place.

Second kind of embodiment of the present utility model comprises: the channel signal Acquisition Circuit, be used to gather the Wave data of input signal, the channel signal Acquisition Circuit comprises: analog amplify circuit, analog amplify circuit connection mode number converter, analog to digital converter comparer in parallel, described analog to digital converter is connected the FPGA processing module with comparer.The FPGA processing module connects CPU, and CPU connects Flash program storage and internal storage, and the FPGA processing module connects external storage, and CPU connects display.CPU is ARM9, the FPGA processing module adopts the field programmable gate array LatticeXP2 of a kind of low-power consumption, high-performance and the low price of Lattice company to handle, and channel modulus converter is selected the modulus switching device AD9288 of two 8 bit port 80MSPS of AD company for use.The triggering software of the last operation of CPU following steps:

(1) prestores the template waveforms data in the FPGA processing module;

(2) tested point is prestored template waveforms data and Wave data to be measured compares, if this template waveforms data and Wave data to be measured coupling are then carried out the comparison of next tested point, until all tested points are relatively finished, sends trigger pip.Its concrete steps as shown in Figure 4, Wave data to be measured is gathered at first counter O reset, in the FPGA processing module, take out the template waveforms data, Wave data to be measured and template waveforms data are mated, and see that promptly whether numerical value equate, if equate then counter adds 1 finishes until whole couplings.

In some application scenario, data waveform is not stable periodic waveform as shown in Figure 5, and the waveform that the user needs is mixed in other central appearance of waveform, use FPGA to mate fast, when detecting identical waveform, then send synchronizing signal, make the user can observe at that time waveform.

As a kind of improvement of the present utility model, can be that it fails to match also in the trigger condition of template waveforms data and Wave data to be measured coupling, be that described template waveforms data and Wave data to be measured are inequality, or template waveforms data and Wave data gap to be measured are outside the scope of setting.Thereby under template waveforms data and the Wave data to be measured situation that it fails to match, trigger oscillograph and scan, show the waveform under this state.

Claims

1. template triggered digital oscillograph, comprise: the channel signal Acquisition Circuit is characterized in that: described channel signal Acquisition Circuit connects the FPGA processing module, and the FPGA processing module connects CPU, CPU connects Flash program storage and internal storage, and the FPGA processing module connects external storage.

2. the compound triggered digital oscillograph of hyperchannel according to claim 1 is characterized in that: described channel signal Acquisition Circuit comprises: analog amplify circuit, analog amplify circuit connection mode number converter, analog to digital converter comparer in parallel.