CN102376534A

CN102376534A - Manufacturing method of standard sheet for silicon epitaxial film thickness test

Info

Publication number: CN102376534A
Application number: CN2010102653146A
Authority: CN
Inventors: 刘继全
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2010-08-26
Filing date: 2010-08-26
Publication date: 2012-03-14

Abstract

The invention discloses a manufacturing method of a standard sheet for a silicon epitaxial film thickness test, which comprises the following steps of: (1) depositing a layer of dielectric film on a silicon substrate; (2) patterning and etching the dielectric film so as to form a pattern formed by the dielectric film on the silicon substrate; (3) selectively growing a silicon epitaxial layer on the silicon substrate; (4) removing the dielectric film; and (5) measuring the depth of a groove formed by the silicon epitaxial layer after the dielectric film is removed, wherein the depth is used as a standard thickness of an adjacent silicon epitaxial layer. Through the invention, the silicon epitaxial measurement accuracy can be improved.

Description

The manufacture method of silicon epitaxy thickness testing standard sheet

Technical field

The present invention relates to the semiconductor integrated circuit field, particularly relate to a kind of manufacture method of silicon epitaxy thickness testing standard sheet.

Background technology

Silicon epitaxy thickness method of testing mainly adopts fourier infrared (FTIR) method of testing; The method is that the doping content according to silicon epitaxy layer and substrate layer has evident difference to demarcate the thickness of epitaxial loayer (substrate generally has high doping content, for example highly doped P type or N type substrate).But (generally being higher than 1000 ℃) carried out in epitaxial growth under hot conditions; The dopant of substrate can spread in epitaxial loayer in epitaxial process; Thereby cause moving on the interface of substrate and epitaxial loayer and thickening; The degree of moving on the different epitaxial growth condition interfaces is different, causes existing than mistake with the result that preceding method is measured, so need calibration with preceding method.

Summary of the invention

The technical problem that the present invention will solve provides a kind of manufacture method of silicon epitaxy thickness testing standard sheet, improves silicon epitaxy and measures accuracy.

For solving the problems of the technologies described above, the manufacture method of silicon epitaxy thickness testing standard sheet of the present invention comprises the steps:

Step 1, the layer dielectric of on silicon base, growing;

Step 2, carry out graphical and etching, on silicon base, form the figure that constitutes by said deielectric-coating said deielectric-coating;

Step 3, on said silicon base the selective growth silicon epitaxy layer;

Step 4, remove said deielectric-coating;

Step 5, measure to remove behind the deielectric-coating the degree of depth, with the standard thickness of this degree of depth as the adjacent silicon epitaxial loayer by the formed groove of said silicon epitaxy layer.

Because silicon epitaxy layer and deielectric-coating all grow on silicon base, the bottom of formed groove was the interface of silicon base after deielectric-coating was removed, and the degree of depth of groove is the thickness of epitaxial loayer.Therefore method of the present invention can obtain accurately to demarcate the silicon epitaxy standard film of epitaxy layer thickness, effectively solves silicon epitaxy thickness measurement problem.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:

Fig. 1-the 6th, method one embodiment process flow diagram of the present invention;

Fig. 7 is method one an embodiment control flow chart of the present invention.

Embodiment

Referring to shown in Figure 7, in one embodiment, the manufacture method of said silicon epitaxy thickness testing standard sheet comprises the steps:

Step 1, combine shown in Figure 1, growth one layer dielectric 2 on silicon base 1.Said silicon base 1 is P+ silicon base or N+ silicon base, for example adopts P type heavy doping silicon chip (resistivity＜0.01ohm.cm).The dielectric film 2 is a silicon oxide film having a thickness of

Of course, the medium may be a silicon oxide film 2 other than the dielectric film, such as silicon nitride or silicon oxynitride; wherein the thickness of the dielectric film 2 is not limited to Yu

For example in the 500 -

Step 2, combine Fig. 2, shown in 3, said deielectric-coating 2 carried out graphical and etching, on silicon base 1, form the ring-shaped figure that constitutes by said deielectric-coating 2.Fig. 2 is the sectional drawing of formed figure after deielectric-coating is etched, and Fig. 3 is the vertical view of formed figure after deielectric-coating is etched.The deielectric-coating 2 that behind over etching, circularizes is concentric with silicon base 1, and the width of annular is 10-100 μ m; The deielectric-coating of annular can be a ring or equally spaced a plurality of ring.

Step 3, combine shown in Figure 4, selective growth silicon epitaxy layer 3 on said silicon base 1.Be that silicon epitaxy layer 3 is only grown on silicon base, on silicon oxide film, do not grow.The thickness of silicon epitaxy layer 3 is about

.The thickness of silicon epitaxy layer 3 is less than the thickness of deielectric-coating 2 in this step.

Step 4, combine Fig. 5, shown in 6, remove the deielectric-coating 2 on the said silicon base 1, groove 4 appearance that formed by silicon epitaxy layer 3 are just arranged on said silicon base 1 like this.Said deielectric-coating 2 can adopt wet method or dry etching to remove.Fig. 5 is the sectional drawing of the formed figure after deielectric-coating 2 is removed, and Fig. 6 is the vertical view that deielectric-coating is removed the formed figure in back.

Step 5, measure the degree of depth that deielectric-coating 2 is removed the formed groove 4 in back with the scan-probe method.Because groove 4 bottoms are the interface of silicon base 1, so the degree of depth of groove 4 is the thickness of silicon epitaxy layer 3.The degree of depth of the groove of measuring with the scan-probe method 4 can be used as the standard thickness (standard thickness of adjacent position silicon epitaxy layer 3) of this epitaxial wafer, can demarcate the FTIR assay method with this epitaxial wafer.

More than through embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.

Claims

1. the manufacture method of a silicon epitaxy thickness standard film is characterized in that, comprises the steps:

Step 1, on silicon base deposit one layer dielectric;

Step 3, on said silicon base the selective growth silicon epitaxy layer;

Step 4, remove said deielectric-coating;

The degree of depth of the groove that is formed by said silicon epitaxy layer behind step 5, the mensuration removal deielectric-coating is with the standard thickness of this degree of depth as the adjacent silicon epitaxial loayer.

2. manufacture method as claimed in claim 1 is characterized in that: the resistivity of silicon base is less than or equal to 0.05ohm.cm.

3. manufacture method as claimed in claim 1; It is characterized in that: deielectric-coating described in the step 1 is at least a in silica, silicon nitride or the silicon oxynitride, and thickness is 500-

4. manufacture method as claimed in claim 1 is characterized in that: the figure described in the step 2 is annular and concentric with said silicon base, and annular width is 1-100 μ m; Said figure is a ring or equally spaced a plurality of ring.

5. manufacture method as claimed in claim 1 is characterized in that: selective growth described in the step 3, and grown silicon epitaxial loayer on said silicon base only, grown silicon epitaxial loayer not on said deielectric-coating, and the thickness of silicon epitaxy layer is less than the thickness of deielectric-coating.

6. manufacture method as claimed in claim 1 is characterized in that: the mensuration in the step 5 adopts the scan-probe method to measure the degree of depth of groove.