CN102097348A - Electric test structure and method for measuring epitaxial graphic offset - Google Patents
Electric test structure and method for measuring epitaxial graphic offset Download PDFInfo
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- CN102097348A CN102097348A CN2010105757965A CN201010575796A CN102097348A CN 102097348 A CN102097348 A CN 102097348A CN 2010105757965 A CN2010105757965 A CN 2010105757965A CN 201010575796 A CN201010575796 A CN 201010575796A CN 102097348 A CN102097348 A CN 102097348A
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- 238000012360 testing method Methods 0.000 title claims abstract description 144
- 238000000034 method Methods 0.000 title claims abstract description 17
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- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005259 measurement Methods 0.000 claims description 12
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
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Abstract
The invention relates to an electric test structure for measuring epitaxial graphic offset, comprising a buried layer formed on the surface of a semiconductor substrate, an epitaxial layer formed on the surface of the semiconductor substrate, a plug region equidistantly which is formed in the epitaxial layer on the surface of the semiconductor substrate and has a preset offset different with the buried layer along the same direction, a contact hole formed on the surface of the plug region as well as a first conductive connection, a second conductive connection and a third conductive connection which are sequentially formed at the contact hole on the adjacent plug region. The method for measuring the epitaxial graphic offset comprises the step of respectively carrying out an electric test on the electric test structure with different preset offsets. In the invention, the electric test structure is utilized to measure the epitaxial graphic offset, not only is the measuring accuracy higher, but also the registration error of a graph after extension to the graph before extension can be effective reduced.
Description
Technical field
The present invention relates to the epitaxy technique in the integrated circuit manufacturing, relate in particular to a kind of electrical testing structure and method thereof of measuring the epitaxial patterns side-play amount.
Background technology
In the bipolar semiconductor manufacturing process, the method at surface of silicon growth one deck single-crystal semiconductor thin film is referred to as extension.On initial wafer, carry out epitaxial growth many benefits are arranged.One, epitaxial loayer do not need to have identical doping type with the lower floor wafer.For example in bipolar process, N type epitaxial loayer can be grown on the P type substrate.Secondly, unlike CZ silicon, epitaxial silicon can not stain by oxygen or carbon.
Simultaneously, in epitaxial loayer, also allow to form buried regions.The N+ buried regions becomes the committed step in most bipolar process, because it makes the vertical NPN transistor of making low collector resistance become possibility.Arsenic and antimony are the first-selected impurity that forms n type buried layer, because the low diffusion rate of described arsenic and antimony makes the horizontal proliferation minimum of buried regions in high-temperature process subsequently.Antimony is than the more normal use of arsenic because it outside time-delay table reveal littler laterally mixing automatically.
The N+ buried regions that forms in described epitaxial loayer needs annealed with the elimination implant damage, in annealing process thermal oxidation can take place, and it is discontinuous slight silicon face to occur around the oxidation meeting causes at the oxidation layer window edge.Epitaxial loayer will be discontinuous at the described silicon face of final surface-rendering of wafer faithfully.Examine under a microscope and can find, the surface of epitaxial loayer has formed a profile faintly, is called the n type buried layer shade.In lithography step subsequently, the etching in for example dark N+ district, described dark N+ district will with the discontinuous aligned in position of described silicon face.This preceding layer pattern displacement that produces later on through extension is called the domain displacement, and promptly figure through after the epitaxial growth certain drift has taken place.
When outside the photoetching delayed need and extension before lithography alignment the time, must when exposing, compensate this side-play amount.The value of compensation generally multiply by a penalty coefficient by epitaxial thickness and obtains.But described penalty coefficient is an empirical value, can not meet fully with real offset, and make the compensation inaccuracy, can not control effectively outer delay figure to extension before the registration error of figure.
The problem that prior art exists, this case designer relies on the industry experience for many years of being engaged in, and the active research improvement is so there has been the present invention to utilize electrical parameter to measure the method for extent pattern drifting quantity.
Summary of the invention
The present invention be directed in the prior art, to the compensation inaccuracy of extension map migration amount, can not control effectively outer delay figure to extension before the defectives such as registration error of figure, a kind of electrical testing structure of measuring the epitaxial patterns side-play amount is provided.
Another purpose of the present invention is in the prior art, compensation inaccuracy to extension map migration amount, can not control effectively outer delay figure to extension before the defectives such as registration error of figure, a kind of method of utilizing described electrical testing structure to measure the epitaxial patterns side-play amount is provided.
In order to address the above problem, the invention provides a kind of electrical testing structure of measuring the epitaxial patterns side-play amount, the electrical testing structure of described measurement epitaxial patterns side-play amount comprises: buried regions is formed on semiconductor substrate surface; Epitaxial loayer is formed on the semiconductor substrate surface with described buried regions; The plug district equidistantly is formed in the epitaxial loayer on described buried regions surface, and has different default bias amounts along equidirectional and described buried regions; Contact hole is formed on surface, described plug district; And the contact hole place in described adjacent plug district first conductive connecting line, second conductive connecting line and the 3rd conductive connecting line that form successively.The plug district is offset along equidirectional, and each electrical testing structure with different default bias amounts forms an electrical testing structure group.
Wherein, the size of described default bias amount is 0 to 1 times of arbitrary numerical value between the epitaxy layer thickness.
The step-length in described plug district is determined according to the thickness of epitaxial loayer and the precision of compensation rate.
Described step-length is between 0.01 micron to 1 micron.
Optionally, when described epitaxy layer thickness was 1 micron, step-length was 0.1 micron.
Optionally, described electrical testing structure group is included in equidirectional skew, and the default bias amount is respectively 0 micron, and 0.1 micron, 0.2 micron, 0.3 micron, 0.4 micron, 0.5 micron, 0.6 micron, 0.7 micron, 0.8 micron, 0.9 micron, 1 micron electrical testing structure.
Optionally, described electrical testing structure has 3 adjacent plug districts.
The direction of electrical testing structure be with respect to buried regions along X positive direction, X negative direction, Y positive direction, and Y negative direction.
For realizing another purpose of the present invention, the invention provides a kind of method of utilizing described electrical testing structure to measure the epitaxial patterns side-play amount, the method for testing of described epitaxial patterns side-play amount comprises:
The electrical testing structure with different default bias amounts in the electrical testing structure group is carried out electrical testing respectively, first conductive connecting line of test electrical testing structure and first resistance between second conductive connecting line, and second second resistance between conductive connecting line and the 3rd conductive connecting line
If described first resistance equates with described second resistance, just then the pairing default bias amount of this electrical testing structure is a real offset;
If described first resistance and described second resistance are all unequal, then the electrical testing structure in the electrical testing structure group opposite with offset direction, described electrical testing structure group plug district carries out described electrical testing respectively, if described first resistance equates with described second resistance, just then the pairing default bias amount of this electrical testing structure is a real offset;
If described first resistance and described second resistance are all unequal, then in described electrical testing structure group and the electrical testing structure group opposite, choose the pairing default bias amount of electrical testing structure of first resistance and the second resistance difference minimum as real offset with offset direction, described electrical testing structure group plug district.
In sum, the present invention measures the epitaxial patterns side-play amount by utilizing electrical testing structure, makes that not only measuring accuracy is higher, and can effectively reduce outer delay figure to extension before the registration error of figure.
Description of drawings
Fig. 1 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount has the first default bias amount along the X positive direction structural representation;
Fig. 2 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount has the second default bias amount along the X positive direction structural representation;
Fig. 3 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount has the 3rd default bias amount along the X positive direction structural representation;
Fig. 4 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount has the 4th default bias amount along the X negative direction structural representation;
Fig. 5 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount has the 5th default bias amount along the X negative direction structural representation;
Fig. 6 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount has the 6th default bias amount along the Y positive direction structural representation;
Fig. 7 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount has the 7th default bias amount along the Y positive direction structural representation;
Fig. 8 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount has the 8th default bias amount along the Y positive direction structural representation;
Fig. 9 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount has the 9th default bias amount along the Y negative direction structural representation;
Figure 10 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount has the tenth default bias amount along the Y negative direction structural representation.
Embodiment
By the technology contents, the structural feature that describe the invention in detail, reached purpose and effect, described in detail below in conjunction with embodiment and conjunction with figs..
See also Fig. 1～Figure 10, Fig. 1～Figure 10 shows that measures the schematic diagram of the electrical testing structure 1 of epitaxial patterns side-play amount.Described electrical testing structure 1 is included in Semiconductor substrate (not shown) surface with first conduction type ion and carries out the diffusion of second conduction type ion, is positioned at the buried regions with second conduction type ion 10 of described semiconductor substrate surface with formation.Form epitaxial loayer 11 with second conduction type ion in semiconductor substrate surface extension with described buried regions 10.Described buried regions 10 is between Semiconductor substrate and epitaxial loayer 11.
Be positioned at described epitaxial loayer 11, and be positioned at buried regions 10 surfaces along the same offset direction etching and the some plugs of the formation district 12 of mixing.Described plug district 12 is that the second conduction type ion heavy doping forms.Described plug district 12 equidistant and with respect to described buried regions 10 along X positive direction, X negative direction, Y positive direction, and the Y negative direction has different default bias amounts.
Wherein, described default bias amount is 0 to 1 times of arbitrary numerical value between epitaxial loayer 11 thickness.The step-length in described plug district 12 is determined by the thickness of epitaxial loayer 11 and the precision of compensating offset amount.Described step-length is between 0.01 micron to 1 micron.For example epitaxial loayer 11 thickness are 1 micron technology, and step-length is made as 0.1 micron, and then the mechanism for testing 1 in the positive direction of X comprises: 0 micron, and 0.1 micron, 0.2 micron, 0.3 micron, 0.4 micron, 0.5 micron, 0.6 micron, 0.7 micron, 0.8 micron, 0.9 micron, 1 micron.In the negative direction of X, the rest may be inferred for the positive direction of Y and the mechanism for testing of negative direction 1.
In the present embodiment, be listed below different default bias values of measuring, but not as limitation of the present invention.Particularly, i.e. Fig. 1～Figure 3 shows that structural representation that has the electrical testing structure 1 of the first default bias amount 121, the second default bias amount 122, the 3rd default bias amount 123 along the X positive direction with respect to buried regions 10 respectively.Fig. 4～Figure 5 shows that structural representation that has the electrical testing structure 1 of the 4th default bias amount 124, the 5th default bias amount 125 along the X negative direction with respect to buried regions 10.Fig. 6～Figure 8 shows that structural representation that has the electrical testing structure 1 of the 6th default bias amount 126, the 7th default bias amount 127, the 8th default bias amount 128 along the Y positive direction with respect to buried regions 10 respectively.Fig. 9～Figure 10 shows that structural representation that has the electrical testing structure 1 of the 9th default bias amount 129, the tenth default bias amount 120 along the Y negative direction with respect to buried regions 10.
Correspondingly form contact hole 13 on 12 surfaces, described plug district.Described contact hole 13 is electrically connected with outer test circuit by the conductive connecting line that is positioned at successively in the described plug district 12.
In the present invention, preferably, described electrical testing structure 1 comprises 3 adjacent plug districts 12, and forms first conductive connecting line 141, second conductive connecting line 142 successively at contact hole 13 places in described adjacent plug district 12, and the 3rd conductive connecting line 143.
Utilize described electrical testing structure 1 to measure the method for epitaxial patterns side-play amount, comprise: the electrical testing structure with different default bias amounts 1 in the electrical testing structure group is carried out electrical testing respectively, first conductive connecting line 141 of test electrical testing structure 1 and first resistance between second conductive connecting line 142, and second second resistance between conductive connecting line 142 and the 3rd conductive connecting line 143
If described first resistance equates with described second resistance, just then this electrical testing structure 1 pairing default bias amount is a real offset;
If described first resistance and described second resistance are all unequal, then the electrical testing structure 1 in the electrical testing structure group opposite with 12 offset directions, described electrical testing structure group plug district carries out described electrical testing respectively, if described first resistance equates with described second resistance, just then this electrical testing structure 1 pairing default bias amount is a real offset;
If described first resistance and described second resistance are all unequal, then in described electrical testing structure group and the electrical testing structure group opposite, choose the electrical testing structure 1 pairing default bias amount of first resistance and the second resistance difference minimum as real offset with 12 offset directions, described electrical testing structure group plug district.
Particularly, if carry out the measurement of X pros and X negative direction real offset, choose one in the electrical testing structure with different default bias amounts of the electrical testing structure group that then on the X positive direction, forms wantonly, and this electrical testing structure 1 is carried out electrical testing.That is, choose first conductive connecting line 141, second conductive connecting line 142 that electrical testing structure 1 is positioned at contact hole 13 places in the described adjacent plug district 12 successively, and the 3rd conductive connecting line 143 carries out resistance test.At this moment, the resistance between the electrical testing structure 1 that untired definition first conductive connecting line 141 and second conductive connecting line 142 are constituted is first resistance, and the resistance of the electrical testing structure 1 that second conductive connecting line 142 and the 3rd conductive connecting line 143 are constituted is second resistance.
If described first resistance equates with described second resistance, just this electrical testing structure 1 pairing default bias amount real offset that is the X positive direction then.If described first resistance and described second resistance do not wait, then in the electrical testing structure with different default bias amounts 1 of the electrical testing structure group that is offset along the X negative direction, choose one wantonly, and test first conductive connecting line 141 of described electrical testing structure 1 and first resistance between second conductive connecting line 142, and second second resistance between conductive connecting line 142 and the 3rd conductive connecting line 143, if described first resistance equates with described second resistance, just then this electrical testing structure 1 pairing skew is a real offset; If described first resistance and described second resistance are all unequal, then described be real offset along the electrical testing structure group of X positive direction skew and along the electrical testing structure 1 pairing side-play amount of choosing first resistance and the second resistance difference minimum in the electrical testing structure group of X negative direction skew.
Similarly, if carry out the measurement of Y pros and Y negative direction real offset, choose one in the electrical testing structure with different default bias amounts of the electrical testing structure group that then on the Y positive direction, forms wantonly, and this electrical testing structure 1 is carried out electrical testing.That is, choose first conductive connecting line 141, second conductive connecting line 142 that electrical testing structure 1 is positioned at contact hole 13 places in the described adjacent plug district 12 successively, and the 3rd conductive connecting line 143 carries out the series resistance test.At this moment, the resistance between the electrical testing structure 1 that untired definition first conductive connecting line 141 and second conductive connecting line 142 are constituted is first resistance, and the resistance of the electrical testing structure 1 that second conductive connecting line 142 and the 3rd conductive connecting line 143 are constituted is second resistance.
If described first resistance equates with described second resistance, just this electrical testing structure 1 pairing default bias amount real offset that is the Y positive direction then.If described first resistance and described second resistance do not wait, then in the electrical testing structure with different default bias amounts 1 of the electrical testing structure group that is offset along the Y negative direction, choose one wantonly, and test first conductive connecting line 141 of described electrical testing structure 1 and first resistance between second conductive connecting line 142, and second second resistance between conductive connecting line 142 and the 3rd conductive connecting line 143, if described first resistance equates with described second resistance, just then this electrical testing structure 1 pairing skew is a real offset; If described first resistance and described second resistance are all unequal, then described be real offset along the electrical testing structure group of Y positive direction skew and along the electrical testing structure 1 pairing side-play amount of choosing first resistance and the second resistance difference minimum in the electrical testing structure group of Y negative direction skew.
By utilizing 1 pair of epitaxial patterns of described electrical testing structure in X positive direction, X negative direction, Y positive direction, and the real offset of Y negative direction measures, and just obtains the real offset of epitaxial patterns.
In sum, the present invention measures the epitaxial patterns side-play amount by utilizing electrical testing structure, makes that not only measuring accuracy is higher, and can effectively reduce outer delay figure to extension before the registration error of figure.
Those skilled in the art all should be appreciated that, under the situation that does not break away from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thereby, if when any modification or modification fall in the protection range of appended claims and equivalent, think that the present invention contains these modifications and modification.
Claims (9)
1. an electrical testing structure of measuring the epitaxial patterns side-play amount is characterized in that, the electrical testing structure of described measurement epitaxial patterns side-play amount comprises:
Buried regions is formed on semiconductor substrate surface;
Epitaxial loayer is formed on the semiconductor substrate surface with described buried regions;
The plug district equidistantly is formed in the epitaxial loayer on described buried regions surface, and has different default bias amounts along equidirectional and described buried regions;
Contact hole is formed on surface, described plug district;
And, first conductive connecting line, second conductive connecting line and the 3rd conductive connecting line that the contact hole place in described adjacent plug district forms successively;
The plug district is offset along equidirectional, and each electrical testing structure with different default bias amounts forms an electrical testing structure group.
2. the electrical testing structure of measurement epitaxial patterns side-play amount as claimed in claim 1 is characterized in that, the size of described default bias amount is 0 to 1 times of arbitrary numerical value between the epitaxy layer thickness.
3. the electrical testing structure of measurement epitaxial patterns side-play amount as claimed in claim 1 is characterized in that, the step-length in described plug district is determined according to the thickness of epitaxial loayer and the precision of compensation rate.
4. the electrical testing structure of measurement epitaxial patterns side-play amount as claimed in claim 3 is characterized in that, described step-length is between 0.01 micron to 1 micron.
5. the electrical testing structure of measurement epitaxial patterns side-play amount as claimed in claim 3 is characterized in that, when described epitaxy layer thickness was 1 micron, step-length was 0.1 micron.
6. the electrical testing structure of measurement epitaxial patterns side-play amount as claimed in claim 5 is characterized in that, described electrical testing structure group is included in the equidirectional skew, and the default bias amount is respectively 0 micron, 0.1 micron, and 0.2 micron, 0.3 micron, 0.4 micron, 0.5 micron, 0.6 micron, 0.7 micron, 0.8 micron, 0.9 micron, 1 micron electrical testing structure.
7. the electrical testing structure of measurement epitaxial patterns side-play amount as claimed in claim 1 is characterized in that, the direction of electrical testing structure be with respect to buried regions along X positive direction, X negative direction, Y positive direction, and Y negative direction.
8. the electrical testing structure of measurement epitaxial patterns side-play amount as claimed in claim 1 is characterized in that, described electrical testing structure has 3 adjacent plug districts.
9. method of utilizing electrical testing structure as claimed in claim 1 to measure the epitaxial patterns side-play amount is characterized in that the method for described measurement epitaxial patterns side-play amount comprises:
The electrical testing structure with different default bias amounts in the electrical testing structure group is carried out electrical testing respectively, first conductive connecting line of test electrical testing structure and first resistance between second conductive connecting line, and second second resistance between conductive connecting line and the 3rd conductive connecting line
If described first resistance equates with described second resistance, just then the pairing default bias amount of this electrical testing structure is a real offset;
If described first resistance and described second resistance are all unequal, then the electrical testing structure in the electrical testing structure group opposite with offset direction, described electrical testing structure group plug district is carried out described electrical testing respectively, if described first resistance equates with described second resistance, just then the pairing default bias amount of this electrical testing structure is a real offset;
If described first resistance and described second resistance are all unequal, then in described electrical testing structure group and the electrical testing structure group opposite, choose the pairing default bias amount of electrical testing structure of first resistance and the second resistance difference minimum as real offset with offset direction, described electrical testing structure group plug district.
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| CN103137603B (en) * | 2011-11-23 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | Under monitoring polysilicon side wall, light dope injects test structure and the method for stability |
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| US11854915B2 (en) | 2021-07-09 | 2023-12-26 | Changxin Memory Technologies, Inc. | Electrical test structure, semiconductor structure and electrical test method |
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| JPS57159014A (en) * | 1981-03-25 | 1982-10-01 | Nec Home Electronics Ltd | Measuring method for characteristics of epitaxial semiconductor wafer |
| JPH08330375A (en) * | 1995-05-31 | 1996-12-13 | Oki Electric Ind Co Ltd | Pattern and method for measuring effective gate length of schottky gate field effect transistor |
| JPH10303104A (en) * | 1997-04-28 | 1998-11-13 | Sony Corp | Method and pattern structure for measuring mask alignment accuracy |
| US20030199110A1 (en) * | 2002-04-19 | 2003-10-23 | Hitachi, Ltd. | Method for test conditions |
| US20060128041A1 (en) * | 2002-12-27 | 2006-06-15 | Nanya Technology Corporation | Misalignment test structure and method thereof |
| KR100902080B1 (en) * | 2008-07-11 | 2009-06-15 | 주식회사 엠아이티 | Insulator electric conduction plate, method of manufacturing the insulator electric conduction plate |
| US20120018723A1 (en) * | 2010-07-20 | 2012-01-26 | Keng-Li Su | Structure and method for testing through-silicon via (tsv) |
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2010
- 2010-12-06 CN CN201010575796.5A patent/CN102097348B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57159014A (en) * | 1981-03-25 | 1982-10-01 | Nec Home Electronics Ltd | Measuring method for characteristics of epitaxial semiconductor wafer |
| JPH08330375A (en) * | 1995-05-31 | 1996-12-13 | Oki Electric Ind Co Ltd | Pattern and method for measuring effective gate length of schottky gate field effect transistor |
| JPH10303104A (en) * | 1997-04-28 | 1998-11-13 | Sony Corp | Method and pattern structure for measuring mask alignment accuracy |
| US20030199110A1 (en) * | 2002-04-19 | 2003-10-23 | Hitachi, Ltd. | Method for test conditions |
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| CN103137603B (en) * | 2011-11-23 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | Under monitoring polysilicon side wall, light dope injects test structure and the method for stability |
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