CN102346689B - 用于暂停处理器中执行过程的方法和装置 - Google Patents
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Abstract
描述用于暂述来自一个线程的指令的执行的方法和装置。在一个实施例中,暂停指令作为两种指令或微指令来实现:SET指令和READ指令。当接收到用于指定线程的SET标志时,SET指令在存储器中设置一Bit标志表示已经暂停对该线程的执行。SET指令被放在流水线中以便执行。然而用于那个线程的READ指令被阻止进入流水线直到SET指令被执行且退役(由清除Bit标志引起)。一旦Bit标志被清除,READ指令被放在流水线中以便执行。在暂停一个线程的处理的时间中,其他线程的执行可能继续。
Description
技术领域
本发明涉及用于暂停在处理器等中执行过程的方法和装置。更具体而言,本发明的实施方案涉及控制暂停多个线程中的一个的执行过程,以便将优先权给另一个线程或省电。
背景技术
如本领域所公知的,处理器包括许多子模块,每一子模块适用于执行特定任务。在公知处理器中,这些子模块包括如下:指令高速缓冲存储器,取指令单元用于从指令高速缓冲存储器中取适当指令;译码逻辑,将指令译码成最后或中间格式;微操作逻辑,将中间指令转换成用于执行的最后格式;以及执行单元,执行最后格式指令(在一些例子中来自译码逻辑,而在另外的例子中来自微操作逻辑)。
在时钟的操作下,处理器系统的执行单元执行提交给它的连续指令。如本领域所公知的,指令可提供给执行单元,该执行单元对处理器系统来说不产生重大的工作作用。例如,在X86处理器系统中,NOP(空操作)指令使执行单元不对“指令周期”采取行动。在此所使用的指令周期是处理器所需要的用于执行指令的设定的处理器时钟周期数。实际效果是,NOP指令处理器阻塞一个指令周期。
NOP指令的局限在于它使处理器阻塞一个设定的时间单位。因此,使用一个或多个NOP指令,处理器仅能被阻塞等于总的许多指令周期的一段时间。
NOP指令的另一个局限是处理器的执行单元不能进行任何其他指令执行。例如,由执行单元要执行的指令可被细分为两个或多个“线程”。每一线程是用来实现指定任务的一组指令。因此,如果其中一个线程包括NOP指令,该指令由执行单元执行并且阻塞整个处理器(即在NOP指令执行期间不能完成其他线程的执行)。
由上可知,需要一种避免这些局限的暂停处理器执行的改进的方法和装置。
发明内容
根据本发明的实施方案,一种暂停执行线程中指令的方法被提出。首先,确定用于第一线程的下一指令是否是第一种类型的指令。如果是,要执行的第一线程的指令将不被处理而要执行的来自第二线程的指令能被处理。
附图说明
图1是采用本发明附加实施方案处理器中一部分的方框图。
图2是根据本发明附加实施方案,表示实施方案方法的流程图。
图3是采用本发明附加实施方案的处理器的一部分的方框图。
图4是根据本发明附加实施方案,表示附加实施方案方法的流程图。
具体实施方式
参考图1,示出了采用本发明的实施方案的处理器系统10中一部分的例子。在该实施方案中,处理器是多线程处理器,其中执行理论上被细分为两个或多个逻辑处理器。在此,术语“线程”指的是指令码序列。
例如,在电视电话应用中,处理器可被要求执行代码来处理视频图像数据以及音频数据。可以是分开的代码序列,其执行被指定来逐个处理这些数据类型。因此,第一线程可包括用于视频图像数据处理的指令而第二线程可用于音频数据处理的指令。在该例中,有一个单独的执行单元(无次序的执行单元31),一次可执行一个指令。然而,处理器系统10可被视为两个逻辑处理器,第一逻辑处理器执行来自第一线程(线程0)的指令以及第二逻辑处理器执行来自第二线程(线程1)的指令。
在本处理器系统10的实施方案中,指令由取指令单元11抽取并提供给队列13并被存储为线程0队列或线程1队列的一部分。本领域的技术人员能理解在处理器系统10中,使用的队列可被用来存储多于两个线程。来自两个线程的指令被提供给复用器(MUX)15,以及控制逻辑17用来控制是线程0还是线程1的指令被提供给译码单元21。译码单元21可将指令转换成两个或多个微指令并将该指令提供给队列23。队列23的输出被提供给MUX,基于控制逻辑26的操作,MUX将来自线程0或线程1的指令提供给重命名/分配单元27。重命名/分配单元27依次将指令提供给队列28。基于进度控制逻辑30的操作,MUX29在线程0队列和线程1队列间选择。而进度控制逻辑30也接收与MUX29相同的输入。MUX29的输出被提供给执行指令的执行单元31。然后指令被放在队列33中。队列33的输出被提供给MUX34。基于控制逻辑35的操作,MUX34将来自线程0和线程1的指令发送给退役(retire)单元36。
根据本发明的第一实施方案,暂停指令被用来挂起线程的指令的处理。在图1例中,暂停指令由取指令单元11抽取并存储在线程0队列中。线程0队列的输出经MUX15被提供给译码单元21,译码单元21将暂停指令译码成两个微指令:SET指令和READ指令。在译码单元21,SET指令使一值(如位标志19)存储在存储器中,该值表示用于特定线程(在该实例中为线程0)的SET指令已经被接收。然后SET指令被送入“流水线”中。在该实施方案中,“流水线”包括重命名/分配单元27以及执行单元31以及相关队列。执行单元31不对SET指令采取行动(即将其视为已知的NOP指令)。只要SET指令由退役单元26退役,标志19被复位。
在译码单元21,READ指令不被放入流水线中直到标志19被复位。因此,如果在队列13中有来自线程1的指令,这些指令能被译码单元21译码并放入流水线中。因此,取决于队列23、28和33中线程1指令的数量将影响线程0的执行将被暂停多久(即,在流水线中线程1指令的数量越多,SET指令到达退役(retire)单元36的时间越长)。只要标志19被复位,READ指令被发送到队列23并最终被发送到执行单元31。使用SET指令,执行单元不采取行动,如同NOP指令一样。在本发明的实施例,译码单元21从线程0至线程1交替指令的译码。在用于线程0的SET指令后,例如,译码在译码线程1的指令和检验标志19的值直到它被复位间交替。
在该实施方案中译码单元21的操作的例子如图2所示。译码后,在块40中,下一线程的指令被确定。在判定块41中,判定该指令是否是SET指令。如果是,控制传送到块43,在该块处,设置存储器中的位标志。在块47中,SET指令被放入流水线中用于执行单元。然后,控制返回到块40来确定下一线程的下一指令。如果指令不是SET指令,控制传送到判定块45来确定该指令是否是READ指令。如果是,则控制传送到判定块49以确定存储器中适当的位标志是否被设置。如果存储器中位标志被设置,那么控制传送到块51,在该块处指令被从流水线阻止(因此,临时阻止执行来自那个特定线程的指令)。然后控制权被转移到块40来确定来自下一线程的下一指令。如果位标志未被设置(判定块49),那么控制传送到块53,在该块处指令(在这种情况下为READ指令)被放入流水线中用于执行。如上所述,在该实施例中当SET指令被退役时,位标志被复位。然后控制返回到块40来确定来自下一线程的下一指令。同样,如果指令既不是SET指令也不是READ指令,用一正常的方法将其放入流水线中用于执行。
如从上面所看到的,SET指令用来在线程的执行中引起暂停直到该指令退役。这是因为下述的READ指令直到阻塞那个线程其后指令执行的SET指令有效地退役才被放入流水线中。在一个线程的暂停期间,那个线程用于执行的的指令不被处理(例如,放入流水线中,发送到执行单元等等)而来自另一线程用于执行的指令可被处理。当一个线程的执行被暂停时,用于处理系统的总的功耗可被降低。
根据本发明的另一实施方案,暂停指令用定时器或计数器来实现。如图3所示,图1的存储器标志19由计数器39代替。作为第一个例子,当译码单元21确定第一线程的下一指令是暂停指令(即具有特定位格式的指令),那么预定值被送入计数器39中。在该例子中,计数器39从预定值递减计数到0。当计数器递减计数到0时,第二线程(如线程1)的指令被译码并送入流水线中。在该例子中,译码单元21在检验计数器39的值(不是译码线程0的指令)和译码线程1的指令间交替执行。只要计数器结束(如到0),那个线程的下一指令能被装入流水线中。作为第二个例子,暂停指令包括一操作数(即载入到定时器中的值)。因此,这就允许译码单元21将该操作数值装入计数器39以便用于暂停指令的时间长度能被设置。
图3的处理系统的操作的例子如图4所示。在判定块60中,确定该计数器是否到达用于当前线程的预定值。如果没有设置计数器或该值已经到达预定值(如0),那么控制传送到块61以确定用于当前线程的下一指令。如果该指令是暂停指令(判定块63),那么控制传送到判定块65以确定操作数是否与暂停指令有关。如果操作数与暂停指令有关,那么控制传送到块67以将该值装入计数器(然后控制传送到块73以改变到下一线程)。如果操作数与暂停指令无关,那么控制传送到块71中以将预定值装入计数器(然后控制再次传送到块73以改变到下一线程)。如果在判定块63中,指令不是暂停指令,那么控制权传送到69以便将该指令送入流水线中。
根据本发明的实施方案,操作系统使用的暂停指令可作为标识,表示处理系统硬件可进入低功率模式。因此,在处理器系统的操作系统代码(或任何其他软件代码)的执行可使暂停指令转移到译码单元。如上所述,线程的暂停执行可导致在总的功耗上的降低。响应译码暂停指令,处理系统10按照需要可采取其他措施来进一步降低总功耗。
尽管在此特定解释和说明了几个实施方案,应能理解不脱离本发明的精神和想要的范围对本发明的修改和改变通过上述教导和附加权利要求的范围也将被包括。
Claims (20)
1.在线程中暂停指令执行的方法,包括:
确定用于第一线程的下一指令是否是第一种类型的;以及
在一时间周期防止所述第一线程的指令被处理以供执行,同时可处理来自第二线程的指令以供执行;以及
在由所述第一种类型的所述下一指令确定的时间,恢复处理所述第一线程的指令以供执行。
2.如权利要求1所述的方法,其中所述第一种类型的所述下一指令是SET指令以及接下来的指令是READ指令。
3.如权利要求2所述的方法,其中所述SET指令使用于所述第一线程的值存储在存储器中。
4.如权利要求3所述的方法,进一步包括:
当存储在所述存储器中的所述值被复位时,处理所述READ指令以供执行。
5.如权利要求4所述的方法,其中当所述SET指令退役时,存储在所述存储器中的所述值被复位。
6.在线程中暂停指令执行的方法,包括:
确定用于第一线程的下一指令是否是第一种类型的;
如果所述用于第一线程的下一指令是第一种类型的,则启动计数器;以及
防止所述第一线程的指令被处理以供执行,直到所述计数器达到预定值。
7.如权利要求6所述的方法,其中所述用于第一线程的下一指令包括操作数,以及所述启动计数器包括将所述操作数装入所述计数器中。
8.如权利要求6所述的方法,其中,在防止所述第一线程的指令被处理以供执行的同时,用于第二线程的指令可被处理以供执行。
9.在处理器系统中降低功耗的方法,包括:
在所述处理器系统中的译码单元接收来自第一线程的暂停指令;
在一时间周期防止所述第一线程的指令被处理以供执行,同时能够处理来自第二线程的指令以供执行;以及
在由所述暂停指令确定的时间,停止防止所述第一线程的指令被处理以供执行。
10.如权利要求9所述的方法,其中软件代码的执行使在所述译码单元接收所述暂停指令,以及其中所述译码单元执行所述防止。
11.用于在线程中暂停指令执行的装置,包括:
译码单元,用于确定用于第一线程的下一指令是否是第一种类型的,所述译码单元在一时间周期防止所述第一线程的指令被处理以供执行,同时能够处理来自第二线程的指令以供执行,并且在由用于所述第一线程的所述下一指令确定的时间停止所述防止。
12.如权利要求11所述的装置,所述第一种类型的所述下一指令是SET指令以及接下来的指令是READ指令。
13.如权利要求12所述的装置,进一步包括:
存储器,其中所述SET指令使用于所述第一线程的值存储在所述存储器中。
14.如权利要求13所述的装置,其中当存储在所述存储器中的所述值被复位时,所述译码单元处理所述READ指令以供执行。
15.如权利要求14所述的装置,进一步包括:
退役单元,耦合到所述译码单元,其中当所述SET指令由所述退役单元退役时,所述退役单元使存储在所述存储器中的所述值复位。
16.用于在线程中暂停指令执行的装置,包括:
译码单元,确定用于第一线程的下一指令是否是第一种类型的;
计数器,当用于所述第一线程的所述下一指令是所述第一种类型的时,启动该计数器,所述译码单元防止所述第一线程的指令被处理以供执行,直到所述计数器到达预定值。
17.如权利要求16所述的装置,其中所述下一指令包括要装入所述计数器中的操作数。
18.如权利要求16所述的装置,其中,在防止处理所述第一线程的指令以供执行的同时,能够处理用于第二线程的指令以供执行。
19.用于降低处理器系统中功耗的装置,包括:
译码单元,接收来自所述处理器系统中的第一线程的暂停指令,所述译码单元在一周期时间防止所述第一线程的指令被处理以供执行,同时能够处理来自第二线程的指令以供执行,并且在从所述暂停指令译码的指令退役之后,恢复处理所述第一线程的指令以供执行。
20.如权利要求19所述的装置,其中在所述处理器系统的软件代码的执行使在所述译码单元接收所述暂停指令,并且其中响应于从所述暂停指令译码的指令的退役,恢复所述第一线程的指令的处理。
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US7451296B2 (en) | 2008-11-11 |
EP1522917B1 (en) | 2010-10-06 |
CN1426553A (zh) | 2003-06-25 |
RU2002122402A (ru) | 2004-02-27 |
WO2001053935A1 (en) | 2001-07-26 |
US20040117604A1 (en) | 2004-06-17 |
AU2001229506A1 (en) | 2001-07-31 |
DE60109748T2 (de) | 2006-02-09 |
CN1426553B (zh) | 2011-11-09 |
DE60109748D1 (de) | 2005-05-04 |
DE60143230D1 (de) | 2010-11-18 |
EP1522917A2 (en) | 2005-04-13 |
EP1256054A1 (en) | 2002-11-13 |
EP1522917A3 (en) | 2007-11-28 |
US6671795B1 (en) | 2003-12-30 |
RU2271035C2 (ru) | 2006-02-27 |
EP1256054B1 (en) | 2005-03-30 |
CN102346689A (zh) | 2012-02-08 |
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