CN102340246A - Thick-film magnetic isolation direct current solid-state power controller - Google Patents
Thick-film magnetic isolation direct current solid-state power controller Download PDFInfo
- Publication number
- CN102340246A CN102340246A CN2011102372630A CN201110237263A CN102340246A CN 102340246 A CN102340246 A CN 102340246A CN 2011102372630 A CN2011102372630 A CN 2011102372630A CN 201110237263 A CN201110237263 A CN 201110237263A CN 102340246 A CN102340246 A CN 102340246A
- Authority
- CN
- China
- Prior art keywords
- circuit
- resistance
- output
- triode
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Electronic Switches (AREA)
Abstract
The invention discloses a thick-film magnetic isolation direct current solid-state power controller which comprises a power MOSFET (metal oxide semiconductor field effect transistor), a detection resistor, a power diode, a TVS (transient voltage suppressor) diode, a current conditioning circuit, a voltage detection circuit, a voltage state judgment circuit, a current state judgment circuit, an immediate trip circuit, an inverse time circuit, a short-circuit detection circuit, a driving circuit, a state synthetic circuit, a trip state latch circuit, a time delay reset circuit, a time sequence matching circuit, a DC/DC (direct current/direct current) isolated power supply, a first isolation circuit, a second isolation circuit, a third isolation circuit, a state feedback interface circuit, a control signal interface circuit and a power-on reset circuit. The circuit structure can optimize the electrical properties of the controller, reduce the volume and the weight, improve the reliability and is widely applied to civil low-voltage direct current power distribution systems, aviation, aerospace, tanks, automobiles, ships and other fields.
Description
Technical field
The invention belongs to power electronics and electrical technology field, particularly a kind of DC solid output control device.
Background technology
Solid-state power controller is the intelligent power distribution device that is made up of semiconductor device that produces along with the development of aircraft distribution system; It is the core component and final execution unit of solid-state distribution system; Have switching function and defencive function concurrently, and can accept the control signal of prime computer and report its state information; When overload takes place in load, according to the tripping operation of anti-delay characteristic, protection circuit and load equipment; When load was short-circuited, load fault was cut off in quick acting in the time of tens microseconds; Solid-state power controller has no electric arc, contactless, noiseless, response is fast, electromagnetic interference is little and be convenient to advantage such as computer remote control, but in all extensive uses of occasions such as civilian low-voltage direct distribution system, aviation, tank, spacecraft, automobile, naval vessel.
The circuit of DC solid power controller exists following key technology problems aspect concrete realization and manufacturing process at present:
(1) the soft connection of DC solid power controller and soft shutoff problem
Soft connection and soft turn-off function are absolutely necessary for the DC solid power controller: there is bigger impulse current in capacitive load in opening process; According to varying in size of load capacitance; Impulse current can reach 2-6 doubly, even more than 10 times, may cause tripping operation like this; The impulse current that soft turn-on power loss can suppress DC solid power controller band capacitive load well when opening, thus DC solid power controller band capacitance load capability improved; Owing to exist distributed inductance inevitably in the distribution line, can produce the induction peak voltage that causes because of di/dt at power semiconductor switch pipe two ends during DC solid power controller switching off load in addition, soft turn-off function can address this problem well; The DC solid power controller adopts some integrated circuit chip for driving more in the solution of soft connection and soft shutoff problem at present, and the one, effect is not ideal enough, and the 2nd, the complicated and inconvenient whole circuit of scheme is integrated.
(2) the short-circuit protection problem of DC solid power controller
Load short circuits may produce the thermal stress that has harm as the severeest fault mode, causes solid-state power controller to damage or the tripping operation of higher level's protective device; Therefore solid-state power controller should be able to fast detecting to short trouble and turn-off rapidly, guaranteed output MOSFET safety be connected the load uninterrupted power supply on the same busbar; Mostly the detection method of short-circuit protection is detection power MOSFET voltage at present, and the problem that exists like this is short-circuit protection circuit and soft connection, comparatively complicated when soft breaking circuit combines, and poor anti jamming capability, mistake protection easily.
(3) the protection problem of power semiconductor switch pipe in the DC solid power controller
The power semiconductor switch pipe is one of core devices in the DC solid power controller, and whether can the safety of power semiconductor switch pipe have determined the function of DC solid power controller normally realize; The resist technology of power semiconductor switch pipe is one of key technology of solid-state power controller always in the DC solid power controller; Adopt the method for buffer circuit at present for the protection of power semiconductor switch pipe more; Do like this and only solved some electric stresss in the turn off process; Surge voltage that not possibly not occur in the taking into account system and the influence of load to the power semiconductor switch pipe, do not have yet consideration of power MOSFET in long-term work and transship, the thermal stress during short circuit.
(4) sequence problem of voltage and current state output in the DC solid power controller
The DC solid power controller can be to host computer feedback load voltage and load current state, the operating state that host computer is judged load and solid-state power controller according to the load voltage state and the load current state of switch control command and feedback; Therefore need the load voltage and the load current state of feedback be done synchronous output processing, otherwise possibly cause host computer to do the judgement that makes mistake.
(5) the electrification reset problem of DC solid power controller
The course of work of DC solid power controller is normally given the power supply of control section bias supply earlier, opens shutoff through sending to order to control to control section then; Electrification reset is meant when the SSPC control section is not supplied power, and opens order if sent, and then gives the power supply of SSPC control section bias supply again this moment, and SSPC should not open so; If will make SSPC open-minded, must send earlier and turn-off order, to send out again and open order, existing solid-state power controller does not have this consideration.
(6) isolating problem of DC solid power controller and host computer interface section
For fear of the forceful electric power loop light current control loop is disturbed, send to solid-state power controller at host computer and open when turn-offing control command and DC solid power controller, usually electrical isolation need be provided to the host computer feedback states; Using at present more method is to adopt light-coupled isolation, has that volume is little, response speed fast, easily and logical circuit cooperates, advantage such as easy to use; But the problem that light-coupled isolation exists be power consumption more greatly, shortcoming such as radiation hardness not, limited its use in the space industry space environment.
Summary of the invention
Technical problem to be solved by this invention is to defective and the deficiency pointed out in the aforementioned background art, and a kind of thick film magnetic isolated DC solid-state power controller is provided; But the electric property of its optimal controller; Reduce volume weight, improve reliability, but in all extensive uses of occasions such as civilian low-voltage direct distribution system, aviation, tank, automobile, naval vessel; And the expansion application, be fit to very much the AEROSPACE APPLICATION environment.
The present invention is for solving above technical problem, and the technical scheme that is adopted is:
A kind of thick film magnetic isolated DC solid-state power controller comprises power MOSFET, detects resistance, power diode, TVS diode, current regulating circuit, voltage detecting circuit, voltage status decision circuitry, current status decision circuitry, trip circuit, inverse time lag circuit, short-circuit detecting circuit, drive circuit, state synthetic circuit, tripped condition latch cicuit, time-delay reset circuit, sequential match circuit, DC/DC insulating power supply, first buffer circuit, second buffer circuit, the 3rd buffer circuit, state feedback interface circuit, control signal interface circuit and electrify restoration circuit immediately;
The drain electrode of power MOSFET connects the power input, and source electrode is connected to load via detection resistance and arrives Power Groud then, and the anode of power diode connects Power Groud, and negative electrode connects power take-off; The anode of TVS diode is connected to Power Groud, and negative electrode is connected to the power input;
The input of current regulating circuit is connected the two ends of detecting resistance, and output is connected to inverse time lag trip circuit, trip circuit, short-circuit detecting circuit and current status decision circuitry immediately respectively; The output of voltage detecting circuit connects the voltage status decision circuitry; The output signal of aforesaid voltage status determination circuit and current status decision circuitry is all through output synchronously after the processing of sequential match circuit; Then respectively through being connected to the state feedback interface circuit behind second buffer circuit and the 3rd buffer circuit, the output signal of said state feedback interface circuit promptly is load current status signal and the load voltage status signal that feeds back to host computer to the output signal of sequential match circuit;
The inverse time lag circuit and immediately the output signal of trip circuit be input to the tripped condition latch cicuit; And the output signal of short-circuit detecting circuit also is connected to the tripped condition latch cicuit; The output signal of this tripped condition latch cicuit and the output signal of first buffer circuit are input to the state synthetic circuit jointly; And the output signal of the output signal of state synthetic circuit and short-circuit detecting circuit is input to jointly to have and falls the soft of grid voltage defencive function and open in the soft shutoff drive circuit; This circuit output is connected to the grid source electrode of power MOSFET; The input signal of state synthetic circuit also is connected to time-delay reset circuit as input signal simultaneously, and the output signal of state synthetic circuit then is sent to the sequential match circuit;
Outside control command is connected in the control signal interface circuit through electrify restoration circuit; The output of control signal interface circuit is connected in first buffer circuit; The output signal of first buffer circuit is connected to state synthetic circuit and time-delay reset circuit, and the output of time-delay reset circuit then is connected to the tripped condition latch cicuit;
Electrify restoration circuit, control signal interface circuit, state feedback interface circuit are supplied power by outside 5V bias supply; The DC/DC insulating power supply boosts to 15V with the 5V bias voltage of outside; As internal reference ground, give following functional circuit module power supply with the power MOSFET source electrode: state synthetic circuit, time-delay reset circuit, sequential match circuit, short-circuit detecting circuit, inverse time lag circuit, trip circuit, tripped condition latch cicuit, drive circuit, voltage detecting circuit, voltage status decision circuitry, current status decision circuitry and current regulating circuit immediately.
Above-mentioned drive circuit comprises soft connection and soft breaking circuit and falls the grid voltage short-circuit protection circuit; Wherein, The structure of soft connection and soft breaking circuit is: control signal is connected the base stage of NPN the 5th triode through the three or five resistance; Power supply connects the collector electrode of the 5th triode through the two or eight resistance, and the emitter of the 5th triode with link to each other with reference to ground; The collector electrode of the 5th triode also is connected in the base stage of NPN second, six triodes respectively through the 31, four zero resistances; The second, the emitter of six triodes all with reference to ground links to each other, and the collector electrode of second, six triodes then is connected in power supply through the 27,32 resistance respectively; The two or nine resistance is from the collector electrode of second triode, arrive with reference to ground through the 4th electric capacity, the three or four resistance, three nine-day periods after the winter solstice resistance, and the three or four resistance wherein also forward be parallel with second diode; The node that the two or nine resistance links to each other with the 4th electric capacity is connected in the base stage of NPN first triode and PNP the 3rd triode, and the emitter of first and third triode links to each other, and the collector electrode of first triode is connected to power supply, and the collector electrode of the 3rd triode is connected to reference to ground; One end of the 3rd zero resistance links to each other with the emitter of first and third triode; The other end is connected to the grid of power MOSFET; Grid parallel connection pseudo-ginseng resistance at power MOSFET is connected in parallel on after third and fourth voltage-stabiliser tube differential concatenation between the grid and source electrode of power MOSFET;
Said structure of falling the grid voltage short-circuit protection circuit is: the short-circuit condition signal that short-circuit detecting circuit sends connects the input of first NAND gate; The collector electrode of the 6th triode connects another input of first NAND gate and the negative polarity input that output stage is open-collector first comparator; The output of first NAND gate is connected to an input of second NAND gate, and second, four NAND gates connect to form rest-set flip-flop; The positive polarity input termination reference voltage of first comparator; And be that the positive polarity input of open-collector second comparator links to each other with output stage; The output of first comparator is connected to the negative polarity input point of second comparator; And resistance and the five or two electric capacity are connected to power supply and with reference to ground, the output of second comparator is connected in power supply via the one one two resistance one by one through first respectively; The output of the 4th NAND gate is connected to two inputs of the 3rd NAND gate; And the output of the 3rd NAND gate is received the base stage of NPN the 4th triode through the three or six resistance; The emitter of the 4th triode connects with reference to ground; The collector electrode of the 4th triode is connected to reference to ground through the three or three resistance and the 5th electric capacity, and the anode of first diode is connected in the node that the two or nine resistance links to each other with the 4th electric capacity, and negative electrode is connected in the node that the three or three resistance links to each other with the 5th electric capacity; The two or six resistance connects the negative electrode of the power supply and first diode.
The structure of above-mentioned inverse time lag circuit is: the output of current regulating circuit connects the negative polarity input of the 3rd operational amplifier via the one or four resistance; The the one two, the 1 resistance string joint group becomes voltage divider; The 5V reference voltage is carried out dividing potential drop; The voltage of getting is connected in the positive polarity input of the 3rd operational amplifier through the one or seven resistance; The one or five resistance is connected to the output of the 3rd operational amplifier, and the 3rd electric capacity cross-over connection is in the other end of the one or five resistance and the negative polarity input of the 3rd operational amplifier, and the output of the 3rd comparator is connected in power supply through the one one resistance; The negative polarity input of the 3rd comparator is linked the negative polarity input of open-collector the 4th comparator through low pass filter; Power supply is connected to reference to ground through the 23,25 resistance; The positive polarity input that a bit is connected to the 4th comparator that the 22,25 resistance link to each other; And the output of the output of the 4th comparator and the 3rd comparator links to each other, as inverse time lag circuit and the output of trip circuit immediately.
The structure of above-mentioned sequential match circuit is: five, six, seven, eight comparators all are that output stage is open-collector comparator; The output of state synthetic circuit connects the negative polarity input of the 5th comparator and the positive polarity input of the 7th comparator, and the positive polarity input of the 5th, six, eight comparators links to each other with the negative polarity input of the 7th comparator and is connected to reference voltage; The output of the 5th comparator connects the negative polarity input of the 6th comparator, and connects with reference to ground, connects power supply through the seven or two resistance through the two or three electric capacity; The output of the 7th comparator connects the negative polarity input of the 8th comparator, and connects with reference to ground, connects power supply through the seven or four resistance through the two or four electric capacity; The output of the 6th comparator connects the input of the 5th, six NAND gates, and connects power supply through the seven or three resistance; The output of the 8th comparator connects the input of the 5th, eight NAND gates, and connects power supply through the Seventh Five-Year Plan resistance; The output of the 5th NAND gate connects the input of the 6th, eight NAND gates; And the output of the 6th, eight NAND gates connects the input of the 7th NAND gate; The output of the 7th NAND gate also connects the trigger end of first and second d type flip flop, and the output of the D termination voltage status determination circuit of first d type flip flop, the Q end connects the input of the 3rd buffer circuit; The output of the D termination current status decision circuitry of second d type flip flop, the Q end connects the input of second buffer circuit.
The structure of above-mentioned electrify restoration circuit is: NPN second triode is received in order through the 6th resistance base stage is turn-offed in opening that host computer sends; The emitter of this second triode is connected in the base stage of NPN the 3rd triode; And the base stage of the collector electrode of second and third triode and NPN first triode links to each other; And be connected in the 5V bias supply through second resistance; The emitter of first and third triode is connected in the reference ground of 5V bias supply, and the collector electrode of first triode connects the 5V bias supply through first resistance; The 4th resistance and second capacitances in series, another termination 5V bias supply of the 4th resistance, the reference ground of another termination 5V bias supply of second electric capacity; The reference ground that the D end of 3d flip-flop and clock end are connected in the 5V bias supply; Clear terminal is connected in the collector electrode of first triode; Preset end and be connected in the node that second electric capacity links to each other with the 4th resistance; And
of 3d flip-flop the end be connected in first with the door input; And this first is connected the collector electrode of first triode with another input of door, and its output is the input of connection control signal interface circuit then.
The structure of above-mentioned first buffer circuit is: second with the input of the door respectively output and the high-frequency impulse of connection control signal interface circuit; Output then connects NPN the 9th, the base stage of triode one by one; The collector electrode of the 9th triode connects the 5V bias supply, and the collector electrode of the one one triode connects bias supply with reference to ground; The emitter of the 9th triode links to each other with the emitter of the one one triode; The four or nine resistance and first shunt capacitance composition parallel branch parallel with one another; One end of this parallel branch connects the emitter of the 9th triode; The other end connects the base stage of NPN the tenth triode, and the emitter of the tenth triode is connected in bias supply with reference to ground; The input of the same name of pulse transformer links to each other with the 5V bias supply, and the different name input links to each other with the collector electrode of the tenth triode; The anode of voltage-stabiliser tube links to each other with the 5V bias supply, and negative electrode links to each other with the negative electrode of the 6th diode, and the anode of the 6th diode is connected in the different name input of pulse transformer; The output of the same name of pulse transformer connects the anode of the 5th diode; And the negative electrode of the 5th diode connects internal reference ground through first parallel resistance; The negative electrode of said the 5th diode also connects internal reference ground through second shunt capacitance; The negative electrode of the 5th diode is connected in the base stage of NPN the 8th triode simultaneously through the four or four resistance, the collector electrode of the 8th triode is connected in the base stage of NPN the 7th triode, and is connected in internal electric source through the four or five resistance; Seven, the emitter of eight triodes is connected in internal reference ground, and the collector electrode of the 7th triode is connected in internal electric source through the four or two resistance.
After adopting such scheme, thick-film technique magnetic isolated DC solid-state power controller provided by the present invention has the following advantages:
(1) soft connection technology has effectively suppressed the impulse current in the solid-state power controller band capacitive load opening process, has improved the ability of band capacitive load;
(2) soft shutoff technology and effectively suppressed the peak voltage in the inductive load turn off process, the safety of guaranteed output MOSFET with the antiparallel power diode of load;
(3) the TVS diode surge voltage that suppressed effectively to exist in the system is to the impact of power MOSFET, the safety of guaranteed output MOSFET;
(4) the simple realization and more accurate easily of inverse time lag circuit, the protection curve can be according to passing through to change the adjustment of component parameters needs;
(5) have the soft connection, the soft breaking circuit that fall the grid voltage short-circuit protection and realized the rapid and reliable short-circuit protection;
(6) realized that state feedback exports synchronously, made host computer can not make erroneous judgement the state of solid-state power controller and load;
(7) partly adopt the magnetic isolation technology at the solid-state power controller external interface, reduced power consumption, simultaneously can radiation hardness, expanded the application scenario of solid-state power controller, be fit to very much the applied environment of space flight;
(8) electrify restoration circuit is that the system applies of solid-state power controller provides flexibility;
(9) be applicable to that the thick-film technique of solid-state power controller and wiring technique have reduced volume and weight greatly, have improved reliability.
Description of drawings
Fig. 1 is a theory diagram of the present invention;
Fig. 2 (a) is the circuit structure of the pure resistive load of band of the present invention;
Fig. 2 (b) is the oscillogram of Fig. 2 (a) when normally opening shutoff;
Fig. 3 (a) is the circuit structure of band capacitance-resistance property of the present invention load;
Fig. 3 (b) is the oscillogram of Fig. 3 (a) when normally opening shutoff;
Fig. 4 (a) is the circuit structure of band resistance sense property of the present invention load;
Fig. 4 (b) is the oscillogram of Fig. 4 (a) when normally opening shutoff;
Fig. 5 is that the present invention has the soft connection of falling the grid voltage short-circuit protection function and the drive circuit figure of soft shutoff;
Fig. 6 is the oscillogram of failed because after load is normally opened among Fig. 2 (a);
Fig. 7 is the typical inverse time protection curve of DC solid power controller;
Fig. 8 is the circuit diagram of inverse time lag circuit among the present invention;
Fig. 9 (a) is the circuit diagram of sequential match circuit among the present invention;
Fig. 9 (b) is the working waveform figure of Fig. 9 (a);
Figure 10 is the circuit diagram of electrify restoration circuit among the present invention;
Figure 11 is the sequential sketch map of Figure 10;
Figure 12 is the theory diagram of first buffer circuit among the present invention;
Figure 13 is the circuit diagram of first buffer circuit among the present invention;
Figure 14 is the working waveform figure of Figure 13.
Embodiment
At first with reference to shown in Figure 1; The present invention provides a kind of thick film magnetic isolated DC solid-state power controller; Comprise power MOSFET, detect resistance, power diode, TVS diode, current regulating circuit, voltage detecting circuit, voltage status decision circuitry, current status decision circuitry, trip circuit, inverse time lag circuit, short-circuit detecting circuit, drive circuit, state synthetic circuit, tripped condition latch cicuit, time-delay reset circuit, sequential match circuit, DC/DC insulating power supply, first buffer circuit, second buffer circuit, the 3rd buffer circuit, state feedback interface circuit, control signal interface circuit and electrify restoration circuit immediately, below put up with its annexation and course of work separately and describe.
DC power supply power input process power MOSFET and current detection circuit are connected to load and arrive Power Groud then, and the lower end of current detection circuit is a power take-off; The anode of power diode is connected to Power Groud, and negative electrode is connected to power take-off; The anode of TVS diode is connected to Power Groud, and negative electrode is connected to the power input.
Adopt detecting resistance is converted into voltage with the electric current of solid-state power controller and detects; Described detection resistance is connected between power MOSFET and the power diode; The current regulating circuit is used for the voltage that detects resistance is amplified and lifts pressure, and carries out filtering and eliminate and disturb.
The output of current regulating circuit is connected to inverse time lag trip circuit, trip circuit, short-circuit detecting circuit and current status decision circuitry immediately respectively; The output of load voltage testing circuit connects the voltage status decision circuitry; The output signal of aforesaid voltage status determination circuit and current status decision circuitry is all through output synchronously after the processing of sequential match circuit; The output signal of sequential match circuit then is connected to the state feedback interface circuit through second buffer circuit and the 3rd buffer circuit respectively, and the output signal of said state feedback interface circuit promptly is load current status signal and the load voltage status signal that feeds back to host computer.
Connect aforementioned; The inverse time lag circuit and immediately the output signal TRIP of trip circuit be input to the tripped condition latch cicuit; And the output signal SHORT of short-circuit detecting circuit also is connected to the tripped condition latch cicuit; The output signal CMD2 of the output signal FAULT of this tripped condition latch cicuit and first buffer circuit is input to the state synthetic circuit jointly; And the output signal SHORT of the output signal CMD3 of state synthetic circuit and short-circuit detecting circuit is input to jointly to have and falls the soft of grid voltage defencive function and open in the soft shutoff drive circuit; This circuit output is connected to the grid source electrode of power MOSFET, and the input signal CMD2 of state synthetic circuit also is connected to time-delay reset circuit as input signal simultaneously, and the output signal CMD3 of state synthetic circuit then is sent to the sequential match circuit.
Outside control command CMD is connected in the control signal interface circuit through electrify restoration circuit; The output of control signal interface circuit is connected in first buffer circuit; The output signal CMD2 of first buffer circuit is connected to state synthetic circuit and time-delay reset circuit, and the output of time-delay reset circuit then connects the tripped condition latch cicuit.
Electrify restoration circuit, control signal interface circuit, state feedback interface circuit are supplied power by outside 5V bias supply; The DC/DC insulating power supply boosts to 15V with the 5V bias voltage of outside; As internal reference ground, give following functional circuit module power supply with the power MOSFET source electrode: state synthetic circuit, time-delay reset circuit, sequential match circuit, short-circuit detecting circuit, inverse time lag circuit, trip circuit, tripped condition latch cicuit, drive circuit, voltage status decision circuitry, current status decision circuitry, current regulating circuit, voltage detecting circuit immediately.
Cooperate shown in Figure 1ly again, when the present invention works, send control command CMD, handle turning on and off of back control Driver Circuit driving power MOSFET control load through internal logic by host computer; Power is input as the direct current Bus Voltage, and power output connects load and returned by Power Groud; Adopt to detect the resistance sampling load current in the loop of power circuit, to the signal of sampling through the amplification of current regulating circuit, lift press and filtering after, with the inverse time lag circuit and immediately the benchmark of trip circuit and short-circuit detecting circuit compare and delay time; Inverse time lag circuit and the output of trip circuit are immediately latched tripped condition through behind the tripped condition latch cicuit, and to carry out state comprehensive with the CMD2 signal that sends from front end; When inverse time lag circuit and trip circuit action immediately, through the soft switching off load of drive circuit; When load short circuits took place, short-circuit detecting circuit can detect, and drive circuit receives the signal of aforementioned short-circuit detecting circuit and latchs short-circuit condition, through falling the rapid switch-off power MOSFET of grid voltage circuit in the drive circuit; The result of voltage, current status decision circuitry is sent in the state feedback interface circuit through sequential match circuit and second and third buffer circuit respectively, accomplishes the state feedback to host computer.
Introduce some key technologies involved in the present invention below in detail, to support the claim part.
1. the main power topological structure of DC solid power controller: promptly direct voltage through the power input to power MOSFET, detect resistance and arrive Power Groud again to load, load two ends inverse parallel power diode, power import and Power Groud between parallelly connected TVS diode; When power MOSFET was in off state, the power input voltage almost completely was added in the power MOSFET two ends, and the TVS diode can be limited in certain limit with it when power input overvoltage, therefore can effectively protect power switch pipe.
Fig. 2 (a) has provided the circuit structure under the pure resistive load of band of the present invention, comes opening or turn-offing of control load, load voltage V through power controlling MOSFET
LoadAnd load current (is the electric current I of SSPC at this moment
SSPC) change synchronously, provided waveform correlation among Fig. 2 (b).
Fig. 3 (a) has provided the circuit structure under the band capacitance-resistance property of the present invention load, and when solid-state power controller was opened, the supply voltage of power input will charge to load capacitance, therefore can in opening process, have impulse current; Electric capacity was the equal of open circuit after stable state was opened, and the voltage on the electric capacity deducts the voltage drop of solid-state power controller for the power input terminal voltage; When solid-state power controller turn-offed, the energy of storing on the electric capacity was released through load resistance, and Fig. 3 (b) has provided waveform correlation.
Fig. 4 (a) has provided the circuit structure under the band resistance sense property of the present invention load, when solid-state power controller is opened, owing to be connected in series inductance in the load, so the rising of load current will lag behind the rising of load voltage; The decline of load current also is the decline that lags behind load voltage during shutoff; Therefore after load voltage drops to zero within a certain period of time; Because load current does not drop to zero, must from the antiparallel power diode D1 of load afterflow, decay to zero until inductive current; Fig. 4 (b) has provided waveform correlation; The power diode D1 of afterflow has reduced the voltage stress of power MOSFET when turn-offing effectively, has protected the safety of power MOSFET.
2. have the soft connection of falling the grid voltage short-circuit protection function, soft shutoff drive circuit
Have the soft connection of falling the grid voltage short-circuit protection function and soft shutoff drive circuit as a reference, be designated as FGND, form by two parts with the source electrode of power MOSFET: the one, soft connection and soft breaking circuit, the 2nd, the grid voltage short-circuit protection circuit falls.Concrete composition is as shown in Figure 5, and narration is as follows respectively:
The structure of soft connection and soft breaking circuit is: control signal CMD3 is connected in the base stage of NPN triode T5 through resistance R 35, and power Vcc (15V) is connected in the collector electrode of triode T5 through resistance R 28, and the emitter of triode T5 with link to each other with reference to ground FGND; The collector electrode of triode T5 also is connected in the base stage of NPN triode T2 and T6 respectively through resistance R 31 and R40, the emitter of triode T2 and T6 links to each other with reference ground FGND, and the collector electrode of triode T2 and T6 then is connected in power Vcc through resistance R 27 with R32 respectively; Resistance R 29 is from the collector electrode of triode T2, arrive with reference to ground FGND through capacitor C 4, resistance R 34, resistance R 39, and resistance R wherein 34 gone back forward and is parallel with diode D2; The node DRIVE0 that resistance R 29 links to each other with capacitor C 4 is connected in the base stage of NPN triode T1 and PNP triode T3, and the emitter of triode T1 and T3 links to each other, and the collector electrode of triode T1 is connected to power Vcc, and the collector electrode of triode T3 is connected to reference to ground FGND; One end of resistance R 30 links to each other with the emitter of triode T1, T3, and the other end is connected to the grid of MOSFET, and the grid parallel resistance R37 at MOSFET is connected in parallel between MOSFET grid and the source electrode after voltage-stabiliser tube Z3 and the Z4 differential concatenation.
The structure of falling the grid voltage short-circuit protection circuit is: U5A, U5B, U5C and U5D right and wrong door, U111A and U111B are that output stage is open-collector comparator; The SHORT signal is the short-circuit condition signal that short-circuit detecting circuit sends; Be connected in the input of NAND gate U5A; The collector electrode of triode T6 connects another input of NAND gate U5A and the negative polarity input of U111A; The output of U5A is connected to the input of U5B, and U5B and U5D connect into the form of rest-set flip-flop; The positive polarity input termination reference voltage HalfREF (7.5V) of U111A; And link to each other with the positive polarity input of U111B; The output of U111A is connected to the negative polarity input point of U111B; And be connected to power Vcc and reference ground FGND through resistance R 111 and capacitor C 52 respectively, the output of U111B is connected in power Vcc via resistance R 112; The output SHORTED of U5D is connected to two inputs of U5C; The output of U5C is received the base stage of NPN triode T4 through resistance R 36; The emitter of T4 connects with reference to ground FGND; The collector electrode of T4 is connected to reference to ground FGND through resistance R 33 and capacitor C 5, and the anode of diode D1 is connected in DRIVE0, and negative electrode is connected in the node that R33 links to each other with C5; R26 connects the negative electrode of power Vcc and diode D1.
Narration has the soft connection of falling the grid voltage short-circuit protection function, the operation principle of soft shutoff drive circuit below:
(1) soft connection process:
Short-circuit protection circuit and inoperative in normal soft connection and the soft turn off process: the SHORT signal is that low level is represented not to be short-circuited; When not being short-circuited; The output SHORTED of NAND gate U5D is a high level, and NAND gate U5C is output as low level, and triode T4 is in off state; The voltage of capacitor C 5 equals power source voltage Vcc, and diode D1 is in cut-off state.
The soft thought of opening is that the grid voltage of control MOSFET slowly rises, and reaches the purpose of restriction capacitive load impulse current; When CMD3 becomes high level by low level; Triode T5 saturation conduction; Triode T2 turn-offs; Power Vcc gives capacitor C 4 chargings through R34, the resistance R 39 of resistance R 27, R29, diode D2 and parallel connection thereof, and the DRIVE0 current potential rises gradually, through totem output stage and the resistance R 30 rear drive power MOSFETs of being made up of triode T1 and T3.
(2) soft turn off process:
The thought of soft shutoff is that the grid voltage of control MOSFET slowly descends, and reaches the purpose that reduces the power MOSFET voltage stress; When CMD3 becomes low level by high level; Triode T5 turn-offs; Triode T2 saturation conduction, capacitor C 4 is through the collector electrode discharge of resistance R 29 and triode T2, and the DRIVE0 current potential descends gradually; Through totem output stage and the resistance R 30 rear drive power MOSFETs of being made up of triode T1 and T3, the DRIVE1 current potential drops to the power MOSFET of back below the cut-in voltage and turn-offs.
(3) short-circuit protection process:
When load was short-circuited, short-circuit detecting circuit can detect load current: if load current greater than set point (12 times of rated current), SHORT becomes high level; The tripped condition latch cicuit can latch short-circuit condition simultaneously, makes the FAULT signal remain low level, and the action of state synthetic circuit makes that the CMD3 signal is a low level; The rest-set flip-flop that NAND gate U5B and U5D constitute also latchs short-circuit condition; The SHORTED signal keeps low level always before short-circuit condition resets, triode T4 keeps conducting, and the DRIVE0 current potential descends rapidly; The DRIVE1 current potential also descends rapidly, thereby lets power MOSFET turn-off.When CMD3 becomes low level; Triode T6 saturation conduction, its collector electrode becomes low level, and the delay circuit that U111A and U111B form is with low level time-delay a period of time output of T6 collector electrode; And to make the SHORTED signal be high level; This moment, short-circuit protection was accomplished, and power MOSFET turn-offs, and waveform correlation is as shown in Figure 6.
3. inverse time lag circuit and trip circuit immediately
The equation or the curve representation of common working load electric current of the inverse-time overcurrent protection characteristic of DC solid power controller and tripping operation delay time; Shown in Figure 7ly be typical inverse time protection curve of the present invention: when load current during less than doubly rated current of 1.15-1.45, solid-state power controller keeps conducting state; When load current greater than 1.15-1.45 during doubly and less than 8-12 times of rated current, square being inversely proportional to of tripping operation delay time and electric current; When load current during greater than 8-12 times, solid-state power controller trips immediately.
Fig. 8 has provided the inverse time lag circuit diagram; The voltage of LCS is the output of current regulating circuit, and LCS is via the negative polarity input of resistance R 14 concatenation operation amplifier U3C, and REF5 is the reference voltage of 5V; Resistance R 12 is formed voltage divider with R19; The voltage of getting is connected in the positive polarity input of operational amplifier U3C through resistance R 17, and resistance R 15 is connected to the output of U3C, and capacitor C 3 cross-over connections are in the other end (being that output stage is the positive polarity input of open-collector comparator U1C) of R15 and the negative polarity input of U3C; The negative polarity input of comparator U1C is LCS, and output is connected in power Vcc through resistance R 11; LCS links the negative polarity input of open-collector comparator U1D simultaneously through the low pass filter that is made up of resistance R _ f s1 and capacitor C fst1; Power Vcc is connected to reference to ground FGND through resistance R 23 and resistance R 25; The positive polarity input that a bit is connected to U1D that R23 links to each other with R25; The output of U1D and the output of U1C are connected in TRIP, as inverse time lag circuit and the output of trip circuit immediately.
The narration inverse time lag circuit and the operation principle of trip circuit below immediately:
(1) when overload not taking place; The voltage that the LCS point voltage sets greater than the voltage divider of being made up of R12 and R19, operational amplifier U3C are as the comparator operate in open loop state, and output is near the magnitude of voltage of power source voltage Vcc; Greater than the voltage of U1C negative polarity input LCS, U1C exports high level; And because U1D also can export high level this moment, so TRIP is output as high level;
(2) when overload takes place but does not reach immediately trip protection point in load; The voltage that the LCS point voltage sets greater than the voltage divider of being made up of R12 and R19; U3C is as integrator work, and U1C becomes low level through output TRIP after the time of delay corresponding with overload magnification; When TRIP was low level, the tripped condition latch cicuit was at once with the TRIP state latch, and state synthetic circuit output low level is through the soft shutoff solid-state power controller of drive circuit;
(3) when the overload magnification of load reaches trip-point immediately (trip-point forms voltage divider setting) immediately by resistance R 23 and resistance R 25; The output signal TRIP of comparator U1D becomes low level and produces trip signal; State synthetic circuit output low level is through the soft shutoff solid-state power controller of drive circuit.
4. sequential match circuit
Solid-state power controller must provide two state informations to host computer, and one is load current state (STATE1), and another is load voltage state (STATE2); STATE1 is judged by current regulating circuit and current status after sequential match circuit and the output of state feedback interface circuit; STATE2 is detected by load voltage and the load voltage state is judged after sequential match circuit and the output of state feedback interface circuit.
Sequential match circuit concrete structure is shown in Fig. 9 (a); Input signal has 3: CMD3, LOAD0 and MOS0; Wherein CMD3 is external control signal CMD and latchs the comprehensive later signal of inner tripped condition FAULT state; LOAD0 is the output of load current status determination circuit, and MOS0 is the output of load voltage status determination circuit; The output signal has 2: LOAD1 and MOS1; U2A, U2B, U2C and U2D are that output stage is open-collector comparator, and U8A, U8B, U8C and U8D are NAND gate, and U22A and U22B are d type flip flops.CMD3 is connected in the negative polarity input of U2A and the positive polarity input of U2C, and the positive polarity input of U2A, U2B and U2D links to each other with the negative polarity input of U2C and is connected to reference voltage HalfREF (7.5V); The output of U2A is connected to the negative polarity input of U2B, and connects with reference to ground FGND, connects power Vcc through resistance R 72 through capacitor C 23; The output of U2C connects the negative polarity input of U2D, and connects with reference to ground FGND, connects power Vcc through resistance R 74 through capacitor C 24; The output of U2B connects the input of U8A and U8B, and connects power Vcc through resistance R 73; The output of U2D connects the input of U8A and U8D, and connects power Vcc through resistance R 75; The output of NAND gate U8A connects the input of U8B and U8D; The output of U8B and U8D is connected two inputs of U8C; The output signal CLK of U8C is as the trigger end CLK of U22A and U22B, the D termination MOS0 of U22A, the D termination LOAD0 of U22B; The Q end output signal of U22A is MOS1, and the Q end output signal of U22B is LOAD1.
When CMD3 signal generation saltus step; No matter because external control order CMD or load tripping operation or short circuit cause that the circuit of being made up of U2A, U2B, U2C and U2D and U8A, U8B, U8C and the U8D rising edge CLK of generation that can delay time can cooperate shown in Fig. 9 (b) simultaneously; This rising edge CLK triggers U22A and U22B; Just can make the output (Q end) of U22A and U22B, the value of MOS1 is refreshed to be that MOS0, the value of LOAD1 are refreshed and to be LOAD0; And this process is simultaneously, has promptly accomplished the synchronous output of state feedback.
5. electrify restoration circuit
Figure 10 is the electrify restoration circuit among the present invention, and CMD is that opening of sending of host computer turn-offed order, receives the base stage of NPN triode T02 through resistance R 06; The emitter of T02 is connected in the base stage of NPN triode T03; The base stage of the collector electrode of T02 and T03 and NPN triode T01 links to each other, and is connected in the 5V bias supply through resistance R 02, and the emitter of T01 and T03 is connected in the reference ground of 5V bias supply; The T01 collector electrode connects the 5V bias supply through resistance R 01; Resistance R 04 and capacitor C 02 series connection, another termination 5V bias supply of resistance R 04, the reference ground of another termination 5V bias supply of capacitor C 02; U14 is for to have the d type flip flop that presets end (PRE) and clear terminal (CLR), and low level is effective; The reference ground that the D end of U14 and clock end (CLK) are connected in the 5V bias supply, clock end is connected in the collector electrode of T01, presets end and is connected in the node that C02 links to each other with R04;
end of U14 is connected in the input with door U20B; Another input of U20B is connected in the collector electrode of T01, and U20B is output as CMD1.
Narrate the operation principle of electrify restoration circuit below:
(1) capacitor C 02 composes in series differential circuit with resistance R 04 among Figure 10; When the 5V bias supply powers on; The end that presets of d type flip flop U14 remains low level; Capacitor C 02 charging makes that presetting terminal voltage slowly rises to high level then, and the low level pulse that utilizes the initial time that powers on to preset end is accomplished electrification reset;
(2) cooperation is shown in Figure 11; When initial moment cmd signal is a low level or unsettled; If this moment, power supply powered on; The clear terminal of d type flip flop U14 is a low level; The output of
end is high level always; The output of the electrification reset low level pulse that presets end can not influence
end, this moment, to make CMD be high level, can obtain CMD1 and CMD is consistent;
(3) when initial moment cmd signal be high level; If this moment, bias supply powered on; The clear terminal of U14 is a high level; The low level pulse that presets end can be held
and be changed to low level; Although this moment, CMD was a high level; But because
end is for low level, so CMD1 is a low level; Have only and earlier cmd signal is changed to low level; The clear terminal of U14 is put low;
end is high level, and making CMD again is that height just can make CMD1 and CMD be consistent.
6. magnetic buffer circuit
The present invention has used the method for magnetic isolation at host computer during with state feedback to solid-state power controller transmit button order; Shown in figure 12 is the theory diagram of first buffer circuit; The CMD1 signal is carried out high frequency modulated; Be delivered to the transformer secondary through pulse transformer, shaping is reduced into the switching signal before modulating again after the secondary demodulation.Figure 13 is for realizing that circuit: CMD1 was for handling later switching signal through electrify restoration circuit; PULSE1 is high frequency (150KHz-250KHz) pulse; CMD1 and PULSE1 link the input with door U20C; The output of U20C is connected in the base stage of NPN triode T9 and PNP triode T11, and the collector electrode of T9 connects the 5V bias supply, and the collector electrode of T11 connects bias supply with reference to ground; The emitter of T9 links to each other with the emitter of T11, and is connected in the base stage of NPN triode T10 through parallel resistor R49 and capacitor C ft3, and the emitter of T10 is connected in bias supply with reference to ground; The input of the same name of pulse transformer TF1 (1 end) links to each other with the 5V bias supply, and different name input (2 end) links to each other with the T10 collector electrode; The anode of voltage-stabiliser tube Z5 links to each other with the 5V bias supply, and negative electrode links to each other with diode D6 negative electrode, and the D6 anode is connected in 2 ends of TF1; The output of the same name of TF1 (4 end) is connected in the anode of diode D5; The negative electrode of D5 meets internal reference ground FGND through parallel resistor Rf1 and Cf1; The negative electrode of D5 is connected in the base stage of NPN triode T8 simultaneously through resistance R 44; The collector electrode of T8 is connected in the base stage of NPN triode T7, and is connected in internal electric source Vcc through resistance R 45; The emitter of T7 and T8 is connected in internal reference ground FGND, and the collector electrode CMD2 of T7 is connected in internal electric source Vcc through resistance R 42.
Narrate this circuit working principle below:
When CMD1 was high level, the output of U20C was high-frequency pulse signal, through the drive circuit rear drive triode T10 high frequency break-make of being made up of triode T9, T11 and capacitor C ft3 and R49; During triode T10 conducting, the voltage that is added in the former limit of transformer equals bias supply voltage (5V); When triode T10 turn-offed, the voltage that is added in the transformer secondary was negative value, and the pressure drop that equals diode D1 adds the reverse breakdown voltage value of voltage-stabiliser tube Z5; So obtained that at the transformer secondary negative high-frequency impulse is just arranged; The direct voltage that must pulse through diode D5 and capacitor C f1 halfwave rectifier; Rf1 is a dummy resistance, and T7 and T8 and R42 and R45 form shaping circuit, the direct voltage of pulsing is become stable high level open signal.
When CMD1 was low level, the output of U20 was always low level, and triode T10 turn-offs always, and the voltage of the former secondary of transformer is zero always, so the voltage of capacitor C f1 also is zero, T8 is in off state, and T7 saturation conduction, CMD2 are low level.
Waveform correlation is shown in figure 14.
7. be applicable to the thick-film technique and the wiring technique of solid-state power controller
The present invention adopts polylaminate wiring technique, on alumina substrate, makes resistance and electric capacity with thick-film techniques such as silk screen printing and sintering, and the precision of resistance can reach 60%, can reach 5% after advancing laser resistor trimming, and temperature coefficient reaches 10
-4/ ℃, and assemble power MOSFET bare chip, discrete device and integrated circuit bare chip above that; The better beryllium oxide ceramics of employing heat conductivility below power MOSFET, and power MOSFET is installed in the place near shell edge, is beneficial to heat radiation; The conduction band that flows through the loop of power circuit part of big electric current is tried one's best slightly, lacks and near pin, to reduce conduction band resistance, is reduced the wastage; Entire circuit adds the encapsulation of 10# cold-rolled steel metal-back, and pours nitrogen, has reduced the volume and weight of solid-state power controller greatly, has increased reliability.
Above embodiment is merely explanation technological thought of the present invention, can not limit protection scope of the present invention with this, every technological thought that proposes according to the present invention, and any change of on the technical scheme basis, being done all falls within the protection range of the present invention.
Claims (6)
1. thick film magnetic isolated DC solid-state power controller is characterized in that: comprise power MOSFET, detect resistance, power diode, TVS diode, current regulating circuit, voltage detecting circuit, voltage status decision circuitry, current status decision circuitry, trip circuit, inverse time lag circuit, short-circuit detecting circuit, drive circuit, state synthetic circuit, tripped condition latch cicuit, time-delay reset circuit, sequential match circuit, DC/DC insulating power supply, first buffer circuit, second buffer circuit, the 3rd buffer circuit, state feedback interface circuit, control signal interface circuit and electrify restoration circuit immediately;
The drain electrode of power MOSFET connects the power input, and source electrode is connected to load through detection resistance and arrives Power Groud then, and the anode of power diode connects Power Groud, and negative electrode connects power take-off; The anode of TVS diode is connected to Power Groud, and negative electrode is connected to the power input;
The input of current regulating circuit is connected the two ends of detecting resistance, and output is connected to inverse time lag trip circuit, trip circuit, short-circuit detecting circuit and current status decision circuitry immediately respectively; The output of voltage detecting circuit connects the voltage status decision circuitry; The output signal of aforesaid voltage status determination circuit and current status decision circuitry is all through output synchronously after the processing of sequential match circuit; The output signal of sequential match circuit then is connected to the state feedback interface circuit through second buffer circuit and the 3rd buffer circuit respectively, and the output signal of said state feedback interface circuit promptly is load current status signal and the load voltage status signal that feeds back to host computer;
The inverse time lag circuit and immediately the output signal of trip circuit be input to the tripped condition latch cicuit; And the output signal of short-circuit detecting circuit also is connected to the tripped condition latch cicuit; The output signal of this tripped condition latch cicuit and the output signal of first buffer circuit are input to the state synthetic circuit jointly; And the output signal of the output signal of state synthetic circuit and short-circuit detecting circuit is input to jointly to have and falls the soft of grid voltage defencive function and open in the soft shutoff drive circuit; This circuit output is connected to the grid source electrode of power MOSFET; The input signal of state synthetic circuit also is connected to time-delay reset circuit as input signal simultaneously, and the output signal of state synthetic circuit then is sent to the sequential match circuit;
Outside control command is connected in the control signal interface circuit through electrify restoration circuit; The output of control signal interface circuit is connected in first buffer circuit; The output signal of first buffer circuit is connected to state synthetic circuit and time-delay reset circuit, and the output of time-delay reset circuit then connects the tripped condition latch cicuit;
Electrify restoration circuit, control signal interface circuit, state feedback interface circuit are supplied power by outside 5V bias supply; The DC/DC insulating power supply boosts to 15V with the 5V bias voltage of outside; As internal reference ground, give following functional circuit module power supply with the power MOSFET source electrode: state synthetic circuit, time-delay reset circuit, sequential match circuit, short-circuit detecting circuit, inverse time lag circuit, trip circuit, tripped condition latch cicuit, drive circuit, voltage status decision circuitry, current status decision circuitry, voltage detecting circuit and current regulating circuit immediately.
2. thick film magnetic isolated DC solid-state power controller as claimed in claim 1; It is characterized in that: said drive circuit comprises soft connection and soft breaking circuit and falls the grid voltage short-circuit protection circuit; Wherein, The structure of soft connection and soft breaking circuit is: control signal is connected the base stage of NPN the 5th triode through the three or five resistance, and power supply connects the collector electrode of the 5th triode through the two or eight resistance, and the emitter of the 5th triode with link to each other with reference to ground; The collector electrode of the 5th triode also is connected in the base stage of NPN second, six triodes respectively through the 31, four zero resistances; The second, the emitter of six triodes all with reference to ground links to each other, and the collector electrode of second, six triodes then is connected in power supply through the 27,32 resistance respectively; The two or nine resistance is from the collector electrode of second triode, arrive with reference to ground through the 4th electric capacity, the three or four resistance, three nine-day periods after the winter solstice resistance, and the three or four resistance wherein also forward be parallel with second diode; The node that the two or nine resistance links to each other with the 4th electric capacity is connected in the base stage of NPN first triode and PNP the 3rd triode, and the emitter of first and third triode links to each other, and the collector electrode of first triode is connected to power supply, and the collector electrode of the 3rd triode is connected to reference to ground; One end of the 3rd zero resistance links to each other with the emitter of first and third triode; The other end is connected to the grid of power MOSFET; Grid parallel connection pseudo-ginseng resistance at power MOSFET is connected in parallel on after third and fourth voltage-stabiliser tube differential concatenation between the grid and source electrode of power MOSFET;
Said structure of falling the grid voltage short-circuit protection circuit is: the short-circuit condition signal that short-circuit detecting circuit sends connects the input of first NAND gate; The collector electrode of the 6th triode connects another input of first NAND gate and the negative polarity input that output stage is open-collector first comparator; The output of first NAND gate is connected to an input of second NAND gate, and second, four NAND gates connect to form rest-set flip-flop; The positive polarity input termination reference voltage of first comparator; And be that the positive polarity input of open-collector second comparator links to each other with output stage; The output of first comparator is connected to the negative polarity input point of second comparator; And resistance and the five or two electric capacity are connected to power supply and with reference to ground, the output of second comparator is connected in power supply via the one one two resistance one by one through first respectively; The output of the 4th NAND gate is connected to two inputs of the 3rd NAND gate; And the output of the 3rd NAND gate is received the base stage of NPN the 4th triode through the three or six resistance; The emitter of the 4th triode connects with reference to ground; The collector electrode of the 4th triode is connected to reference to ground through the three or three resistance and the 5th electric capacity, and the anode of first diode is connected in the node that the two or nine resistance links to each other with the 4th electric capacity, and negative electrode is connected in the node that the three or three resistance links to each other with the 5th electric capacity; The two or six resistance connects the negative electrode of the power supply and first diode.
3. according to claim 1 or claim 2 thick film magnetic isolated DC solid-state power controller; The structure that it is characterized in that said inverse time lag circuit is: the output of current regulating circuit connects the negative polarity input of the 3rd operational amplifier and the negative polarity input of open-collector the 3rd comparator via the one or four resistance; The the one two, the 1 resistance string joint group becomes voltage divider; The 5V reference voltage is carried out dividing potential drop; The voltage of getting is connected in the positive polarity input of the 3rd operational amplifier through the one or seven resistance; The output of the 3rd operational amplifier is connected in the positive polarity input of the 3rd comparator through the one or five resistance, and the 3rd electric capacity cross-over connection is in the positive polarity input of the 3rd comparator and the negative polarity input of the 3rd operational amplifier, and the output of the 3rd comparator is connected in power supply through the one one resistance; The negative polarity input of open-collector the 4th comparator is linked in the output of current regulating circuit through low pass filter; Power supply is connected to reference to ground through the 23,25 resistance; The positive polarity input that a bit is connected to the 4th comparator that the 23,25 resistance link to each other; And the output of the output of the 4th comparator and the 3rd comparator links to each other, as inverse time lag circuit and the output of trip circuit immediately.
4. like claim 1,2 or 3 described thick film magnetic isolated DC solid-state power controllers; The structure that it is characterized in that said sequential match circuit is: five, six, seven, eight comparators all are that output stage is open-collector comparator; The output of state synthetic circuit connects the negative polarity input of the 5th comparator and the positive polarity input of the 7th comparator, and the positive polarity input of the 5th, six, eight comparators links to each other with the negative polarity input of the 7th comparator and is connected to reference voltage; The output of the 5th comparator connects the negative polarity input of the 6th comparator, and connects with reference to ground, connects power supply through the seven or two resistance through the two or three electric capacity; The output of the 7th comparator connects the negative polarity input of the 8th comparator, and connects with reference to ground, connects power supply through the seven or four resistance through the two or four electric capacity; The output of the 6th comparator connects the input of the 5th, six NAND gates, and connects power supply through the seven or three resistance; The output of the 8th comparator connects the input of the 5th, eight NAND gates, and connects power supply through the Seventh Five-Year Plan resistance; The output of the 5th NAND gate connects the input of the 6th, eight NAND gates; And the output of the 6th, eight NAND gates connects the input of the 7th NAND gate; The output of the 7th NAND gate also connects the trigger end of first and second d type flip flop, and the output of the D termination voltage status determination circuit of first d type flip flop, the Q end connects the input of the 3rd buffer circuit; The output of the D termination current status decision circuitry of second d type flip flop, the Q end connects the input of second buffer circuit.
5. like claim 1,2,3 or 4 described thick film magnetic isolated DC solid-state power controllers; The structure that it is characterized in that said electrify restoration circuit is: NPN second triode is received in order through the 6th resistance base stage is turn-offed in opening that host computer sends; The emitter of this second triode is connected in the base stage of NPN the 3rd triode; And the base stage of the collector electrode of second and third triode and NPN first triode links to each other; And be connected in the 5V bias supply through second resistance, and the emitter of first and third triode is connected in the reference ground of 5V bias supply, and the collector electrode of first triode connects the 5V bias supply through first resistance; The 4th resistance and second capacitances in series, another termination 5V bias supply of the 4th resistance, the reference ground of another termination 5V bias supply of second electric capacity; The 3rd D
The reference ground that the D end of trigger and clock end are connected in the 5V bias supply; Clear terminal is connected in the collector electrode of first triode; Preset end and be connected in the node that second electric capacity links to each other with the 4th resistance; And
of 3d flip-flop the end be connected in first with the door input; And this first is connected the collector electrode of first triode with another input of door, and its output is the input of connection control signal interface circuit then.
6. like any described thick film magnetic isolated DC solid-state power controller in the claim 1 to 5; The structure that it is characterized in that said first buffer circuit is: second with the input of the door respectively output and the high-frequency impulse of connection control signal interface circuit; Output then connects the base stage of NPN the 9th triode and PNP the one one triode; The collector electrode of the 9th triode connects the 5V bias supply, and the collector electrode of the one one triode connects bias supply with reference to ground; The emitter of the 9th triode links to each other with the emitter of the one one triode; The four or nine resistance and first shunt capacitance composition parallel branch parallel with one another; One end of this parallel branch connects the emitter of the 9th triode; The other end connects the base stage of NPN the tenth triode, and the emitter of the tenth triode is connected in bias supply with reference to ground; The input of the same name on the former limit of pulse transformer links to each other with the 5V bias supply, and the different name input on former limit links to each other with the collector electrode of the tenth triode; The anode of the 5th voltage-stabiliser tube links to each other with the 5V bias supply, and negative electrode links to each other with the negative electrode of the 6th diode, and the anode of the 6th diode is connected in the different name input on the former limit of pulse transformer; The output of the same name of pulse transformer secondary connects the anode of the 5th diode, and the different name output connects internal reference ground; The negative electrode of the 5th diode connects internal reference ground through first parallel resistance; The negative electrode of the 5th diode connects internal reference ground through second shunt capacitance; Be connected in the base stage of NPN the 8th triode simultaneously through the four or four resistance; The collector electrode of the 8th triode is connected in the base stage of NPN the 7th triode, and is connected in internal electric source through the four or five resistance; Seven, the emitter of eight triodes is connected in internal reference ground, and the collector electrode of the 7th triode is connected in internal electric source through the four or two resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110237263 CN102340246B (en) | 2011-08-18 | 2011-08-18 | Thick-film magnetic isolation direct current solid-state power controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110237263 CN102340246B (en) | 2011-08-18 | 2011-08-18 | Thick-film magnetic isolation direct current solid-state power controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102340246A true CN102340246A (en) | 2012-02-01 |
| CN102340246B CN102340246B (en) | 2013-11-06 |
Family
ID=45515801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110237263 Expired - Fee Related CN102340246B (en) | 2011-08-18 | 2011-08-18 | Thick-film magnetic isolation direct current solid-state power controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102340246B (en) |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769272A (en) * | 2012-07-18 | 2012-11-07 | 北京三一自动化技术有限责任公司 | Failure latching and resetting system of power converter and power converter |
| CN104320001A (en) * | 2014-10-29 | 2015-01-28 | 广州金升阳科技有限公司 | Magnetic isolation feedback circuit |
| CN104753033A (en) * | 2015-04-16 | 2015-07-01 | 重庆梅安森科技股份有限公司 | Power output overcurrent and overvoltage protector and anti-interference method thereof |
| CN104993811A (en) * | 2015-07-27 | 2015-10-21 | 深圳市英可瑞科技开发有限公司 | Overcurrent protection circuit for semiconductor switch |
| CN107015556A (en) * | 2017-04-28 | 2017-08-04 | 莱诺斯科技（北京）股份有限公司 | A kind of bus solid-state power controller test device |
| CN107453718A (en) * | 2017-09-26 | 2017-12-08 | 佛山市南海蜚声演出器材制造有限公司 | The non-electric current detection trigger protection circuit of power amplifier |
| CN107689733A (en) * | 2017-09-01 | 2018-02-13 | 壮都通信股份有限公司 | A kind of preservation method and electromagnetism fresh-keeping device |
| CN108649805A (en) * | 2018-06-14 | 2018-10-12 | 成都信息工程大学 | High power D C-DC power-switching circuits based on isolation and delay technology |
| CN109217856A (en) * | 2018-08-23 | 2019-01-15 | 北京机械设备研究所 | A kind of power electronic switching |
| CN109672432A (en) * | 2018-11-29 | 2019-04-23 | 杭州电子科技大学 | A kind of MOSFET direct-current solid-state relay circuit with short-circuit protection |
| CN109672433A (en) * | 2018-11-29 | 2019-04-23 | 杭州电子科技大学 | A kind of IGBT high voltage direct current solid-state relay circuit with short-circuit protection |
| CN109787044A (en) * | 2019-04-02 | 2019-05-21 | 佛山市顺德区信辉达电子有限公司 | Three pole on-off leakage protecting plug of semi-intelligent |
| CN110460012A (en) * | 2019-08-20 | 2019-11-15 | 南京志卓电子科技有限公司 | A kind of power device isolating and protecting device |
| CN110646780A (en) * | 2019-09-30 | 2020-01-03 | 南京邮电大学 | Photon synchronous detection circuit applied to single photon flight time ranging system and preparation method thereof |
| CN112367072A (en) * | 2020-10-26 | 2021-02-12 | 上海空间电源研究所 | Anti-saturation magnetic isolation circuit |
| CN113342122A (en) * | 2021-06-04 | 2021-09-03 | 上海空间电源研究所 | Long-delay all-solid-state power tuner for space |
| CN113708748A (en) * | 2021-07-22 | 2021-11-26 | 北京卫星制造厂有限公司 | Special integrated controller for solid-state electronic switch |
| CN113777984A (en) * | 2021-09-02 | 2021-12-10 | 郑州中科集成电路与系统应用研究院 | Direct-current high-voltage multi-path solid-state power controller |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4665355A (en) * | 1986-09-15 | 1987-05-12 | Rockwell International Corporation | Off line capacitor-divider power supply for solid state power controller |
| CN1667951A (en) * | 2005-03-08 | 2005-09-14 | 南京航空航天大学 | DC solid-state power switch circuit |
| US20060200688A1 (en) * | 2005-02-16 | 2006-09-07 | Farshid Tofigh | Power distribution system using solid state power controllers |
-
2011
- 2011-08-18 CN CN 201110237263 patent/CN102340246B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4665355A (en) * | 1986-09-15 | 1987-05-12 | Rockwell International Corporation | Off line capacitor-divider power supply for solid state power controller |
| US20060200688A1 (en) * | 2005-02-16 | 2006-09-07 | Farshid Tofigh | Power distribution system using solid state power controllers |
| CN1667951A (en) * | 2005-03-08 | 2005-09-14 | 南京航空航天大学 | DC solid-state power switch circuit |
Cited By (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769272A (en) * | 2012-07-18 | 2012-11-07 | 北京三一自动化技术有限责任公司 | Failure latching and resetting system of power converter and power converter |
| CN104320001A (en) * | 2014-10-29 | 2015-01-28 | 广州金升阳科技有限公司 | Magnetic isolation feedback circuit |
| CN104753033B (en) * | 2015-04-16 | 2018-05-04 | 重庆梅安森科技股份有限公司 | A kind of power supply output overcurrent and overvoltage protective device and its anti-interference method |
| CN104753033A (en) * | 2015-04-16 | 2015-07-01 | 重庆梅安森科技股份有限公司 | Power output overcurrent and overvoltage protector and anti-interference method thereof |
| CN104993811A (en) * | 2015-07-27 | 2015-10-21 | 深圳市英可瑞科技开发有限公司 | Overcurrent protection circuit for semiconductor switch |
| CN104993811B (en) * | 2015-07-27 | 2018-08-14 | 深圳市英可瑞科技股份有限公司 | A kind of current foldback circuit of semiconductor switch |
| CN107015556A (en) * | 2017-04-28 | 2017-08-04 | 莱诺斯科技（北京）股份有限公司 | A kind of bus solid-state power controller test device |
| CN107689733A (en) * | 2017-09-01 | 2018-02-13 | 壮都通信股份有限公司 | A kind of preservation method and electromagnetism fresh-keeping device |
| CN107689733B (en) * | 2017-09-01 | 2021-02-09 | 壮都通信股份有限公司 | Preservation method and electromagnetic preservation device |
| CN107453718B (en) * | 2017-09-26 | 2023-05-16 | 佛山市南海蜚声演出器材制造有限公司 | Non-current triggering detection protection circuit of power amplifier |
| CN107453718A (en) * | 2017-09-26 | 2017-12-08 | 佛山市南海蜚声演出器材制造有限公司 | The non-electric current detection trigger protection circuit of power amplifier |
| CN108649805A (en) * | 2018-06-14 | 2018-10-12 | 成都信息工程大学 | High power D C-DC power-switching circuits based on isolation and delay technology |
| CN108649805B (en) * | 2018-06-14 | 2023-11-10 | 成都信息工程大学 | High-power DC-DC power supply conversion circuit based on isolation and delay technology |
| CN109217856B (en) * | 2018-08-23 | 2022-05-31 | 北京机械设备研究所 | Power electronic switch |
| CN109217856A (en) * | 2018-08-23 | 2019-01-15 | 北京机械设备研究所 | A kind of power electronic switching |
| CN109672432B (en) * | 2018-11-29 | 2023-01-13 | 杭州电子科技大学 | MOSFET direct current solid state relay circuit with short-circuit protection |
| CN109672432A (en) * | 2018-11-29 | 2019-04-23 | 杭州电子科技大学 | A kind of MOSFET direct-current solid-state relay circuit with short-circuit protection |
| CN109672433A (en) * | 2018-11-29 | 2019-04-23 | 杭州电子科技大学 | A kind of IGBT high voltage direct current solid-state relay circuit with short-circuit protection |
| CN109672433B (en) * | 2018-11-29 | 2023-01-13 | 杭州电子科技大学 | IGBT high-voltage direct-current solid-state relay circuit with short-circuit protection |
| CN109787044A (en) * | 2019-04-02 | 2019-05-21 | 佛山市顺德区信辉达电子有限公司 | Three pole on-off leakage protecting plug of semi-intelligent |
| CN109787044B (en) * | 2019-04-02 | 2023-09-22 | 佛山市顺德区信辉达电子有限公司 | Semi-intelligent tripolar on-off leakage protection plug |
| CN110460012A (en) * | 2019-08-20 | 2019-11-15 | 南京志卓电子科技有限公司 | A kind of power device isolating and protecting device |
| CN110646780A (en) * | 2019-09-30 | 2020-01-03 | 南京邮电大学 | Photon synchronous detection circuit applied to single photon flight time ranging system and preparation method thereof |
| CN112367072A (en) * | 2020-10-26 | 2021-02-12 | 上海空间电源研究所 | Anti-saturation magnetic isolation circuit |
| CN113342122A (en) * | 2021-06-04 | 2021-09-03 | 上海空间电源研究所 | Long-delay all-solid-state power tuner for space |
| CN113708748A (en) * | 2021-07-22 | 2021-11-26 | 北京卫星制造厂有限公司 | Special integrated controller for solid-state electronic switch |
| CN113777984A (en) * | 2021-09-02 | 2021-12-10 | 郑州中科集成电路与系统应用研究院 | Direct-current high-voltage multi-path solid-state power controller |
| CN113777984B (en) * | 2021-09-02 | 2023-12-15 | 郑州中科集成电路与系统应用研究院 | DC high-voltage multipath solid-state power controller |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102340246B (en) | 2013-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102340246B (en) | Thick-film magnetic isolation direct current solid-state power controller | |
| CN102684656B (en) | Gate circuit | |
| CN105322522A (en) | Method and circuit for restraining surge current of DC electrical source | |
| CN103606895B (en) | A kind of overvoltage turn-off protection circuit | |
| CN203415971U (en) | Anti-overvoltage surge protection control circuit designed based on field-effect transistor | |
| CN103166444B (en) | Remote turn-off control signal receiving circuit | |
| CN208939567U (en) | IC chip protection circuit against input over-voltage | |
| CN102541144B (en) | Method for implementing alternating current-direct current (AC-DC) general solid state power controller and controller | |
| CN104410038A (en) | Overvoltage protection circuit for discharge regulating circuit | |
| CN216929868U (en) | Input protecting circuit for anti-impact MOS tube | |
| CN203645292U (en) | An overvoltage over-current protection circuit | |
| CN101651336A (en) | Distribution protection method and distribution protection device | |
| CN103701444A (en) | Power driving circuit with hard real-time overcurrent protection function | |
| CN102629758B (en) | Voltage comparator-based drop gate voltage circuit | |
| CN105610305A (en) | Current-limiting power supply control circuit of satellite solar cell array parallel regulator | |
| CN203840311U (en) | Solid state power controller | |
| CN209233749U (en) | Driver current-limited startup circuit for DC power-supply system | |
| CN109347315B (en) | Power-on buffer circuit of power electronic device | |
| CN108831798B (en) | Magnetic latching relay driving device for intelligent ammeter | |
| CN103326323A (en) | Switching power supply protective circuit and method | |
| CN105977908B (en) | Unmanned plane can recover DC over-voltage protection circuit automatically | |
| CN209929946U (en) | Power supply protection circuit of Ethernet switch | |
| CN103401220A (en) | Novel switch power supply short-circuit protection circuit and protection method | |
| CN208046209U (en) | A kind of output overvoltage protection circuit | |
| CN203645299U (en) | Hardware overload or short circuit protective circuit and DC power supply circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131106 Termination date: 20180818 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |