CN104320001A - Magnetic isolation feedback circuit - Google Patents
Magnetic isolation feedback circuit Download PDFInfo
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- CN104320001A CN104320001A CN201410593524.6A CN201410593524A CN104320001A CN 104320001 A CN104320001 A CN 104320001A CN 201410593524 A CN201410593524 A CN 201410593524A CN 104320001 A CN104320001 A CN 104320001A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
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- Dc-Dc Converters (AREA)
- Inverter Devices (AREA)
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Abstract
The invention provides a magnetic isolation feedback circuit which comprises an auxiliary edge chip, a compensating circuit, a magnetic isolation coupling transformer and a primary edge chip. A voltage amplitude signal is modulated into pulse width information, and the pulse width information is restored into the voltage amplitude signal after being transmitted through the magnetic isolation coupling transformer. By means of the magnetic isolation feedback circuit, an error signal can be fed back accurately, primary edge control of a controller is achieved, the interference-resisting capacity is high, and the design of the magnetic isolation coupling transformer is simplified.
Description
Technical field
The present invention relates to a kind of magnetic isolation feedback circuit, particularly in a kind of field of switch power, realize the magnetic isolation feedback circuit of closed-loop control.
Background technology
Off-line SMPS utilizes transformer to realize electrical isolation, and the signal of its output also needs the negative feedback control ring feeding back to former limit construction system isolator.Classical mode is the former limit that output voltage is fed back to converter by the trsanscondutance amplifier formed by TL431 and optocoupler.But TL431 and optocoupler all need larger static working current, and the optocoupler range of linearity is narrower.Especially under the severe applied environment such as high temperature, high irradiation, the performance of optocoupler is more unreliable, easily damages.Another isolation feedback system is Magnetic isolation, namely by a coupling transformer, output signal is fed back to former limit.The advantage of Magnetic isolation feedback has stronger anti-interference, Radiation hardness, can keep higher precision and stability under the adverse circumstances such as high temperature, high pressure.
In prior art, relatively more conventional Magnetic isolation feedback system is the UC1901 chip adopting TI, and this chip sampling electric power output voltage, to inner error amplifier, carries out chopper amplification by clock signal to it after producing error signal.The pulse formed is sent to main limit by halfwave rectifier, filter circuit reduction error signal by coupling transformer again.The weak point of this feedback system is to adopt which amplitude modulation to error signal, and amplitude is at any time in change, adds the design difficulty of transformer.And the power consumption of transformer is comparatively large when chopping frequency is lower, easily saturated, when error magnitude is lower, antijamming capability weakens.Patent US6301135 it is also proposed a kind of magnetic isolation feedback circuit, directly the PWM modulation signal of secondary error signal and triangle wave is sent to main limit control main switch.The link of reducing owing to not having error signal, this circuit can only realize secondary univoltage ring and control, and can cause difficulty when being used in the topologys such as flyback to loop compensation.
In addition, the magnetic isolation feedback circuit that discrete device is built is also had, as patent CN102185485 and patent CN103326579.The circuit that these two sections of patents propose remains and carries out which amplitude modulation to error signal, similar with the modulation demodulation system of UC1901, and the circuit reliability that discrete device is built is poor, occupies larger PCB surface and amasss.
Summary of the invention
The object of the invention is: provide a kind of magnetic isolation feedback circuit, this circuit can feedback error signal exactly, and the main limit realizing controller controls, and antijamming capability is strong, simplifies the design of Magnetic isolation coupling transformer.
The object of the invention is to be achieved through the following technical solutions: a kind of magnetic isolation feedback circuit, comprises secondary chip, compensating circuit, Magnetic isolation coupling transformer and main limit chip.Secondary chip by the information of FB port sampling power output end, and is translated into error signal, and outputted to one end of compensating circuit by COMP port, the other end of compensating circuit is connected to FB port; Meanwhile, be that pulse signal outputs to Magnetic isolation coupling transformer via TRP port and TRN port by error signals modulate, be connected to SP port and the SN port of main limit chip by Magnetic isolation coupling transformer; The pulse signal comprising error signal information is reduced to error signal by main limit chip, realizes closed-loop control.It is characterized in that:
Described secondary chip comprises error amplifier, error signals modulate unit and pulse modulation unit; The reference voltage V of the forward termination chip internal generation of described error amplifier
ref, described error amplifier negative end receives the sampled value K*V of electric power output voltage
out, described error amplifier output error signal is to error signals modulate unit; Error signals modulate is output to described pulse modulation unit after square-wave signal by described error signals modulate unit; Square-wave frequency modulation is that burst pulse outputs to Magnetic isolation coupling transformer by described pulse modulation unit;
Described former limit chip comprises main limit square wave reduction unit, main edge error signal demodulation unit, the second comparator, the first rest-set flip-flop and the second oscillator; The input of described main limit square wave reduction unit is connected the output of described Magnetic isolation coupling transformer with SP port by SN port, the output of described main limit square wave reduction unit outputs signal described main edge error signal demodulation unit; The positive input of described second comparator receives the output signal of autonomous edge error signal demodulation unit, the negative input of described second comparator connects the forward end of inductive current sampling resistor, the reset terminal R of the first rest-set flip-flop described in the output termination of described second comparator by CS port; The set end S of described first rest-set flip-flop meets the output terminal of clock CLK of described second oscillator, and the output Q of described first rest-set flip-flop connects power switch pipe by GATE port.
Preferably, described error signals modulate unit comprises the first oscillator, the first comparator, first and door and sawtooth waveforms generation unit; The forward end of described first comparator connects the output of described error amplifier, and the negative end of the first described comparator is connected to described sawtooth waveforms generation unit; The first described comparator output terminal connect described first with an input of door, described first inputs with another of door clock signal clk that described in termination, the first oscillator produces; Described first with the pulse modulation unit described in output termination of door; The inversion clock output CLK_ of the first described oscillator connects described sawtooth waveforms generation unit.
Preferably, described sawtooth waveforms generation unit comprises the first switching tube, the first current source, sawtooth waveforms generation electric capacity and second switch pipe; The grid of the first described switching tube and the grid of described second switch pipe meet the inversion clock output CLK_ of the first described oscillator; The source electrode of described first switching tube meets power supply VCC, and the drain electrode of described first switching tube connects the positive pole of described first current source; The drain electrode of described second switch pipe connects described sawtooth waveforms and produces one end of electric capacity and the negative pole of described first current source, ground connection together with the other end of the source electrode of described second switch pipe and sawtooth waveforms generation electric capacity.
Preferably, described pulse modulation unit comprises the 4th inverter, the 5th switching tube, the 6th switching tube, the 3rd current source, the second electric capacity, the first Schmidt trigger, the 5th inverter, the second NOR gate, the 4th current source, the 7th switching tube, the 8th switching tube, the 3rd electric capacity, the second Schmidt trigger, hex inverter and the 3rd NOR gate; The output of error signals modulate unit described in the input termination of described 4th inverter, and the input being connected respectively to the grid of described 7th switching tube, the grid of described 8th switching tube and described 3rd NOR gate; The output of described 4th inverter connects the grid of described 5th switching tube, the grid of described 6th switching tube and an input of described second NOR gate respectively; The source electrode of described 5th switching tube connects the negative pole of described 3rd current source, and the drain electrode of described 5th switching tube drain electrode and described 6th switching tube connects one end of described second electric capacity and the input of described first Schmidt trigger respectively; The source ground of described 6th switching tube; The input of the 5th inverter described in the output termination of described first Schmidt trigger, another input of the second NOR gate described in the output termination of described 5th inverter; The positive input of Magnetic isolation coupling transformer described in the output termination of described second NOR gate; The source electrode of described 7th switching tube connects the negative pole of described 4th current source, the drain electrode of described 7th switching tube and the drain electrode of described 8th switching tube connect one end of described 3rd electric capacity and the input of described second Schmidt trigger, the source ground of described 8th switching tube respectively; The input of hex inverter described in the output termination of described second Schmidt trigger, another input of the 3rd NOR gate described in the output termination of described hex inverter; The negative input of Magnetic isolation coupling transformer described in the output termination of described 3rd NOR gate.
Preferably, described main edge error signal demodulation unit comprises the first inverter, delay circuit Delay, the second inverter, the 3rd switching tube, the second current source, sawtooth waveforms reduction electric capacity, the 4th switching tube, the first NOR gate, the first transmission gate, the 3rd inverter, sampling capacitance; An input of the input of described first inverter, the input of described delay circuit Delay and described first NOR gate connects the output of described main limit square wave reduction unit respectively; The grid of the 3rd switching tube described in the output termination of described first inverter, the source electrode of described 3rd switching tube and drain electrode connect the positive pole of power supply VCC and described second current source respectively; The two ends of described sawtooth waveforms reduction electric capacity connect negative pole and the ground of described second current source respectively; The drain electrode of described 4th switching tube and source electrode connect negative pole and the ground of described second current source respectively; The input of the second inverter described in the output termination of described delay circuit Delay, the grid of the 4th switching tube described in the output termination of described second inverter and another input of described first NOR gate; A control end of the first transmission gate described in the output termination of described first NOR gate and the input of described 3rd inverter, another control end of first transmission gate described in the output termination of described 3rd inverter, the negative pole of the second current source described in the input termination of described first transmission gate, one end of sampling capacitance described in the output termination of described first transmission gate and the positive input of described second comparator.
Preferably, described main limit square wave reduction unit comprises the second rest-set flip-flop, the S end of described second rest-set flip-flop and R end receive two outputs of described Magnetic isolation coupling transformer respectively by main limit chip SP port and SN port, the Q end of described second rest-set flip-flop exports the square wave after reduction.
Preferably, described compensating circuit comprises the first electric capacity and the first resistance, the first described electric capacity and the first resistant series.
Below, in conjunction with anti exciting converter, above-mentioned magnetic isolation feedback circuit is described.Anti exciting converter as shown in Figure 1, comprises main power stage circuit and magnetic isolation feedback circuit.
Basic functional principle of the present invention is as follows: the output voltage V of power supply
outafter sampling network sampling, produce and V
outproportional sampled voltage K*V
out, wherein K=R
13/ (R
12+ R
13), R
12, R
13for the sampling resistor in Fig. 1.Sampled voltage is input to the backward end of error amplifier by the FB port of secondary chip, with the reference voltage V being connected on forward end
referror signal V is produced relatively
eabe connected to the first comparator COM
21positive input.First oscillator OSC
21clocking CLK and inversion signal CLK_ thereof, wherein, CLK_ is connected to the first switching tube PM in sawtooth waveforms generation unit 22
21grid and second switch pipe NM
22grid.Due to PM
21for PMOS, NM
22for NMOS tube, so two switching tube alternate conduction, produce electric capacity C at sawtooth waveforms
21upper generation and the synperiodic sawtooth signal V of clock signal
saw, V
sawbe connected to the first comparator COM
21negative input, the first comparator COM
21output provide the synperiodic square-wave signal P with sawtooth waveforms
21.P
21duty ratio by error signal V
eadetermine.P
21signal again with clock signal clk phase with output to pulse modulation unit P_G, with the maximum duty cycle of square wave to receive of performance constraint P_G.P_G produces and corresponds to square wave P
21the burst pulse of rising edge and trailing edge, when square wave rising edge arrives, in P_G unit, due to the 3rd current source I
s31to the second electric capacity C
31the time-lag action of charging, the second NOR gate NOR
31two inputs keep the electronegative potential of a very short time, then NOR simultaneously
31output provide burst pulse corresponding to square wave rising edge.In like manner, when square wave trailing edge arrives, the 3rd NOR gate NOR
32provide the burst pulse that corresponds to trailing edge.Pulse signal is transferred to the square wave reduction unit P_R on main limit through Magnetic isolation coupling transformer, and rising edge pulse and trailing edge pulse are input to S end and the R end of the second rest-set flip-flop after treatment respectively, then the Q of the second rest-set flip-flop holds the square wave P after providing reduction
22.P
22signal is through the first inverter NOT
21produce inversion signal P afterwards
23control the 3rd switching tube PM
22conducting or shutoff.Meanwhile, P
22signal produces a time delay t to its trailing edge after delay circuit Delay
d, obtain P
24signal.P
24signal obtains P after anti-phase
25signal controls the 4th switching tube NM
22conducting or shutoff.Due to P
24relative to P
23the many time delay t of rising edge
d, so sawtooth waveforms reduction electric capacity C
22on sawtooth waveforms V
saw_resa period of time t can be kept at peak value
d, this makes the first transmission gate TG
21with sampling capacitance C
23v can be sampled exactly
saw_rescurrent potential during peak value, and the error signal V that the height of spike potential exports with secondary error amplifier
eabe directly proportional.The sampling pulse of sampling hold circuit is by P
22with P
25phase or non-acquisition, the width of sampling pulse and t
didentical.Final at sampling capacitance C
23upper generation secondary error signal V
eathe recovering signal V of discretization
ea_res.
Beneficial effect of the present invention is:
1, provide above-mentioned a kind of magnetic isolation feedback circuit, instead of light-coupled isolation feedback, eliminate optocoupler life-span and performance degradation to the impact of product, can reduce the error signal of secondary exactly, realize the closed-loop control of main limit;
2, introduce above-mentioned modulation and demodulation circuit, therefore eliminate the peripheral rectification discrete device of traditional Magnetic isolation feedback needed for chip, simplify circuit design;
3, the burst pulse of isolation coupling transformer transmission has fixing amplitude and width, thus improves antijamming capability, simplifies the design of Magnetic isolation transformer.
Accompanying drawing explanation
Fig. 1 is the typical apply topology of magnetic isolation feedback circuit of the present invention;
Fig. 2 is magnetic isolation feedback circuit figure of the present invention;
Fig. 3 is pulse modulation unit of the present invention and main limit square wave reduction unit circuit diagram;
The oscillogram of Fig. 4 embodiment one medial error signal madulation;
The oscillogram of Fig. 5 embodiment one medial error signal receiving;
Analogous diagram before and after the reduction of Fig. 6 error signal.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with accompanying drawing 2, the present invention is described in more detail.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Embodiment one
A kind of magnetic isolation feedback circuit, as shown in Figure 2, comprising: secondary chip Sec_IC, main limit chip Pri_IC, compensating circuit and Magnetic isolation coupling transformer T2.
Compensating circuit comprises the first electric capacity C
cwith the first resistance R
c, C
cand R
cseries connection.
Secondary chip comprises error amplifier EA, error signals modulate unit 21 and pulse modulation unit P_G.
Wherein, error signals modulate unit 21 comprises the first oscillator OSC
21, the first comparator COM
21, first and door AND and sawtooth waveforms generation unit 22.Sawtooth waveforms generation unit 22 comprises the first switching tube PM
21, the first current source I
s21, sawtooth waveforms produces electric capacity C
21with second switch pipe NM
21.The reference voltage V of the forward termination chip internal generation of error amplifier EA
ref, the sampled value K*V of electric power output voltage
outbe input to the negative end of error amplifier EA by FB port, the output of EA connects the first comparator COM respectively
21forward end and the COMP port of secondary chip; Compensating circuit is composed in series by the first electric capacity Cc and the first resistance Rc, and the two ends of compensating circuit are connected respectively to negative end and the COMP port of error amplifier EA.First comparator COM
21negative end produce electric capacity C with sawtooth waveforms respectively
21one end, the first current source I
s21negative pole and second switch pipe NM
21drain electrode connect; First comparator COM
21export an input of termination first and door AND.Another input termination first oscillator OSC of AND
21the clock signal clk produced; The output termination pulse modulation unit P_G of AND.First oscillator OSC
21inversion clock output CLK_ meet the first switching tube PM
21grid and second switch pipe NM
21grid.First switching tube PM
21source electrode meet power supply VCC, the first switching tube PM
21drain electrode meet the first current source I
s21positive pole.Second switch pipe NM
21drain electrode connect sawtooth waveforms and produce electric capacity C
21one end and the first current source I
s21negative pole, second switch pipe NM
21source electrode and sawtooth waveforms produce electric capacity C
21other end ground connection together.The output of pulse modulation unit P_G connects the positive input of external isolation transformer T2 by TRP port and TRN port.
Main limit chip comprises main limit square wave reduction unit P_R, main edge error signal demodulation unit 23, second comparator COM
22, the first rest-set flip-flop FF
21with the second oscillator OSC
22.
Wherein, main edge error signal demodulation unit 23 comprises the first inverter NOT
21, delay circuit Delay, the second inverter NOT
22, the 3rd switching tube PM
22, the second current source I
s22, sawtooth waveforms reduction electric capacity C
22, the 4th switching tube NM
22, the first NOR gate NOR
21, the first transmission gate TG
21, the 3rd inverter NOT
23, sampling capacitance C
23.The input of main limit square wave reduction unit P_R is connected the output of outside Magnetic isolation coupling transformer with SP port by SN port, the output of P_R meets the first inverter NOT respectively
21input, the input of delay circuit Delay and the first NOR gate NOR
21an input; First inverter NOT
21output termination the 3rd switching tube PM
22grid, the 3rd switching tube PM
22source electrode and drain electrode meet power supply VCC and the second current source I respectively
s22positive pole; Sawtooth waveforms reduction electric capacity C
22two ends meet the second current source I respectively
s22negative pole and ground; 4th switching tube NM
22drain electrode and source electrode meet the second current source I respectively
s22negative pole and ground; The output termination second inverter NOT of delay circuit Delay
22input, the second inverter NOT
22output be connected on the 4th switching tube NM
22grid and the first NOR gate NOR
21another input; First NOR gate NOR
21the control end of output termination first transmission gate and the input of the 3rd inverter, the output termination first transmission gate TG of the 3rd inverter
21another control end, the first transmission gate TG
21input termination second current source I
s22negative pole, the first transmission gate TG
21output termination sampling capacitance C
23one end and the second comparator COM
22positive input, the second comparator COM
22negative input connected the forward end of external inductors current sampling resistor Rs, the second comparator COM by CS port
22output termination first rest-set flip-flop FF
21reset terminal R.First rest-set flip-flop FF
21set end S meet the second oscillator OSC
22output terminal of clock CLK, the first rest-set flip-flop FF
21output Q met power switch pipe M outside chip by GATE port
p.
As shown in Figure 3, pulse modulation unit P_G comprises the 4th inverter NOT
31, the 5th switching tube PM
31, the 6th switching tube NM
31, the 3rd current source I
s31, the second electric capacity C
31, the first Schmidt trigger SMT
31, the 5th inverter NOT
32, the second NOR gate NOR
31, the 4th current source I
s32, the 7th switching tube PM
32, the 8th switching tube NM
32, the 3rd electric capacity C
32, the second Schmidt trigger SMT
32, hex inverter NOT
33, the 3rd NOR gate NOR
32.4th inverter NOT
31the output of input termination error signals modulate unit 21, and be connected respectively to the 7th switching tube PM
32grid, the 8th switching tube NM
32grid and the 3rd NOR gate NOR
32an input; 4th inverter NOT
31output meet the 5th switching tube PM respectively
31grid, the 6th switching tube NM
31grid and the second NOR gate NOR
31an input; 5th switching tube PM
31source electrode meet the 3rd current source I
s31negative pole, the 5th switching tube PM
31drain electrode and the drain electrode of the 6th switching tube connect one end of the second electric capacity and the input of the first Schmidt trigger respectively; 6th switching tube NM
31source ground; First Schmidt trigger SMT
31output termination the 5th inverter NOT
32input, the 5th inverter NOT
32output termination second NOR gate NOR
31another input; Second NOR gate NOR
31the positive input of output termination Magnetic isolation coupling transformer T2.7th switching tube PM
32source electrode meet the 4th current source I
s32negative pole, the 7th switching tube PM
32drain electrode and the 8th switching tube NM
32drain electrode meet the 3rd electric capacity C respectively
32one end and the second Schmidt trigger SMT
32input, the 8th switching tube NM
32source ground; Second Schmidt trigger SMT
32output termination hex inverter NOT
33input, hex inverter NOT
33output termination the 3rd NOR gate NOR
32another input; 3rd NOR gate NOR
32the negative input of output termination Magnetic isolation coupling transformer T2.Two of T2 export the input of termination main limit square wave reduction unit P_R.
Main limit square wave reduction unit P_R comprises the second rest-set flip-flop FF
31, FF
31s end and R hold and receive two outputs of Magnetic isolation coupling transformer T2 respectively.
Below its concrete operation principle substep is illustrated.
1, secondary error signal V
eamodulation
Oscillator OSC
21clock signal clk _ control the PM exported
21and NM
21turn-on and turn-off, and then control current source I
s21to electric capacity C
21discharge and recharge.Due to PM
21and NM
21be respectively PMOS and NMOS tube, so two switching tube alternate conduction, when CLK_ is low level, PM
21conducting NM
21turn off, I
s21with constant electric current I
chargeto C
21charging.Suppose OSC
21the duty ratio of the clock CLK produced is D, and the cycle is T, then inversion clock CLK_ is low level time t
lfor T*D.OSC is set herein
21with maximum duty cycle 80% output clock CLK, then sawtooth waveforms V
sawamplitude can be provided by following formula:
In formula, C
sawfor electric capacity C
21capacitance.
When CLK_ is high level, PM
21turn off NM
21conducting is rapidly to C
21electric discharge.Sawtooth waveforms V
sawcycle identical with CLK, by comparator COM
21the signal V exported with error amplifier EA
eathe square-wave signal P of modulation is produced relatively
21, suppose that its duty ratio is D
p1, then specific D in the single cycle
p1value characterizes V in this cycle
eathe size of amplitude, corresponding pass is:
The waveform of part signal is shown in Fig. 4.P
21signal and CLK signal mutually with it after be modulated into and its rising edge and narrow pulse signal corresponding to trailing edge through extra pulse modulating unit P_G, be convenient to the transmission of Magnetic isolation coupling transformer.Level due to the reception of isolation transformation is all the burst pulse of fixed amplitude and width, thus simplifies the design of Magnetic isolation coupling transformer, improves antijamming capability.
2, the reduction of main edge error signal
The narrow pulse signal that Magnetic isolation coupling transformer passes over is reduced to and P after square wave reduction unit P_R
21identical square-wave signal P
22, the duty ratio in its single cycle is also D
p1.P
22through the first inverter NOT
21produce inversion signal P afterwards
23, in order to control the 3rd switching tube PM
22turn-on and turn-off.Meanwhile, P
22after delay unit Delay, trailing edge produces a time delay t
d, obtain P
24signal, t
dsize can be arranged according to demand.P
24through the second inverter NOT
22produce P afterwards
25signal is in order to control the 4th switching tube NM
22break-make.By current source I
s22to sawtooth waveforms reduction electric capacity C
22charging.For the ease of understanding, suppose I herein
s22with secondary current source I
s21identical, C
22with C
21identical.Because there is time delay t
d, PM
22oN time be T*D
p1, and NM
22oN time be T* (1-D
p1-t
d), then at PM
22after shutoff, the sawtooth waveforms V of reduction
saw_respeak value can at C
22upper maintenance time t
d, then pass through NM
22charge discharging resisting is fallen.T is set
dobject be convenient to subsequent sampling holding circuit have time enough to sample crest voltage exactly.Ideally, V
saw_respeak value should with the V of each cycle internal modulation
eaidentical.P
22with P
25phase or non-generation afterwards the first transmission gate TG
21control signal Sa, TG
21with sampling holding capacitor C
23composition sampling hold circuit, to V
saw_respeak value carry out sampling and keeping, then at C
23on can obtain reduction after the V of discretization
ea_ressignal.
3, the realization of current-mode
The electric current of power stage static exciter inductance produces pressure drop C on sampling resistor Rs
s.V after reduction
ea_ressignal and C
srelatively produce the reset signal Ctrl in each cycle, switch-off power pipe.And the turn-on instant of each cycle is by OSC
22the clock CLK produced determines.Work as FF
21reset terminal when being high level, the low level of CLK signal makes FF
21q hold set be 1, open peripheral power tube, power stage transformer starts excitation.And as current potential C on sampling resistor Rs
sreach V
ea_resvalue, then produce low level Ctrl reset FF
21, Q end is reset to 0, switch-off power pipe, and power stage transformer starts degaussing.Like this, just achieve traditional Peak Current Mode to control.
Generally speaking, basic thought of the present invention is: be pulse width information by voltage magnitude signal madulation, after the transmission of Magnetic isolation coupling transformer, then this pulse width information is reduced to voltage magnitude signal.So embodiments of the present invention are not limited thereto, according to foregoing, according to ordinary technical knowledge and the customary means of this area, do not departing under the present invention's above-mentioned basic fundamental thought prerequisite, magnetic isolation feedback circuit of the present invention also has other execution mode; Therefore the present invention can also make the amendment of other various ways, replacement or change, all drops within rights protection scope of the present invention.
Claims (7)
1. a magnetic isolation feedback circuit, comprises secondary chip, compensating circuit, Magnetic isolation coupling transformer and main limit chip; Secondary chip by the information of FB port sampling power output end, and is translated into error signal, and outputted to one end of compensating circuit by COMP port, the other end of compensating circuit is connected to FB port; Meanwhile, be that pulse signal outputs to Magnetic isolation coupling transformer via TRP port and TRN port by error signals modulate, be connected to SP port and the SN port of main limit chip by Magnetic isolation coupling transformer; The pulse signal comprising error signal information is reduced to error signal by main limit chip, realizes closed-loop control; It is characterized in that:
Described secondary chip comprises error amplifier, error signals modulate unit and pulse modulation unit; The reference voltage V of the forward termination chip internal generation of described error amplifier
ref, described error amplifier negative end receives the sampled value K*V of electric power output voltage
out, described error amplifier output error signal is to error signals modulate unit; Error signals modulate is output to described pulse modulation unit after square-wave signal by described error signals modulate unit; Square-wave frequency modulation is that burst pulse outputs to Magnetic isolation coupling transformer by described pulse modulation unit;
Described former limit chip comprises main limit square wave reduction unit, main edge error signal demodulation unit, the second comparator, the first rest-set flip-flop and the second oscillator; The input of described main limit square wave reduction unit is connected the output of described Magnetic isolation coupling transformer with SP port by SN port, the output of described main limit square wave reduction unit outputs signal described main edge error signal demodulation unit; The positive input of described second comparator receives the output signal of autonomous edge error signal demodulation unit, the negative input of described second comparator connects the forward end of inductive current sampling resistor, the reset terminal R of the first rest-set flip-flop described in the output termination of described second comparator by CS port; The set end S of described first rest-set flip-flop meets the output terminal of clock CLK of described second oscillator, and the output Q of described first rest-set flip-flop connects power switch pipe by GATE port.
2. magnetic isolation feedback circuit according to claim 1, is characterized in that: described error signals modulate unit comprises the first oscillator, the first comparator, first and door and sawtooth waveforms generation unit; The forward end of described first comparator connects the output of described error amplifier, and the negative end of the first described comparator is connected to described sawtooth waveforms generation unit; The first described comparator output terminal connect described first with an input of door, described first inputs with another of door clock signal clk that described in termination, the first oscillator produces; Described first with the pulse modulation unit described in output termination of door; The inversion clock output CLK_ of the first described oscillator connects described sawtooth waveforms generation unit.
3. magnetic isolation feedback circuit according to claim 2, is characterized in that: described sawtooth waveforms generation unit comprises the first switching tube, the first current source, sawtooth waveforms generation electric capacity and second switch pipe; The grid of the first described switching tube and the grid of described second switch pipe meet the inversion clock output CLK_ of the first described oscillator; The source electrode of described first switching tube meets power supply VCC, and the drain electrode of described first switching tube connects the positive pole of described first current source; The drain electrode of described second switch pipe connects described sawtooth waveforms and produces one end of electric capacity and the negative pole of described first current source, ground connection together with the other end of the source electrode of described second switch pipe and sawtooth waveforms generation electric capacity.
4. magnetic isolation feedback circuit according to claim 1, is characterized in that: described pulse modulation unit comprises the 4th inverter, the 5th switching tube, the 6th switching tube, the 3rd current source, the second electric capacity, the first Schmidt trigger, the 5th inverter, the second NOR gate, the 4th current source, the 7th switching tube, the 8th switching tube, the 3rd electric capacity, the second Schmidt trigger, hex inverter and the 3rd NOR gate; The output of error signals modulate unit described in the input termination of described 4th inverter, and the input being connected respectively to the grid of described 7th switching tube, the grid of described 8th switching tube and described 3rd NOR gate; The output of described 4th inverter connects the grid of described 5th switching tube, the grid of described 6th switching tube and an input of described second NOR gate respectively; The source electrode of described 5th switching tube connects the negative pole of described 3rd current source, and the drain electrode of described 5th switching tube drain electrode and described 6th switching tube connects one end of described second electric capacity and the input of described first Schmidt trigger respectively; The source ground of described 6th switching tube; The input of the 5th inverter described in the output termination of described first Schmidt trigger, another input of the second NOR gate described in the output termination of described 5th inverter; The positive input of Magnetic isolation coupling transformer described in the output termination of described second NOR gate; The source electrode of described 7th switching tube connects the negative pole of described 4th current source, the drain electrode of described 7th switching tube and the drain electrode of described 8th switching tube connect one end of described 3rd electric capacity and the input of described second Schmidt trigger, the source ground of described 8th switching tube respectively; The input of hex inverter described in the output termination of described second Schmidt trigger, another input of the 3rd NOR gate described in the output termination of described hex inverter; The negative input of Magnetic isolation coupling transformer described in the output termination of described 3rd NOR gate.
5. magnetic isolation feedback circuit according to claim 1, is characterized in that: described main edge error signal demodulation unit comprises the first inverter, delay circuit Delay, the second inverter, the 3rd switching tube, the second current source, sawtooth waveforms reduction electric capacity, the 4th switching tube, the first NOR gate, the first transmission gate, the 3rd inverter, sampling capacitance; An input of the input of described first inverter, the input of described delay circuit Delay and described first NOR gate connects the output of described main limit square wave reduction unit respectively; The grid of the 3rd switching tube described in the output termination of described first inverter, the source electrode of described 3rd switching tube and drain electrode connect the positive pole of power supply VCC and described second current source respectively; The two ends of described sawtooth waveforms reduction electric capacity connect negative pole and the ground of described second current source respectively; The drain electrode of described 4th switching tube and source electrode connect negative pole and the ground of described second current source respectively; The input of the second inverter described in the output termination of described delay circuit Delay, the grid of the 4th switching tube described in the output termination of described second inverter and another input of described first NOR gate; A control end of the first transmission gate described in the output termination of described first NOR gate and the input of described 3rd inverter, another control end of first transmission gate described in the output termination of described 3rd inverter, the negative pole of the second current source described in the input termination of described first transmission gate, one end of sampling capacitance described in the output termination of described first transmission gate and the positive input of described second comparator.
6. magnetic isolation feedback circuit according to claim 1, it is characterized in that: described main limit square wave reduction unit comprises the second rest-set flip-flop, the S end of described second rest-set flip-flop and R end receive two outputs of described Magnetic isolation coupling transformer respectively by main limit chip SP port and SN port, the Q end of described second rest-set flip-flop exports the square wave after reduction.
7. magnetic isolation feedback circuit according to claim 1, is characterized in that: described compensating circuit comprises the first electric capacity and the first resistance, the first described electric capacity and the first resistant series.
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