CN102340246B - Thick-film magnetic isolation direct current solid-state power controller - Google Patents
Thick-film magnetic isolation direct current solid-state power controller Download PDFInfo
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Abstract
The invention discloses a thick-film magnetic isolation direct current solid-state power controller which comprises a power MOSFET (metal oxide semiconductor field effect transistor), a detection resistor, a power diode, a TVS (transient voltage suppressor) diode, a current conditioning circuit, a voltage detection circuit, a voltage state judgment circuit, a current state judgment circuit, an immediate trip circuit, an inverse time circuit, a short-circuit detection circuit, a driving circuit, a state synthetic circuit, a trip state latch circuit, a time delay reset circuit, a time sequence matching circuit, a DC/DC (direct current/direct current) isolated power supply, a first isolation circuit, a second isolation circuit, a third isolation circuit, a state feedback interface circuit, a control signal interface circuit and a power-on reset circuit. The circuit structure can optimize the electrical properties of the controller, reduce the volume and the weight, improve the reliability and is widely applied to civil low-voltage direct current power distribution systems, aviation, aerospace, tanks, automobiles, ships and other fields.
Description
Technical field
The invention belongs to power electronics and electrical technology field, particularly a kind of DC solid power control device.
Background technology
Solid-state power controller is the Intelligent power distribution device consisted of semiconductor device produced along with the development of aircraft distribution system, it is core component and the final execution unit of solid-state distribution system, have switching function and defencive function concurrently, and can accept the control signal of prime computer and report its state information; When overload occurs in load, according to the tripping operation of anti-delay characteristic, protection circuit and load equipment; When load is short-circuited, within the time of tens microseconds, load fault is cut off in quick acting; Solid-state power controller has without electric arc, contactless, noiseless, response is fast, electromagnetic interference is little and be convenient to the advantage such as computer remote control, but in all extensive uses of the occasions such as civilian low-voltage direct distribution system, aviation, tank, spacecraft, automobile, naval vessel.
The circuit of DC solid-state power controller, aspect specific implementation and manufacturing process, exists following key technology problems at present:
(1) the soft connection of DC solid-state power controller and soft shutoff problem
Soft connection and soft turn-off function are absolutely necessary for DC solid-state power controller: there is larger impulse current in capacitive load in opening process, according to varying in size of load capacitance, impulse current can reach 2-6 doubly, even, more than 10 times, may cause like this tripping operation; The impulse current that soft turn-on power loss can suppress DC solid-state power controller band capacitive load well while opening, thus DC solid-state power controller band capacitance load capability improved; Owing to inevitably existing distributed inductance in distribution line, during the DC solid-state power controller switching off load, can produce the induction peak voltage caused because of di/dt at power semiconductor switch pipe two ends in addition, soft turn-off function can address this problem well; DC solid-state power controller some integrated circuits that adopt in the solution of soft connection and soft shutoff problem drive chip more at present, and the one, effect is not ideal enough, and the 2nd, the complicated and inconvenient whole circuit of scheme is integrated.
(2) the short-circuit protection problem of DC solid-state power controller
Load short circuits, as the severeest fault mode, may produce the thermal stress that has harm, causes solid-state power controller to damage or the tripping operation of higher level's protective device; Therefore solid-state power controller should be able to fast detecting to short trouble and turn-off rapidly, guaranteed output MOSFET safety and be connected to the load uninterrupted power supply on same busbar; At present mostly the detection method of short-circuit protection is detection power MOSFET both end voltage, the problem existed like this be short-circuit protection circuit and soft connection, soft breaking circuit in conjunction with the time comparatively complicated, and poor anti jamming capability, easily mistake is protected.
(3) the protection problem of power semiconductor switch pipe in DC solid-state power controller
The power semiconductor switch pipe is one of core devices in DC solid-state power controller, and whether the safety of power semiconductor switch pipe has determined that can the function of DC solid-state power controller normally realize; In DC solid-state power controller, the resist technology of power semiconductor switch pipe is one of key technology of solid-state power controller always; Adopt at present the method for buffer circuit for the protection of power semiconductor switch pipe more; do like this and only solved some electric stresss in the turn off process; the surge voltage that not may not occur in taking into account system and the load impact on the power semiconductor switch pipe, do not consider power MOSFET in long-term work yet and transship, thermal stress during short circuit.
(4) sequence problem of voltage and current State-output in DC solid-state power controller
DC solid-state power controller can be to host computer feedback load voltage and load current state, and host computer is according to the operating state of load voltage state and the judgement load of load current state and the solid-state power controller of switch control command and feedback; Therefore the load voltage of feedback and load current state need to be done to synchronous output processing, otherwise may cause host computer to do the judgement made mistake.
(5) the electrification reset problem of DC solid-state power controller
The course of work of DC solid-state power controller is normally first given the power supply of control section bias supply, then by sending to order to control to control section, opens shutoff; Electrification reset refers to when the SSPC control section is not powered, if sent, opens order, now gives the power supply of SSPC control section bias supply again, and SSPC should not open so; If make SSPC open-minded, must first send and turn-off order, then send out and open order, existing solid-state power controller does not have this consideration.
(6) isolating problem of DC solid-state power controller and host computer interface section
For fear of the forceful electric power loop, the light current control loop is disturbed, at host computer, to solid-state power controller, send and open while turn-offing control command and DC solid-state power controller to the host computer feedback states, usually need to provide electrical isolation; Using at present more method is to adopt light-coupled isolation, has that volume is little, a fast response time, easily and logical circuit coordinates, the advantage such as easy to use; But the problem that light-coupled isolation exists be power consumption more greatly, the shortcoming such as radiation hardness not, limited its use in the space industry space environment.
Summary of the invention
Technical problem to be solved by this invention, for the defect of pointing out in aforementioned background art and deficiency, a kind of thick-film magnetic isolation direct current solid-state power controller is provided, but the electric property of its optimal controller, reduce volume weight, improve reliability, but in all extensive uses of the occasions such as civilian low-voltage direct distribution system, aviation, tank, automobile, naval vessel, and the expansion application, be applicable to very much the AEROSPACE APPLICATION environment.
The present invention is for solving above technical problem, and the technical scheme adopted is:
A kind of thick-film magnetic isolation direct current solid-state power controller, comprise power MOSFET, detect resistance, power diode, the TVS diode, the current regulating circuit, voltage detecting circuit, the voltage status decision circuitry, the current status decision circuitry, trip circuit immediately, the inverse time lag circuit, short-circuit detecting circuit, drive circuit, the state synthetic circuit, the tripped condition latch cicuit, time-delay reset circuit, the sequential match circuit, the DC/DC insulating power supply, the first buffer circuit, the second buffer circuit, the 3rd buffer circuit, the state feedback interface circuit, control signal interface circuit and electrify restoration circuit,
The drain electrode of power MOSFET connects the power input, and source electrode is connected to load via detection resistance and then arrives Power Groud, the anodic bonding Power Groud of power diode, and negative electrode connects power take-off; The anode of TVS diode is connected to Power Groud, and negative electrode is connected to the power input;
The input of current regulating circuit is connected to the two ends of detecting resistance, and output is connected to respectively inverse time lag trip circuit, trip circuit, short-circuit detecting circuit and current status decision circuitry immediately; The output of voltage detecting circuit connects the voltage status decision circuitry; The all synchronously output after the processing of sequential match circuit of the output signal of aforesaid voltage status determination circuit and current status decision circuitry; The output signal of sequential match circuit is connected to the state feedback interface circuit respectively after the second buffer circuit and the 3rd buffer circuit, and the output signal of described state feedback interface circuit is load current status signal and the load voltage status signal that feeds back to host computer;
The inverse time lag circuit and immediately the output signal of trip circuit be input to the tripped condition latch cicuit, and the output signal of short-circuit detecting circuit also is connected to the tripped condition latch cicuit, the output signal of the output signal of this tripped condition latch cicuit and the first buffer circuit is input to the state synthetic circuit jointly, and the output signal of the output signal of state synthetic circuit and short-circuit detecting circuit jointly is input to and opens in soft shutoff drive circuit with falling the soft of grid voltage defencive function, this circuit output is connected to the grid source electrode of power MOSFET, the input signal of state synthetic circuit also is connected to time-delay reset circuit as input signal simultaneously, the output signal of state synthetic circuit is sent to the sequential match circuit,
Outside control command is connected in the control signal interface circuit through electrify restoration circuit, the output of control signal interface circuit is connected in the first buffer circuit, the output signal of the first buffer circuit is connected to state synthetic circuit and time-delay reset circuit, and the output of time-delay reset circuit is connected to the tripped condition latch cicuit;
Electrify restoration circuit, control signal interface circuit, state feedback interface circuit are powered by outside 5V bias supply, the DC/DC insulating power supply boosts to 15V by outside 5V bias voltage, using the power MOSFET source electrode as internal reference ground, give following functional circuit module power supply: state synthetic circuit, time-delay reset circuit, sequential match circuit, short-circuit detecting circuit, inverse time lag circuit, trip circuit, tripped condition latch cicuit, drive circuit, voltage detecting circuit, voltage status decision circuitry, current status decision circuitry and current regulating circuit immediately.
Above-mentioned drive circuit comprises soft connection and soft breaking circuit and falls the grid voltage short-circuit protection circuit, wherein, the structure of soft connection and soft breaking circuit is: control signal is connected the base stage of NPN the 5th triode through the three or five resistance, power supply connects the collector electrode of the 5th triode by the two or eight resistance, and the emitter of the 5th triode is connected with reference ground; The collector electrode of the 5th triode also respectively by the 31, four zero resistances are connected in the base stage of NPN second, six triodes, the second, the emitter of six triodes all with reference to ground is connected, and the collector electrode of second, six triodes is connected in power supply by the 27,32 resistance respectively; The two or nine resistance is from the collector electrode of the second triode, through the 4th electric capacity, the three or four resistance, three nine-day periods after the winter solstice resistance, arrive with reference to ground, and the three or four resistance wherein also forward be parallel with the second diode; The node that the two or nine resistance is connected with the 4th electric capacity is connected in the base stage of NPN the first triode and PNP the 3rd triode, and the emitter of first and third triode is connected, and the collector electrode of the first triode is connected to power supply, and the collector electrode of the 3rd triode is connected to reference to ground; One end of the 3rd zero resistance is connected with the emitter of first and third triode, the other end is connected to the grid of power MOSFET, at the grid of power MOSFET pseudo-ginseng resistance in parallel, after third and fourth voltage-stabiliser tube differential concatenation, be connected in parallel between the grid and source electrode of power MOSFET;
Described structure of falling the grid voltage short-circuit protection circuit is: the short-circuit condition signal that short-circuit detecting circuit sends connects the input of the first NAND gate, the collector electrode of the 6th triode connects another input of the first NAND gate and the negative polarity input that output stage is open-collector the first comparator, the output of the first NAND gate is connected to an input of the second NAND gate, and second, four NAND gate connect to form rest-set flip-flop; The positive polarity input termination reference voltage of the first comparator, and the positive polarity input that is open-collector the second comparator with output stage is connected, the output of the first comparator is connected to the negative polarity input point of the second comparator, and by first, resistance and the five or two electric capacity are connected to power supply and, with reference to ground, the output of the second comparator is connected in power supply via the one one two resistance one by one respectively; The output of the 4th NAND gate is connected to two inputs of the 3rd NAND gate, and the output of the 3rd NAND gate is received the base stage of NPN the 4th triode by the three or six resistance, the emitter of the 4th triode connects with reference to ground, the collector electrode of the 4th triode is connected to reference to ground by the three or three resistance and the 5th electric capacity, the anode of the first diode is connected in the node that the two or nine resistance is connected with the 4th electric capacity, and negative electrode is connected in the node that the three or three resistance is connected with the 5th electric capacity; The two or six resistance connects the negative electrode of power supply and the first diode.
The structure of above-mentioned inverse time lag circuit is: the output of current regulating circuit connects the negative polarity input of the 3rd operational amplifier via the one or four resistance, the the one two, the 1 resistance is composed in series voltage divider, the 5V reference voltage is carried out to dividing potential drop, the voltage of getting is connected in the positive polarity input of the 3rd operational amplifier by the one or seven resistance, the one or five resistance is connected to the output of the 3rd operational amplifier, the 3rd electric capacity is connected across the other end of the one or five resistance and the negative polarity input of the 3rd operational amplifier, and the output of the 3rd comparator is connected in power supply through the one one resistance; The negative polarity input of the 3rd comparator is linked the negative polarity input of open-collector the 4th comparator by low pass filter, power supply is connected to reference to ground through the 23,25 resistance, the positive polarity input that a bit is connected to the 4th comparator that the 22,25 resistance are connected, and the output of the 4th comparator is connected with the output of the 3rd comparator, as inverse time lag circuit and the output of trip circuit immediately.
The structure of above-mentioned sequential match circuit is: five, six, seven, eight comparators are all that output stage is open-collector comparator, the output of state synthetic circuit connects the negative polarity input of the 5th comparator and the positive polarity input of the 7th comparator, and the positive polarity input of the 5th, six, eight comparators is connected and is connected to reference voltage with the negative polarity input of the 7th comparator; The output of the 5th comparator connects the negative polarity input of the 6th comparator, and connects with reference to ground, by the seven or two resistance, connects power supply by the two or three electric capacity; The output of the 7th comparator connects the negative polarity input of the 8th comparator, and connects with reference to ground, by the seven or four resistance, connects power supply by the two or four electric capacity; The output of the 6th comparator connects the input of the 5th, six NAND gate, and connects power supply by the seven or three resistance; The output of the 8th comparator connects the input of the 5th, eight NAND gate, and connects power supply by the Seventh Five-Year Plan resistance; The output of the 5th NAND gate connects the input of the 6th, eight NAND gate, and the output of the 6th, eight NAND gate connects the input of the 7th NAND gate, the output of the 7th NAND gate also connects the trigger end of first and second d type flip flop, and the output of the D termination voltage status determination circuit of the first d type flip flop, the Q end connects the input of the 3rd buffer circuit, the output of the D termination current status decision circuitry of the second d type flip flop, the Q end connects the input of the second buffer circuit.
The structure of above-mentioned electrify restoration circuit is: the base stage of NPN the second triode is received in the shutoff order of opening that host computer sends by the 6th resistance, the emitter of this second triode is connected in the base stage of NPN the 3rd triode, and the base stage of the collector electrode of second and third triode and NPN the first triode is connected, and be connected in the 5V bias supply by the second resistance, the emitter of first and third triode is connected in the reference ground of 5V bias supply, and the collector electrode of the first triode connects the 5V bias supply by the first resistance; The 4th resistance and the second capacitances in series, another termination 5V bias supply of the 4th resistance, the reference ground of another termination 5V bias supply of the second electric capacity; The reference ground that the D end of 3d flip-flop and clock end are connected in the 5V bias supply, clear terminal is connected in the collector electrode of the first triode, and preset end is connected in the node that the second electric capacity is connected with the 4th resistance, and 3d flip-flop
end be connected in first with the input of door, and this first with another input be connected the collector electrode of the first triode, its output is the input of connection control signal interface circuit.
The structure of above-mentioned the first buffer circuit is: second with the input of door respectively output and the high-frequency impulse of connection control signal interface circuit, output connects NPN the 9th, the base stage of triode one by one, the collector electrode of the 9th triode connects the 5V bias supply, and the collector electrode of the one one triode connects bias supply with reference to ground; The emitter of the 9th triode is connected with the emitter of the one one triode, the four or nine resistance and the first shunt capacitance composition parallel branch parallel with one another, one end of this parallel branch connects the emitter of the 9th triode, the other end connects the base stage of NPN the tenth triode, and the emitter of the tenth triode is connected in bias supply with reference to ground; The input of the same name of pulse transformer is connected with the 5V bias supply, and the different name input is connected with the collector electrode of the tenth triode; The anode of voltage-stabiliser tube is connected with the 5V bias supply, and negative electrode is connected with the negative electrode of the 6th diode, and the anode of the 6th diode is connected in the different name input of pulse transformer; The output of the same name of pulse transformer connects the anode of the 5th diode, and the negative electrode of the 5th diode connects internal reference ground by the first parallel resistance, the negative electrode of described the 5th diode also connects internal reference ground by the second shunt capacitance, the negative electrode of the 5th diode is connected in the base stage of NPN the 8th triode simultaneously by the four or four resistance, the collector electrode of the 8th triode is connected in the base stage of NPN the 7th triode, and is connected in internal electric source by the four or five resistance; Seven, the emitter of eight triodes is connected in internal reference ground, and the collector electrode of the 7th triode is connected in internal electric source by the four or two resistance.
After adopting such scheme, thick-film technique magnetic isolated DC solid-state power controller provided by the present invention has the following advantages:
(1) soft connection technology has effectively suppressed the impulse current in solid-state power controller band capacitive load opening process, has improved the ability with capacitive load;
(2) soft turn-off technique and effectively suppressed the peak voltage in the inductive load turn off process, the safety of guaranteed output MOSFET with the antiparallel power diode of load;
(3) the TVS diode has suppressed the impact to power MOSFET of the surge voltage that exists in the system, the safety of guaranteed output MOSFET effectively;
(4) the simple easily realization and more accurate of inverse time lag circuit, the protection curve can be according to needing to adjust by changing component parameters;
(5) realized the short-circuit protection of fast and reliable with the soft connection, the soft breaking circuit that fall the grid voltage short-circuit protection;
(6) realized that state feedback synchronously exports, made host computer can not make erroneous judgement to the state of solid-state power controller and load;
(7) partly adopt the magnetic isolation technology at the solid-state power controller external interface, reduced power consumption, simultaneously can radiation hardness, expanded the application scenario of solid-state power controller, be applicable to very much the applied environment of space flight;
(8) system applies that electrify restoration circuit is solid-state power controller provides flexibility;
(9) thick-film technique and the wiring technique that are applicable to solid-state power controller have reduced volume and weight greatly, have improved reliability.
The accompanying drawing explanation
Fig. 1 is theory diagram of the present invention;
Fig. 2 (a) is the circuit structure of the pure resistive load of band of the present invention;
Fig. 2 (b) is the oscillogram of Fig. 2 (a) when normally opening shutoff;
Fig. 3 (a) is the circuit structure of band capacitance-resistance of the present invention load;
Fig. 3 (b) is the oscillogram of Fig. 3 (a) when normally opening shutoff;
Fig. 4 (a) is the circuit structure of band resistance sense of the present invention load;
Fig. 4 (b) is the oscillogram of Fig. 4 (a) when normally opening shutoff;
Fig. 5 is the drive circuit figure of the present invention with the soft connection of falling the grid voltage short-circuit protection function and soft shutoff;
Fig. 6 is be short-circuited after normally the opening oscillogram of fault of load in Fig. 2 (a);
Fig. 7 is the typical inverse time protection curve of DC solid-state power controller;
Fig. 8 is the circuit diagram of inverse time lag circuit in the present invention;
Fig. 9 (a) is the circuit diagram of sequential match circuit in the present invention;
Fig. 9 (b) is the working waveform figure of Fig. 9 (a);
Figure 10 is the circuit diagram of electrify restoration circuit in the present invention;
Figure 11 is the sequential schematic diagram of Figure 10;
Figure 12 is the theory diagram of the first buffer circuit in the present invention;
Figure 13 is the circuit diagram of the first buffer circuit in the present invention;
Figure 14 is the working waveform figure of Figure 13.
Embodiment
At first with reference to shown in figure 1, the invention provides a kind of thick-film magnetic isolation direct current solid-state power controller, comprise power MOSFET, detect resistance, power diode, the TVS diode, the current regulating circuit, voltage detecting circuit, the voltage status decision circuitry, the current status decision circuitry, trip circuit immediately, the inverse time lag circuit, short-circuit detecting circuit, drive circuit, the state synthetic circuit, the tripped condition latch cicuit, time-delay reset circuit, the sequential match circuit, the DC/DC insulating power supply, the first buffer circuit, the second buffer circuit, the 3rd buffer circuit, the state feedback interface circuit, control signal interface circuit and electrify restoration circuit, below putting up with its annexation and course of work separately describes.
DC power supply power input process power MOSFET and current detection circuit are connected to load and then arrive Power Groud, and the lower end of current detection circuit is power take-off; The anode of power diode is connected to Power Groud, and negative electrode is connected to power take-off; The anode of TVS diode is connected to Power Groud, and negative electrode is connected to the power input.
Adopting detection resistance that the electric current of solid-state power controller is converted into to voltage is detected, described detection resistance is connected between power MOSFET and power diode, the current regulating circuit is amplified and is lifted pressure for the voltage that will detect resistance, and carries out filtering and eliminate interference.
The output of current regulating circuit is connected to respectively inverse time lag trip circuit, trip circuit, short-circuit detecting circuit and current status decision circuitry immediately; The output of load voltage testing circuit connects the voltage status decision circuitry; The all synchronously output after the processing of sequential match circuit of the output signal of aforesaid voltage status determination circuit and current status decision circuitry; The output signal of sequential match circuit is connected to the state feedback interface circuit through the second buffer circuit and the 3rd buffer circuit respectively, and the output signal of described state feedback interface circuit is load current status signal and the load voltage status signal that feeds back to host computer.
Connect aforementioned, the inverse time lag circuit and immediately the output signal TRIP of trip circuit be input to the tripped condition latch cicuit, and the output signal SHORT of short-circuit detecting circuit also is connected to the tripped condition latch cicuit, the output signal CMD2 of the output signal FAULT of this tripped condition latch cicuit and the first buffer circuit is input to the state synthetic circuit jointly, and the output signal SHORT of the output signal CMD3 of state synthetic circuit and short-circuit detecting circuit jointly is input to and opens in soft shutoff drive circuit with falling the soft of grid voltage defencive function, this circuit output is connected to the grid source electrode of power MOSFET, the input signal CMD2 of state synthetic circuit also is connected to time-delay reset circuit as input signal simultaneously, the output signal CMD3 of state synthetic circuit is sent to the sequential match circuit.
Outside control command CMD is connected in the control signal interface circuit through electrify restoration circuit, the output of control signal interface circuit is connected in the first buffer circuit, the output signal CMD2 of the first buffer circuit is connected to state synthetic circuit and time-delay reset circuit, and the output of time-delay reset circuit connects the tripped condition latch cicuit.
Electrify restoration circuit, control signal interface circuit, state feedback interface circuit are powered by outside 5V bias supply, the DC/DC insulating power supply boosts to 15V by outside 5V bias voltage, using the power MOSFET source electrode as internal reference ground, give following functional circuit module power supply: state synthetic circuit, time-delay reset circuit, sequential match circuit, short-circuit detecting circuit, inverse time lag circuit, trip circuit, tripped condition latch cicuit, drive circuit, voltage status decision circuitry, current status decision circuitry, current regulating circuit, voltage detecting circuit immediately.
Coordinate again shown in Fig. 1, when the present invention works, by host computer, send control command CMD, control turning on and off of drive circuit driving power MOSFET control load after internal logic is processed; Power is input as the direct current Bus Voltage, and power stage connects load and returned by Power Groud; Adopt to detect the resistance sampling load current in loop of power circuit, to the signal of sampling through the amplification of current regulating circuit, lift press and filtering after, with the inverse time lag circuit and immediately the benchmark of trip circuit and short-circuit detecting circuit compare and time delay; Inverse time lag circuit and the output of trip circuit are immediately latched tripped condition after the tripped condition latch cicuit, and with the CMD2 signal sent from front end, to carry out state comprehensive; When inverse time lag circuit and trip circuit action immediately, by the soft switching off load of drive circuit; When load short circuits occurs, short-circuit detecting circuit can detect, and drive circuit receives the signal of aforementioned short-circuit detecting circuit and latchs short-circuit condition, by drive circuit, falling the rapid switch-off power MOSFET of grid voltage circuit; The result of voltage, current status decision circuitry is sent in the state feedback interface circuit through sequential match circuit and second and third buffer circuit respectively, completes the state feedback to host computer.
Below introduce in detail some key technologies involved in the present invention, to support the claim part.
1. the main power topological structure of DC solid-state power controller: direct voltage through the power input to power MOSFET, detect resistance and arrive again Power Groud to load, load two ends inverse parallel power diode, power input and Power Groud between TVS diode in parallel; When power MOSFET, during in off state, the power input voltage almost completely is added in the power MOSFET two ends, and the TVS diode can be limited in certain limit by it when power input overvoltage, therefore can effectively protect power switch pipe.
Fig. 2 (a) has provided the circuit structure under the pure resistive load of band of the present invention, by power ratio control MOSFET, comes opening or turn-offing of control load, load voltage V
loadand load current (is now the electric current I of SSPC
sSPC) the synchronous variation, provided waveform correlation in Fig. 2 (b).
Fig. 3 (a) has provided the circuit structure under band capacitance-resistance of the present invention load, and when solid-state power controller is opened, the supply voltage of power input will charge to load capacitance, therefore can in opening process, have impulse current; Stable state open after electric capacity be the equal of the open circuit, the voltage on electric capacity is the voltage drop that the power input terminal voltage deducts solid-state power controller; When solid-state power controller turn-offs, the energy of storing on electric capacity is released by load resistance, and Fig. 3 (b) has provided waveform correlation.
Fig. 4 (a) has provided the circuit structure under band resistance sense of the present invention load, when solid-state power controller is opened, owing to being connected in series inductance in load, so the rising of load current will lag behind the rising of load voltage; During shutoff, the decline of load current is also the decline that lags behind load voltage, therefore after load voltage drops to zero within a certain period of time, because load current does not drop to zero, must from the antiparallel power diode D1 of load afterflow, until inductive current decays to zero; Fig. 4 (b) has provided waveform correlation; The power diode D1 of afterflow has reduced the voltage stress of power MOSFET while turn-offing effectively, has protected the safety of power MOSFET.
2. with the soft connection of falling the grid voltage short-circuit protection function, soft shutoff drive circuit
Using the source electrode of power MOSFET as with reference to ground with the soft connection of falling the grid voltage short-circuit protection function and soft shutoff drive circuit, be designated as FGND, formed by two parts: the one, soft connection and soft breaking circuit, the 2nd, the grid voltage short-circuit protection circuit falls.The concrete composition as shown in Figure 5, be described below respectively:
The structure of soft connection and soft breaking circuit is: control signal CMD3 is connected in the base stage of NPN triode T5 through resistance R 35, power Vcc (15V) is connected in the collector electrode of triode T5 by resistance R 28, and the emitter of triode T5 is connected with reference ground FGND; The collector electrode of triode T5 also is connected in respectively the base stage of NPN triode T2 and T6 by resistance R 31 and R40, the emitter of triode T2 and T6 is connected with reference ground FGND, and the collector electrode of triode T2 and T6 is connected in power Vcc by resistance R 27 and R32 respectively; Resistance R 29 is from the collector electrode of triode T2, through capacitor C 4, resistance R 34, resistance R 39, arrive with reference to ground FGND, and resistance R wherein 34 gone back forward and is parallel with diode D2; The node DRIVE0 that resistance R 29 is connected with capacitor C 4 is connected in the base stage of NPN triode T1 and PNP triode T3, and the emitter of triode T1 and T3 is connected, and the collector electrode of triode T1 is connected to power Vcc, and the collector electrode of triode T3 is connected to reference to ground FGND; One end of resistance R 30 is connected with the emitter of triode T1, T3, and the other end is connected to the grid of MOSFET, and the grid parallel resistance R37 at MOSFET, be connected in parallel between MOSFET grid and source electrode after voltage-stabiliser tube Z3 and Z4 differential concatenation.
The structure of falling the grid voltage short-circuit protection circuit is: U5A, U5B, U5C and U5D right and wrong door, and U111A and U111B are that output stage is open-collector comparator; The SHORT signal is the short-circuit condition signal that short-circuit detecting circuit sends, be connected in the input of NAND gate U5A, the collector electrode of triode T6 connects another input of NAND gate U5A and the negative polarity input of U111A, the output of U5A is connected to the input of U5B, and U5B and U5D connect into the form of rest-set flip-flop; The positive polarity input termination reference voltage HalfREF (7.5V) of U111A, and be connected with the positive polarity input of U111B, the output of U111A is connected to the negative polarity input point of U111B, and be connected to power Vcc and reference ground FGND by resistance R 111 and capacitor C 52 respectively, the output of U111B is connected in power Vcc via resistance R 112; The output SHORTED of U5D is connected to two inputs of U5C, the output of U5C is received the base stage of NPN triode T4 by resistance R 36, the emitter of T4 connects with reference to ground FGND, the collector electrode of T4 is connected to reference to ground FGND by resistance R 33 and capacitor C 5, the anode of diode D1 is connected in DRIVE0, and negative electrode is connected in the node that R33 is connected with C5; R26 connects the negative electrode of power Vcc and diode D1.
Below narrate the operation principle with the soft connection of falling the grid voltage short-circuit protection function, soft shutoff drive circuit:
(1) soft connection process:
Short-circuit protection circuit inoperative in normal soft connection and soft turn off process: the SHORT signal is that low level means not to be short-circuited; while not being short-circuited; the output SHORTED of NAND gate U5D is high level; NAND gate U5C is output as low level; triode T4 is in off state; the voltage of capacitor C 5 equals power source voltage Vcc, and diode D1 is in cut-off state.
The soft thought of opening is to control the grid voltage rising of MOSFET, reaches the purpose of restriction capacitive load impulse current; When CMD3 becomes high level by low level, triode T5 saturation conduction, triode T2 turn-offs, power Vcc gives capacitor C 4 chargings by resistance R 27, R29, diode D2 and R34, resistance R 39 in parallel thereof, the DRIVE0 current potential rises gradually, through totem output stage and the resistance R 30 rear drive power MOSFETs that are comprised of triode T1 and T3.
(2) soft turn off process:
The thought of soft shutoff is to control the grid voltage slow decreasing of MOSFET, reaches the purpose that reduces the power MOSFET voltage stress; When CMD3 becomes low level by high level, triode T5 turn-offs, triode T2 saturation conduction, capacitor C 4 is by the collector electrode electric discharge of resistance R 29 and triode T2, the DRIVE0 current potential descends gradually, through totem output stage and the resistance R 30 rear drive power MOSFETs that are comprised of triode T1 and T3, the DRIVE1 current potential drops to the following rear power MOSFET of cut-in voltage and turn-offs.
(3) short-circuit protection process:
When load is short-circuited, short-circuit detecting circuit can detect load current: if load current is greater than set point (12 times of rated current), SHORT becomes high level; The tripped condition latch cicuit can latch short-circuit condition simultaneously, makes the FAULT signal remain low level, and it is low level that the action of state synthetic circuit makes the CMD3 signal; The rest-set flip-flop that NAND gate U5B and U5D form also latchs short-circuit condition, the SHORTED signal keeps low level before short-circuit condition resets always, and triode T4 keeps conducting, and the DRIVE0 current potential descends rapidly, the DRIVE1 current potential also descends rapidly, thereby allows power MOSFET turn-off.When CMD3 becomes low level; triode T6 saturation conduction; its collector electrode becomes low level; the delay circuit that U111A and U111B form is exported low level time delay a period of time of T6 collector electrode; and to make the SHORTED signal be high level; now short-circuit protection completes, and power MOSFET turn-offs, and waveform correlation as shown in Figure 6.
3. inverse time lag circuit and trip circuit immediately
The common working load electric current of the inverse-time overcurrent protection characteristic of DC solid-state power controller means with equation or the curve of tripping operation delay time, be typical inverse time protection curve of the present invention shown in Fig. 7: when load current is less than the rated current of 1.15-1.45 times, solid-state power controller keeps conducting state; When load current is greater than 1.15-1.45 doubly and is less than 8-12 times of rated current, square being inversely proportional to of tripping operation delay time and electric current; When load current is greater than 8-12 times, solid-state power controller trips immediately.
Fig. 8 has provided the inverse time lag circuit diagram, the output that the voltage of LCS is the current regulating circuit, LCS is via the negative polarity input of resistance R 14 concatenation operation amplifier U3C, the reference voltage that REF5 is 5V, resistance R 12 and R19 form voltage divider, the voltage of getting is connected in the positive polarity input of operational amplifier U3C by resistance R 17, resistance R 15 is connected to the output of U3C, capacitor C 3 is connected across the other end (being the positive polarity input that output stage is open-collector comparator U1C) of R15 and the negative polarity input of U3C, the negative polarity input of comparator U1C is LCS, output is connected in power Vcc through resistance R 11, LCS links the negative polarity input of open-collector comparator U1D simultaneously by the low pass filter consisted of resistance R _ f s1 and capacitor C fst1, power Vcc is connected to reference to ground FGND through resistance R 23 and resistance R 25, the positive polarity input that a bit is connected to U1D that R23 is connected with R25, the output of U1D and the output of U1C are connected in TRIP, as inverse time lag circuit and the output of trip circuit immediately.
Below narration inverse time lag circuit and the operation principle of trip circuit immediately:
(1) in while, overload not occurring, the LCS point voltage is greater than the voltage that the voltage divider that is comprised of R12 and R19 sets, and operational amplifier U3C is the device operate in open loop state as a comparison, and output approaches the magnitude of voltage of power source voltage Vcc, be greater than the voltage of U1C negative polarity input LCS, U1C exports high level; And because U1D now also can export high level, so TRIP is output as high level;
(2) when overload occurs but does not reach immediately trip protection point in load, the LCS point voltage is greater than the voltage that the voltage divider that is comprised of R12 and R19 sets, U3C is as integrator work, and U1C exports TRIP and becomes low level after the time of delay corresponding with overload magnification; When TRIP is low level, the tripped condition latch cicuit is at once by the TRIP state latch, and state synthetic circuit output low level, by the soft shutoff solid-state power controller of drive circuit;
(3) when the overload magnification of load reaches immediately trip-point (voltage divider that trip-point is comprised of resistance R 23 and resistance R 25 is immediately set), the output signal TRIP of comparator U1D becomes low level and produces trip signal, state synthetic circuit output low level, by the soft shutoff solid-state power controller of drive circuit.
4. sequential match circuit
Solid-state power controller must provide two state informations to host computer, and one is load current state (STATE1), and another is load voltage state (STATE2); STATE1 is exported by sequential match circuit and state feedback interface circuit by current regulating circuit and current status judgement; STATE2 is detected by load voltage and the judgement of load voltage state is exported by sequential match circuit and state feedback interface circuit.
Sequential match circuit concrete structure is as shown in Fig. 9 (a), input signal has 3: CMD3, LOAD0 and MOS0, wherein CMD3 is external control signal CMD and latchs the comprehensive later signal of inner tripped condition FAULT state, LOAD0 is the output of load current status determination circuit, and MOS0 is the output of load voltage status determination circuit; Output signal has 2: LOAD1 and MOS1; U2A, U2B, U2C and U2D are that output stage is open-collector comparator, and U8A, U8B, U8C and U8D are NAND gate, and U22A and U22B are d type flip flops.CMD3 is connected in the negative polarity input of U2A and the positive polarity input of U2C, and the positive polarity input of U2A, U2B and U2D is connected and is connected to reference voltage HalfREF (7.5V) with the negative polarity input of U2C; The output of U2A is connected to the negative polarity input of U2B, and connects with reference to ground FGND, by resistance R 72, connects power Vcc by capacitor C 23; The output of U2C connects the negative polarity input of U2D, and connects with reference to ground FGND, by resistance R 74, connects power Vcc by capacitor C 24; The output of U2B connects the input of U8A and U8B, and connects power Vcc by resistance R 73; The output of U2D connects the input of U8A and U8D, and connects power Vcc by resistance R 75; The output of NAND gate U8A connects the input of U8B and U8D, the output of U8B and U8D is connected two inputs of U8C, the output signal CLK of U8C is as the trigger end CLK of U22A and U22B, the D termination MOS0 of U22A, the D termination LOAD0 of U22B, the Q end output signal of U22A is MOS1, and the Q end output signal of U22B is LOAD1.
When CMD3 signal generation saltus step, no matter due to external control order CMD or load tripping operation or short circuit, cause, the circuit be comprised of U2A, U2B, U2C and U2D and U8A, U8B, U8C and U8D can time delay produce a rising edge CLK, can coordinate shown in Fig. 9 (b) simultaneously, this rising edge CLK triggers U22A and U22B, just can make the output (Q end) of U22A and U22B, the value of MOS1 is refreshed as MOS0, the value of LOAD1 is refreshed as LOAD0, and this process is simultaneously, has completed the synchronous output of state feedback.
5. electrify restoration circuit
Figure 10 is the electrify restoration circuit in the present invention, CMD is that opening of sending of host computer turn-offed order, receive the base stage of NPN triode T02 by resistance R 06, the emitter of T02 is connected in the base stage of NPN triode T03, the base stage of the collector electrode of T02 and T03 and NPN triode T01 is connected, and be connected in the 5V bias supply by resistance R 02, the emitter of T01 and T03 is connected in the reference ground of 5V bias supply, the T01 collector electrode connects the 5V bias supply by resistance R 01, resistance R 04 and capacitor C 02 series connection, another termination 5V bias supply of resistance R 04, the reference ground of another termination 5V bias supply of capacitor C 02, U14 is the d type flip flop with preset end (PRE) and clear terminal (CLR), Low level effective, the reference ground that the D end of U14 and clock end (CLK) are connected in the 5V bias supply, the clock end is connected in the collector electrode of T01, and preset end is connected in the node that C02 is connected with R04, U14's
end is connected in the input with door U20B, and another input of U20B is connected in the collector electrode of T01, and U20B is output as CMD1.
Below narrate the operation principle of electrify restoration circuit:
(1) in Figure 10, capacitor C 02 and resistance R 04 compose in series differential circuit, when the 5V bias supply powers on, the preset end of d type flip flop U14 remains low level, then to make preset terminal voltage rising be high level in capacitor C 02 charging, utilizes the low level pulse of the preset end of initial time that powers on to complete electrification reset;
(2) coordinate shown in Figure 11, when initial moment cmd signal is low level or unsettled, if now power supply powers on, the clear terminal of d type flip flop U14 is low level,
end output is high level always, and the electrification reset low level pulse of preset end can not affect
the output of end, now making CMD is high level, can obtain CMD1 and CMD is consistent;
(3) when initial moment cmd signal be high level, if now bias supply powers on, the clear terminal of U14 is high level, the low level pulse of preset end can by
end is set to low level, although now CMD is high level, due to
end is for low level, so CMD1 is low level; Only have first cmd signal is set to low level, the clear terminal of U14 sets low,
end is for high level, then to make CMD be that height just can make CMD1 and CMD be consistent.
6. magnetic buffer circuit
The present invention has used the method for magnetic isolation during to the order of solid-state power controller transmit button and state feedback at host computer, be the theory diagram of the first buffer circuit as shown in figure 12, the CMD1 signal is carried out to high frequency modulated, be delivered to the transformer secondary by pulse transformer, after the secondary demodulation, shaping is reduced into the switching signal before modulating again.Figure 13 is for realizing that circuit: CMD1 is for the switching signal after electrify restoration circuit was processed, PULSE1 is high frequency (150KHz-250KHz) pulse, CMD1 and PULSE1 link the input with door U20C, the output of U20C is connected in the base stage of NPN triode T9 and PNP triode T11, the collector electrode of T9 connects the 5V bias supply, and the collector electrode of T11 connects bias supply with reference to ground; The emitter of T9 is connected with the emitter of T11, and is connected in the base stage of NPN triode T10 by resistance R in parallel 49 and capacitor C ft3, and the emitter of T10 is connected in bias supply with reference to ground; The input of the same name of pulse transformer TF1 (1 end) is connected with the 5V bias supply, and different name input (2 end) is connected with the T10 collector electrode; The anode of voltage-stabiliser tube Z5 is connected with the 5V bias supply, and negative electrode is connected with diode D6 negative electrode, and the D6 anode is connected in 2 ends of TF1; The output of the same name of TF1 (4 end) is connected in the anode of diode D5, the negative electrode of D5 meets internal reference ground FGND by resistance R _ f in parallel 1 and Cf1, the negative electrode of D5 is connected in the base stage of NPN triode T8 simultaneously by resistance R 44, the collector electrode of T8 is connected in the base stage of NPN triode T7, and is connected in internal electric source Vcc by resistance R 45; The emitter of T7 and T8 is connected in internal reference ground FGND, and the collector electrode CMD2 of T7 is connected in internal electric source Vcc by resistance R 42.
Below narrate this circuit working principle:
When CMD1 is high level, the output of U20C is high-frequency pulse signal, through the drive circuit rear drive triode T10 high frequency break-make be comprised of triode T9, T11 and capacitor C ft3 and R49; During triode T10 conducting, the voltage that is added in transformer primary side equals bias supply voltage (5V); When triode T10 turn-offs, the voltage that is added in the transformer secondary is negative value, and the pressure drop that equals diode D1 adds the reverse breakdown voltage value of voltage-stabiliser tube Z5; So obtained that at the transformer secondary negative high-frequency impulse is just arranged, the direct voltage that must pulse by diode D5 and capacitor C f1 halfwave rectifier, Rf1 is dummy resistance, and T7 and T8 and R42 and R45 form shaping circuit, the direct voltage of pulsation is become to stable high level and open signal.
When CMD1 is low level, the output of U20 is always low level, and triode T10 turn-offs always, and the voltage of transformer primary secondary is zero always, so the voltage of capacitor C f1 is also zero, T8 is in off state, the T7 saturation conduction, and CMD2 is low level.
Waveform correlation as shown in figure 14.
7. be applicable to thick-film technique and the wiring technique of solid-state power controller
The present invention adopts polylaminate wiring technique, by thick-film techniques such as silk screen printing and sintering, makes resistance and electric capacity on alumina substrate, and the precision of resistance can reach 60%, can reach 5% after advancing laser resistor trimming, and temperature coefficient reaches 10
-4/ ℃, and assemble power MOSFET bare chip, discrete device and integrated circuit bare chip thereon; The better beryllium oxide ceramics of employing heat conductivility below power MOSFET, and power MOSFET is arranged on the place near shell edge, is beneficial to heat radiation; The conduction band of loop of power circuit part that flows through large electric current is as far as possible thick, short and near pin, to reduce conduction band resistance, reduces the wastage; The encapsulation of the additional 10# cold-rolled steel of whole circuit metal-back, and pour nitrogen, greatly reduced the volume and weight of solid-state power controller, increased reliability.
Above embodiment only, for explanation technological thought of the present invention, can not limit protection scope of the present invention with this, every technological thought proposed according to the present invention, and any change of doing on the technical scheme basis, within all falling into protection range of the present invention.
Claims (6)
1. a thick-film magnetic isolation direct current solid-state power controller, it is characterized in that: comprise power MOSFET, detect resistance, power diode, the TVS diode, the current regulating circuit, voltage detecting circuit, the voltage status decision circuitry, the current status decision circuitry, trip circuit immediately, the inverse time lag circuit, short-circuit detecting circuit, drive circuit, the state synthetic circuit, the tripped condition latch cicuit, time-delay reset circuit, the sequential match circuit, the DC/DC insulating power supply, the first buffer circuit, the second buffer circuit, the 3rd buffer circuit, the state feedback interface circuit, control signal interface circuit and electrify restoration circuit,
The drain electrode of power MOSFET connects the power input, and source electrode resistance after testing is connected to load and then arrive Power Groud, the anodic bonding Power Groud of power diode, negative electrode connection power take-off; The anode of TVS diode is connected to Power Groud, and negative electrode is connected to the power input;
The input of current regulating circuit is connected to the two ends of detecting resistance, and output is connected to respectively inverse time lag circuit, trip circuit, short-circuit detecting circuit and current status decision circuitry immediately; The output of voltage detecting circuit connects the voltage status decision circuitry; The all synchronously output after the processing of sequential match circuit of the output signal of aforesaid voltage status determination circuit and current status decision circuitry; The output signal of sequential match circuit is connected to the state feedback interface circuit through the second buffer circuit and the 3rd buffer circuit respectively, and the output signal of described state feedback interface circuit is load current status signal and the load voltage status signal that feeds back to host computer;
The inverse time lag circuit and immediately the output signal of trip circuit be input to the tripped condition latch cicuit, and the output signal of short-circuit detecting circuit also is connected to the tripped condition latch cicuit, the output signal of the output signal of this tripped condition latch cicuit and the first buffer circuit is input to the state synthetic circuit jointly, and the output signal of the output signal of state synthetic circuit and short-circuit detecting circuit jointly is input to and opens in soft shutoff drive circuit with falling the soft of grid voltage defencive function, this is soft opens the grid source electrode that soft shutoff drive circuit output is connected to power MOSFET, the input signal of state synthetic circuit also is connected to time-delay reset circuit as input signal simultaneously, the output signal of state synthetic circuit is sent to the sequential match circuit,
Outside control command is connected in the control signal interface circuit through electrify restoration circuit, the output of control signal interface circuit is connected in the first buffer circuit, the output signal of the first buffer circuit is connected to state synthetic circuit and time-delay reset circuit, and the output of time-delay reset circuit connects the tripped condition latch cicuit;
Electrify restoration circuit, control signal interface circuit, state feedback interface circuit are powered by outside 5V bias supply, the DC/DC insulating power supply boosts to 15V by outside 5V bias voltage, using the power MOSFET source electrode as internal reference ground, give following functional circuit module power supply: state synthetic circuit, time-delay reset circuit, sequential match circuit, short-circuit detecting circuit, inverse time lag circuit, trip circuit, tripped condition latch cicuit, drive circuit, voltage status decision circuitry, current status decision circuitry, voltage detecting circuit and current regulating circuit immediately.
2. thick-film magnetic isolation direct current solid-state power controller as claimed in claim 1, it is characterized in that: described drive circuit comprises soft connection and soft breaking circuit and falls the grid voltage short-circuit protection circuit, wherein, the structure of soft connection and soft breaking circuit is: control signal is connected the base stage of NPN the 5th triode through the three or five resistance, power supply connects the collector electrode of the 5th triode by the two or eight resistance, and the emitter of the 5th triode is connected with reference ground; The collector electrode of the 5th triode also respectively by the 31, four zero resistances are connected in the base stage of NPN second, six triodes, the second, the emitter of six triodes all with reference to ground is connected, and the collector electrode of second, six triodes is connected in power supply by the 27,32 resistance respectively; The two or nine resistance is from the collector electrode of the second triode, through the 4th electric capacity, the three or four resistance, three nine-day periods after the winter solstice resistance, arrive with reference to ground, and the three or four resistance wherein also forward be parallel with the second diode; The node that the two or nine resistance is connected with the 4th electric capacity is connected in the base stage of NPN the first triode and PNP the 3rd triode, and the emitter of first and third triode is connected, and the collector electrode of the first triode is connected to power supply, and the collector electrode of the 3rd triode is connected to reference to ground; One end of the 3rd zero resistance is connected with the emitter of first and third triode, the other end is connected to the grid of power MOSFET, at the grid of power MOSFET pseudo-ginseng resistance in parallel, after third and fourth voltage-stabiliser tube differential concatenation, be connected in parallel between the grid and source electrode of power MOSFET;
Described structure of falling the grid voltage short-circuit protection circuit is: the short-circuit condition signal that short-circuit detecting circuit sends connects the input of the first NAND gate, the collector electrode of the 6th triode connects another input of the first NAND gate and the negative polarity input that output stage is open-collector the first comparator, the output of the first NAND gate is connected to an input of the second NAND gate, and second, four NAND gate connect to form rest-set flip-flop; The positive polarity input termination reference voltage of the first comparator, and the positive polarity input that is open-collector the second comparator with output stage is connected, the output of the first comparator is connected to the negative polarity input point of the second comparator, and by first, resistance and the five or two electric capacity are connected to power supply and, with reference to ground, the output of the second comparator is connected in power supply via the one one two resistance one by one respectively; The output of the 4th NAND gate is connected to two inputs of the 3rd NAND gate, and the output of the 3rd NAND gate is received the base stage of NPN the 4th triode by the three or six resistance, the emitter of the 4th triode connects with reference to ground, the collector electrode of the 4th triode is connected to reference to ground by the three or three resistance and the 5th electric capacity, the anode of the first diode is connected in the node that the two or nine resistance is connected with the 4th electric capacity, and negative electrode is connected in the node that the three or three resistance is connected with the 5th electric capacity; The two or six resistance connects the negative electrode of power supply and the first diode.
3. thick-film magnetic isolation direct current solid-state power controller as claimed in claim 1 or 2, the structure that it is characterized in that described inverse time lag circuit is: the output of current regulating circuit connects the negative polarity input of the 3rd operational amplifier and the negative polarity input of open-collector the 3rd comparator via the one or four resistance, the one or two, the one or nine resistance is composed in series voltage divider, the 5V reference voltage is carried out to dividing potential drop, the voltage of getting is connected in the positive polarity input of the 3rd operational amplifier by the one or seven resistance, the output of the 3rd operational amplifier is connected in the positive polarity input of the 3rd comparator through the one or five resistance, the 3rd electric capacity is connected across the positive polarity input of the 3rd comparator and the negative polarity input of the 3rd operational amplifier, the output of the 3rd comparator is connected in power supply through the one one resistance, the negative polarity input of open-collector the 4th comparator is linked in the output of current regulating circuit by low pass filter, power supply is connected to reference to ground through the 23,25 resistance, the positive polarity input that a bit is connected to the 4th comparator that the 23,25 resistance are connected, and the output of the 4th comparator is connected with the output of the 3rd comparator, as inverse time lag circuit and the output of trip circuit immediately.
4. thick-film magnetic isolation direct current solid-state power controller as claimed in claim 1, the structure that it is characterized in that described sequential match circuit is: five, six, seven, eight comparators are all that output stage is open-collector comparator, the output of state synthetic circuit connects the negative polarity input of the 5th comparator and the positive polarity input of the 7th comparator, and the positive polarity input of the 5th, six, eight comparators is connected and is connected to reference voltage with the negative polarity input of the 7th comparator; The output of the 5th comparator connects the negative polarity input of the 6th comparator, and connects with reference to ground, by the seven or two resistance, connects power supply by the two or three electric capacity; The output of the 7th comparator connects the negative polarity input of the 8th comparator, and connects with reference to ground, by the seven or four resistance, connects power supply by the two or four electric capacity; The output of the 6th comparator connects the input of the 5th, six NAND gate, and connects power supply by the seven or three resistance; The output of the 8th comparator connects the input of the 5th, eight NAND gate, and connects power supply by the Seventh Five-Year Plan resistance; The output of the 5th NAND gate connects the input of the 6th, eight NAND gate, and the output of the 6th, eight NAND gate connects the input of the 7th NAND gate, the output of the 7th NAND gate also connects the trigger end of first and second d type flip flop, and the output of the D termination voltage status determination circuit of the first d type flip flop, the Q end connects the input of the 3rd buffer circuit, the output of the D termination current status decision circuitry of the second d type flip flop, the Q end connects the input of the second buffer circuit.
5. thick-film magnetic isolation direct current solid-state power controller as claimed in claim 1, the structure that it is characterized in that described electrify restoration circuit is: the base stage of NPN the second triode is received in the shutoff order of opening that host computer sends by the 6th resistance, the emitter of this second triode is connected in the base stage of NPN the 3rd triode, and second, the base stage of the collector electrode of three triodes and NPN the first triode is connected, and be connected in the 5V bias supply by the second resistance, first, the emitter of three triodes is connected in the reference ground of 5V bias supply, the collector electrode of the first triode connects the 5V bias supply by the first resistance, the 4th resistance and the second capacitances in series, another termination 5V bias supply of the 4th resistance, the reference ground of another termination 5V bias supply of the second electric capacity, the reference ground that the D end of 3d flip-flop and clock end are connected in the 5V bias supply, clear terminal is connected in the collector electrode of the first triode, and preset end is connected in the node that the second electric capacity is connected with the 4th resistance, and 3d flip-flop
end be connected in first with the input of door, and this first with another input be connected the collector electrode of the first triode, its output is the input of connection control signal interface circuit.
6. thick-film magnetic isolation direct current solid-state power controller as described as any one in claim 1, the structure that it is characterized in that described the first buffer circuit is: second with the input of door respectively output and the high-frequency impulse of connection control signal interface circuit, output connects the base stage of NPN the 9th triode and PNP the one one triode, the collector electrode of the 9th triode connects the 5V bias supply, and the collector electrode of the one one triode connects bias supply with reference to ground; The emitter of the 9th triode is connected with the emitter of the one one triode, the four or nine resistance and the first shunt capacitance composition parallel branch parallel with one another, one end of this parallel branch connects the emitter of the 9th triode, the other end connects the base stage of NPN the tenth triode, and the emitter of the tenth triode is connected in bias supply with reference to ground; The input of the same name on the former limit of pulse transformer is connected with the 5V bias supply, and the different name input on former limit is connected with the collector electrode of the tenth triode; The anode of the 5th voltage-stabiliser tube is connected with the 5V bias supply, and negative electrode is connected with the negative electrode of the 6th diode, and the anode of the 6th diode is connected in the different name input on the former limit of pulse transformer; The output of the same name of pulse transformer secondary connects the anode of the 5th diode, and the different name output connects internal reference ground; The negative electrode of the 5th diode connects internal reference ground by the first parallel resistance, the negative electrode of the 5th diode connects internal reference ground by the second shunt capacitance, be connected in the base stage of NPN the 8th triode by the four or four resistance simultaneously, the collector electrode of the 8th triode is connected in the base stage of NPN the 7th triode, and is connected in internal electric source by the four or five resistance; Seven, the emitter of eight triodes is connected in internal reference ground, and the collector electrode of the 7th triode is connected in internal electric source by the four or two resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110237263 CN102340246B (en) | 2011-08-18 | 2011-08-18 | Thick-film magnetic isolation direct current solid-state power controller |
Applications Claiming Priority (1)
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| CN 201110237263 CN102340246B (en) | 2011-08-18 | 2011-08-18 | Thick-film magnetic isolation direct current solid-state power controller |
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| CN102340246B true CN102340246B (en) | 2013-11-06 |
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| CN102769272A (en) * | 2012-07-18 | 2012-11-07 | 北京三一自动化技术有限责任公司 | Failure latching and resetting system of power converter and power converter |
| CN104320001B (en) * | 2014-10-29 | 2016-11-30 | 广州金升阳科技有限公司 | A kind of magnetic isolation feedback circuit |
| CN104753033B (en) * | 2015-04-16 | 2018-05-04 | 重庆梅安森科技股份有限公司 | A kind of power supply output overcurrent and overvoltage protective device and its anti-interference method |
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| CN107015556A (en) * | 2017-04-28 | 2017-08-04 | 莱诺斯科技（北京）股份有限公司 | A kind of bus solid-state power controller test device |
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| CN108649805B (en) * | 2018-06-14 | 2023-11-10 | 成都信息工程大学 | High-power DC-DC power supply conversion circuit based on isolation and delay technology |
| CN109217856B (en) * | 2018-08-23 | 2022-05-31 | 北京机械设备研究所 | Power electronic switch |
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| CN109787044B (en) * | 2019-04-02 | 2023-09-22 | 佛山市顺德区信辉达电子有限公司 | Semi-intelligent tripolar on-off leakage protection plug |
| CN110460012A (en) * | 2019-08-20 | 2019-11-15 | 南京志卓电子科技有限公司 | A kind of power device isolating and protecting device |
| CN110646780B (en) * | 2019-09-30 | 2022-12-06 | 南京邮电大学 | Photon synchronous detection circuit applied to single photon flight time ranging system and preparation method thereof |
| CN112367072A (en) * | 2020-10-26 | 2021-02-12 | 上海空间电源研究所 | Anti-saturation magnetic isolation circuit |
| CN113342122A (en) * | 2021-06-04 | 2021-09-03 | 上海空间电源研究所 | Long-delay all-solid-state power tuner for space |
| CN113708748B (en) * | 2021-07-22 | 2024-06-25 | 北京卫星制造厂有限公司 | Special integrated controller for solid electronic switch |
| CN113777984B (en) * | 2021-09-02 | 2023-12-15 | 郑州中科集成电路与系统应用研究院 | DC high-voltage multipath solid-state power controller |
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| US4665355A (en) * | 1986-09-15 | 1987-05-12 | Rockwell International Corporation | Off line capacitor-divider power supply for solid state power controller |
| CN1667951A (en) * | 2005-03-08 | 2005-09-14 | 南京航空航天大学 | DC solid-state power switch circuit |
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| WO2007106062A2 (en) * | 2005-02-16 | 2007-09-20 | Leach International Corporation | Power distribution system using solid state power controllers |
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| US4665355A (en) * | 1986-09-15 | 1987-05-12 | Rockwell International Corporation | Off line capacitor-divider power supply for solid state power controller |
| CN1667951A (en) * | 2005-03-08 | 2005-09-14 | 南京航空航天大学 | DC solid-state power switch circuit |
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| CN102340246A (en) | 2012-02-01 |
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