CN102308371A - 具有覆盖层的经离子注入的衬底及方法 - Google Patents

具有覆盖层的经离子注入的衬底及方法 Download PDF

Info

Publication number
CN102308371A
CN102308371A CN2009801564831A CN200980156483A CN102308371A CN 102308371 A CN102308371 A CN 102308371A CN 2009801564831 A CN2009801564831 A CN 2009801564831A CN 200980156483 A CN200980156483 A CN 200980156483A CN 102308371 A CN102308371 A CN 102308371A
Authority
CN
China
Prior art keywords
ion
substrate
cover layer
gas
processing procedure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2009801564831A
Other languages
English (en)
Inventor
J·I·戴尔阿瓜博尼奇尔
T·普恩
R·斯查特尔卡普
M·孚德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of CN102308371A publication Critical patent/CN102308371A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Plasma & Fusion (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Physical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

在一离子注入方法中,衬底放置于制程区,而离子注入衬底的区域中以形成离子注入区。多孔覆盖层沉积于离子注入区上。在退火制程期间,将衬底退火以挥发至少百分之八十上覆于离子注入区的多孔覆盖层。中间产物包括衬底、衬底上的多个离子注入区、以及覆盖离子注入区的多孔覆盖层。

Description

具有覆盖层的经离子注入的衬底及方法
【技术领域】
本发明各实施例涉及在衬底中注入离子以形成离子注入区。
【背景技术】
离子注入区形成在衬底上以改变衬底区域材料的能带间隙级。例如,将硼离子、磷离子、砷离子和其他材料注入硅或复合半导体材料中以形成半导体区域。在另一实例,离子被注入到包含石英、III族或V族化合物(例如:砷化镓)的衬底中,以形成太阳能电池板的光伏电池(photovoltaic cell)。又一实例中,离子被注入到包含氮化镓的衬底,以形成显示面板的发光二极体(LED)。
然而,在某些离子注入制程中,很大比例的注入离子在离子注入制程期间或后续的制程中蒸发或挥发。举例言之,注入离子的扩散与挥发可在离子注入制程完成后执行的退火制程发生。又一实例中,包含硅片的衬底的离子注入区经退火以便更均匀分布注入区中的离子、电活化注入物、并移除晶格缺陷。这种退火制程可藉由加热衬底至温度至少约950℃来执行。然而,在退火制程期间施加的热量可能造成所注入的离子从衬底挥发,特别是针对浅结中的高离子浓度。
基于上述原因和其他缺点以及尽管各种离子注入方法与结构的发展,仍亟待寻求更进一步改良离子注入技术。
【发明内容】
在一离子注入方法中,衬底放置于制程区,且离子注入衬底的区域中以形成离子注入区。多孔覆盖层沉积在离子注入区上方。在退火制程期间,将衬底退火以挥发至少百分之八十覆于离子注入区的多孔覆盖层。中间产物包括衬底、衬底上的多个离子注入区、以及覆盖离子注入区的多孔覆盖层。
【附图说明】
参考以下描述、所附权利要求以及示出本发明各实例的附图,本发明的这些特征、方面及优点将更浅显易懂。然而,须了解的是,每一特征大体上均可适用于本发明,不仅限于特定图示内容,且本发明包含这些特征的任意结合。
图1A及图1B是在衬底上执行离子注入制程以在衬底中形成多个离子注入区的横截面侧图;
图1C是图1B中衬底的横截面侧图,显示多孔覆盖层沉积在离子注入区上方以形成中间产物;
图1D是图1C中衬底的横截面侧图,显示离子注入区的退火处理,以及覆盖层在退火制程中蒸发;
图1E是图1D中的衬底在覆盖层已从离子注入区蒸发后的横截面侧图;
图2是离子注入、覆盖及蒸发制程的流程图;
图3是包含PMOS与NMOS电晶体的积体电路横截面侧图;以及
图4是适合实行离子注入及覆盖制程的设备的横截面侧图。
【具体实施方式】
如图1A、图1B所示,在用于半导体、太阳能电池板、LED及其它应用的衬底40的制造过程中,多个离子注入区44a,b在衬底上形成。衬底40可以是诸如下述任意一种或多种的材料:氧化硅、碳化硅、晶体硅、应变硅、硅锗、掺杂或非掺杂多晶硅、掺杂或非掺杂硅片、掺杂硅、锗、砷化镓、氮化镓、玻璃、蓝宝石(sapphire)和石英的。衬底40可具有不同尺寸,例如:衬底40可以是直径为200或300毫米的圆形晶片,或矩形或方形面板。
注入到离子注入区44a,b中的离子45取决于衬底40的应用。举例而言,通过注入n型与p型掺杂剂至包含硅片的衬底40,离子注入区44a,b可用以形成积体电路晶片的电晶体的栅极和/或源极漏极结构。在注入到硅中时形成n型掺杂剂的合适离子45包含例如至少以下至少一种:磷、砷、锑及上述的组合。适合形成p型掺杂剂的离子45包含例如以下至少一种:硼、铝、镓、铊、铟、硅及上述的组合。因此,当P型导电掺杂剂(如:硼)注入到在相邻于先前已掺杂n型掺杂剂(如:砷或磷)的另一离子注入区(图未显示)的离子注入区44a,b的硅中时,沿着这两个区域的介面形成一p-n结。离子可注入到选定的剂量水平,例如:从1×1014atoms/cm3到1×1017atoms/cm3的剂量。
在注入制程中,将衬底40置于制程区46,并且将衬底温度维持在约25℃至约400℃之间。引入制程气体至制程区46,以提供要注入的离子源种类。制程气体亦可包含挥发性种类,例如:氟和/或氢。举例来说,制程气体可以含有包含砷、硼、磷等的氟化物和/或氢化物的离子注入气体。离子注入气体可以包含,例如,AsF3、AsH3、B2H6、BF3、SiH4、SiF4、PH3、AsF5、P2H5、PO3、PF3、PF5及CF4。亦可组合特定气体的氟化物或氢化物,例如:BF3+B2H6、PH3+PF3、AsF3+AsH3、SiF4+SiH4或GeF4+GeH4。在一实施例中,离子注入气体的流速可在约2sccm至约1000sccm之间。
制程气体可进而包含惰性或非反应性气体,诸如:N2、Ar、He、Xe、Kr。惰性或非反应性气体促使离子撞击以增加制程气体碰撞并减少离子种类再结合。惰性或非反应性气体的流速可在从约10sccm至约1200sccm的范围内。
制程气体可进一步包含含氮气体以助于形成更易于从制程室抽出的挥发性副产物。含氮气体可包含NO、NO2、NH3、N2、N2O及上述的混合物。含氮气体可以流速约10sccm至约500sccm来供给。
离子化该制程气体以形成等离子体48,该等离子体48含有要注入衬底40的原子种类的离子45。藉由施以电压,加速这些离子(如图1A,1B中箭头50所示)使这些离子通过制程区46以形成有力地撞击于制程区上的离子,并使这些离子进入衬底40的暴露区52以形成离子注入区。制程气体可以源功率及偏功率或源功率和偏功率的结合来激发,源功率为施于绕着制程区46的天线(未显示)的感应耦合功率,偏功率为施于绕着制程区46的电极(未显示)的电容耦合功率。典型地,源功率自制程气体产生等离子体48,而偏功率更进而解离制程气体并加速朝向衬底40的解离离子45。设定源功率及偏功率到预先定义能阶,以使离子种类被驱动进入衬底40的期望深度。具有低离子能量的解离离子被注入到距衬底表面小于
Figure BPA00001420626000041
的浅深度,例如,距衬底表面约
Figure BPA00001420626000042
至约
Figure BPA00001420626000043
具有来自高射频功率(例如:高于约10KeV)的高离子能量的解离离子可被注入到衬底40中距衬底40表面大于
Figure BPA00001420626000044
的深度。在一实例中,以约10至约12000伏特的RF电压将源功率维持在约50至约2000瓦、偏功率维持在约50至约11000瓦。
在一示例实施例中,可在制程区46中将砷离子注入衬底40。将衬底40的温度维持在低于30℃。在该制程中,含有含砷气体(例如AsH3)的制程气体被引入制程区46。制程气体的压力维持在约3mTorr至约2Torr左右,例如:约20mTorr。藉由将绕着制程区46的天线(未显示)施加约200至约8000伏特(例如:约6000伏特)的电压,制程气体被激发而形成等离子体。施加于天线的源功率可为约100至约3000瓦,例如:约1000瓦。所形成的等离子体包含激发的砷离子,这些激发的砷离子被注入衬底40以形成包含砷注入区的离子注入区44a,b。将砷离子以至少约1×1016atoms/cm3的剂量注入到距衬底表面小于的深度。
在一预期实例中,可将硼离子从包括含硼气体(例如:三氟化硼气体(BF3))的制程气体的等离子体注入衬底40中。激发该制程气体以产生具有足以解离BF3分子的能量密度的等离子体,从而形成B+离子与BF+离子,亦可能形成BF2+。制程气体的压力维持在约5mTorr至约3Torr。十硼烷粉末的蒸汽压在室温下约为0.1Torr等级,并且十硼烷粉末在高于温度100℃时产生实质蒸汽压,十硼烷粉末亦可作为硼离子源或用来补充硼离子气体源。
在代表示例性硼注入制程的另一预期实例中,制程气体包含BF3、SiH4,BF3、SiH4,BF3、SiH4,BF3、SiH4藉由B3+、BF2+、BF2 2+、F、Si4及H+形式的等离子体解离为离子种类。由SiH4气体提供的活化氢种类与解离的氟种类及其它解离的副产物反应,以形成HF或其他类型的挥发性种类,因此防止氟种类及其它类型的副产物被注入衬底40。从而,选择SiH4气流以防止过量或解离的硅离子在衬底上形成不想要的硅膜。在一实施例中,制程气体包含BF3和SiH4,BF3和SiH4的气流比例为约1∶50至约1∶100。举例而言,BF3流速可从约50至约400sccm,而SiH4流速可从约1至约20sccm。源射频功率(source RFpower)设定在约100瓦至约2000瓦,而偏射频功率(bias RF power)则设定在约100伏特至约12000伏特。所形成的等离子体将硼离子注入衬底40以形成包含硼注入区的离子注入区44a,b。
在又一预期性实例中,掺杂磷可以使用包含含磷气体的制程气体来进行,含磷气体例如是氟化磷气体(诸如:PF3或PF5)或磷氢化物气体(例如:PH3)。将制程气体引入制程区46,并将制程气体的压力维持在约10mTorr至约3Torr。举例而言,PF3气体可以流速约50sccm至约1000sccm来供应。源射频功率可设定在约100瓦至约3000瓦,而偏射频功率则设定在约100伏特至约12000伏特。所形成的等离子体将磷离子注入衬底40以形成包含磷注入区的离子注入区44a,b。
在一示例性实施例中,在离子注入之后,多孔覆盖层54沉积在离子注入区44a,b上,如图2的流程图所示。多孔覆盖层54覆盖离子注入区44a,b以形成中间产物55,如图1C所示。多孔覆盖层54用以防止注入到离子注入区44a,b中的离子在后续过程中(例如:退火制程)挥发。然而,退火制程可造成大部分的注入离子自衬底40蒸发或挥发,特别是当注入离子为低质量、低结合能量或对衬底为低溶解度时。多孔覆盖层54被发现可减少注入离子的挥发耗损,从而即使在退火制程之后,也能保存较大比例的注入在离子注入区44a,b内的离子。
还发现多孔覆盖层54可以在退火制程期间或之后轻易蒸发及移除,并相信多孔覆盖层54的孔隙度允许自下层析出的蒸发物质更轻易散逸且通过多孔覆盖层54的细孔。这防止多孔覆盖层54在强力结合或黏着下层时,自附接的下层分层。而且,因多数体积被空洞的细孔空间所取代,故多孔覆盖层54质量较小,且因此需较少能量即可将多孔覆盖层54从衬底40蒸发。因此,在一态样中,多孔覆盖层54包含至少百分之二十或甚至至少百分之五十的孔隙度。更进而言之,多孔覆盖层54可具有连续状细孔,连续状细孔的孔隙体积为至少百分之二十或甚至至少约百分之五十。连续状细孔是所期望的,因连续状细孔更易允许蒸发气体和副产物通过多孔覆盖层54散逸而不造成分层(delamination)。
在一态样中,多孔覆盖层54包含含硅及含氧物质。在此态样中,多孔覆盖层54的沉积是通过将包含含硅及含氧气体的制程气体引入至制程区46中,并通过利用等离子体增强化学气相沉积法(PECVD)或微波增强化学气相沉积法(MECVD)沉积二氧化硅来激发制程气体以形成等离子体。尽管描述二氧化硅以说明当前制程,应注意的是其他物质亦可用来形成多孔覆盖层54。此外,所沉积的硅和氧物质可包含碳、氢,或者甚至氮。举例而言,二氧化硅形成的多孔覆盖层54可利用包含含硅气体的制程气体来沉积,含硅气体诸如:硅烷(SiH4)、二硅烷、二氯硅烷、三氯硅烷、四乙基正硅烷、甲基硅烷(CH3SiH3)、二甲基甲硅烷((CH3)2SiH2)、三甲基甲硅烷((CH3)3SiH)、二乙基硅烷((C2H5)2SiH2)、丙硅烷(C3H8SiH3)、乙烯甲基硅烷(CH2=CH)CH3SiH2)、1,1,2,2-四甲基二硅烷(HSi(CH3)2-Si(CH3)2H)、六甲基二硅烷(CH3)3Si-Si(CH3)3)、1,1,2,2,3,3-六甲基三硅烷(H(CH3)2Si-Si(CH3)2-SiH(CH3)2)、1,1,2,3,3-五甲基三硅烷(H(CH3)2Si-SiH(CH3)-SiH(CH3)2)及其它硅烷相关化合物。制程气体亦可包含含氧气体,诸如:氧气(O2)、氧化亚氮(N2O)、臭氧(O3)及二氧化碳(CO2)。
中间产物55包含沉积的包含含硅/氧物质的多孔覆盖层54,包含含硅/氧物质的多孔覆盖层54具有均匀分散于二氧化硅层中的微观气洞。有一代表例是,包含多孔二氧化硅的多孔覆盖层54沉积在同一制程区46的衬底40上。将包含含硅气体及含氧气体的制程气体引入制程区46。例如,制程气体可包含硅烷和氧,硅烷和氧的体积流速比从约1∶1至约1∶10,或甚至从约1∶2至约1∶6。例如,硅烷流速可从约5至约50sccm,而氧流速可从约20至约200sccm。可选地,氩可被加入制程气体中。当加入氩时,硅烷与氧的体积流速比维持在上述水平,而充足的氩被加入以维持氧气和氩气体积流速比自约1∶4至约4∶1。制程气体压力维持在约5mTorr至约500mTorr,例如约100mTorr。等离子体自以约200至约10000伏特(例如约1000伏特)的电压且以约1000瓦至约10000瓦(例如约8000瓦)的功率水平施加于绕着制程区46的天线的射频能量产生。衬底40温度维持在低于30℃,以使多孔覆盖层54在衬底上形成。
在另一预期实例中,多孔覆盖层54用含有含硅气体的制程气体形成,其中含硅气体包括三甲基甲硅烷((CH3)3-SiH)和氧。三甲基甲硅烷以流速约20至约100sccm供应而氧以流速约10至约200sccm供应。制程气体亦可包含流速为约10至约5000sccm的氦或氮。室压维持在约1至约15Torr之间。施加约100至约900瓦的RF功率源。衬底40温度维持在约300℃至约450℃以沉积多孔覆盖层54。
在又一预期实例中,利用包含四乙基正硅烷(TEOS)及氧的制程气体沉积多孔覆盖层54,其中四乙基正硅烷的流速约200至约2000sccm,氧的流速约200至约2000sccm。以约300至约1200瓦的射频能量启动等离子体。衬底40温度维持在约300至约500℃。
如图1D与图2所示,退火处理上方覆盖有多孔覆盖层54的离子注入区44a,b,以更均匀分布注入到离子注入区中的离子。举例而言,在退火制程中,离子浓度的变动可由1×1017atm/cm2减至1×1013atm/cm2。退火制程亦可移除或减少离子注入区44a,b中的晶格缺陷,其中这些晶格缺陷可因注入离子的能量撞击而引发。退火制程也可用以活化所注入的离子。在一示例性退火制程中,衬底40被加热至至少约1000℃的温度,或者甚至从约800℃加热至约1300℃。合适的退火制程可以实施约5分钟。
在退火制程中,至少一部份多孔覆盖层54在热处理过程挥发。在一态样中,覆盖在离子注入区上的至少百分之八十的多孔覆盖层54在退火时挥发。例如,在退火期间,至少百分之九十的多孔覆盖层54可被挥发而仍留下至少百分之六十的注入离子在离子注入区44a,b中。因此,多孔覆盖层54保留离子注入区44a,b中的离子,而同时蒸发衬底40。有利的是,该制程使大量的注入离子得以保留,而移除基本上全部的多孔覆盖层54。
尽管大部分的多孔覆盖层54在退火中间产物以形成下一阶段产物期间挥发,未被蒸发的多孔覆盖层54残余物质,如图1D所示,可通过干法净化或等离子体清洗制程或湿法蚀刻制程移除。在适合的干法净化或等离子体清洗制程中,包含氟(例如:CF4)的制程气体可被引入制程区46,并且自该制程气体产生的等离子体被用来清除衬底40表面的残余含硅及含氧物质。如图1E所示,结果衬底40包含离子注入区44a,b,离子注入区44a,b具有均匀分布的离子浓度、减少的晶格缺陷、及干净表面58。
图3示出包括PMOS与NMOS电晶体的积体电路的一个示例性实施例,其中PMOS与NMOS电晶体可使用当前制程来制造。在此结构中,包含硅片的衬底40具有活化半导体层100a,b,活化半导体层100a,b可以是块半导体硅物质(如图所示)或形成于覆于衬底40上的绝缘层上的硅岛(未显示)。PMOS电晶体102在活化层100的轻n-掺杂区100a形成,而NMOS电晶体202在活化层100的轻p-掺杂区100b形成。p-掺杂区100b及n-掺杂区100a以一蚀刻于活化层内并填充绝缘物质(如:二氧化硅)的浅隔离沟槽106彼此绝缘。PMOS电晶体102亦含有重p-掺杂源极及漏极区108a、108b于活化层中,以及由n-掺杂沟道112隔离的重p-掺杂源极及漏极延伸区110a、110b。
举例而言,离子注入区44a,b可以是轻n-掺杂区100a、轻p-掺杂区100b、重p-掺杂源极及漏极区108a、108b、及由n-掺杂沟道112隔离的重p-掺杂源极及漏极延伸区110a、110b中的任何一个。在此态样中,紧接于沉积任一离子注入区44a,b之后,多孔覆盖层(未显示)被用来覆盖离子注入区44a,b以防止离子在后续可实施于衬底40上的退火制程期间挥发。之后,将具有离子注入区44a,b的衬底40退火。在退火制程中,基本上全部的多孔覆盖层54蒸发。之后,其他层被沉积、被蚀刻或以其他方式被处理至衬底40上。
在PMOS电晶体102中,多晶硅栅电极114覆盖在沟道112上,并藉由薄栅二氧化硅层116与沟道112隔离。包含例如钛硅化物或钴硅化物的栅接点118覆盖于栅电极114上。也包含例如钛硅化物或钴硅化物的源极接点区120形成于源极区108a中。氮化硅绝缘层122覆盖于源极及漏极区108a、108b上,并包围栅电极结构114、116、118。二氧化硅岛124位于绝缘层122中。薄氮化硅蚀刻停止层126覆盖于PMOS电晶体102上方。上覆多互连层132的底部绝缘层130覆盖于蚀刻停止层126上方。在绝缘层130形成后,化学机械研磨制程可用来平坦化它的顶面130a。金属源极接点134,例如:锡,垂直延伸穿过绝缘层130,并穿过蚀刻停止层126到钛硅化物源极接点区120。绝缘层可能是二氧化硅(SiO2)或含二氧化硅的组合物,诸如:硅酸磷玻璃(PSG)、硅酸硼玻璃(BSG)或碳掺杂硅酸盐玻璃(CSG)。这种组合物可使用制程气体在等离子体加强沉积制程中形成,其中该制程气体含有含氧气体、硅前体(例如:硅烷)、磷前体气体(PH3)、硼前体气体(B2H6)或含碳气体。
NMOS电晶体202包含活化层中的重n-掺杂源极及漏极区208b、208a以及由p-掺杂沟道212隔离的重n-掺杂源极及漏极延伸区210b、210a。多晶硅栅电极214覆盖沟道212并通过薄栅二氧化硅层216与沟道212隔绝。包含例如钛硅化物的栅接点218覆盖于栅电极214上方。钛硅化物源极接点区220形成于源极区208b中。氮化硅绝缘层222上覆于源极及漏极区208b、208a,并包围栅电极结构214、216、218。二氧化硅岛224位于绝缘层222中。薄氮化硅蚀刻停止层226覆盖于NMOS电晶体202上方。上覆多互连层132的底部绝缘层130覆盖于蚀刻停止层226上方。金属(例如:TiN)漏极接点234垂直延伸穿过绝缘层130,并穿过蚀刻停止层226到钛硅化物源极接点区220。
图4所示为衬底处理装置300的示例性实施例,该装置适合于注入离子以在衬底40形成离子注入区44a,b,并能够在同一制程区46的注入区44a,b上方沉积多孔覆盖层54。衬底处理装置300可以是,例如:环状源等离子体浸渍离子注入装置,例如:可购自美国加州圣克拉拉市之应用材料公司的P31TM。合适装置请参见,例如:Al-Bayati等人于2004年12月1日申请且公开号为2005/0191828的美国专利申请案,该2005/0191828的美国专利申请案的全部内容以引用方式并入本文。
一般而言,装置300包含处理室310,处理室310由圆柱状侧壁312和圆盘状室顶314包围。处理室310内的衬底支撑件316包含衬底接受面318,用以支撑衬底40以便于在制程区46中处理衬底。衬底支撑件316可以是包含电极319的静电夹盘317,电极319埋于或由介电板321所覆盖。电极319由夹持DC电压源产生器323赋予功率。
制程气体(制程气体包含含有要被离子注入衬底40的种类的离子注入气体)经由气体分布器320被引入制程区46。位于处理室310的室顶314上的气体分布器320藉由连结至气体分布板325的气体歧管324接收制程气体。气体歧管324由个别气体供应器326a-j所馈入,气体供应器326a-j各自由一组质量流控制器327a-j所控制,该质量流控制器327a-j设定每一气体供应器326a-j的气流以控制制程气体的组成。举例而言,个别气体供应器326a-j可包含供应含砷气体、含磷气体、含硼气体、含碳气体、氢、氧、氮、硅烷、氢化锗气体、氪、氙、氩或其他气体。气体供应器326a-j可包含不同含掺杂剂气体,包括:含硼氟化物、含硼氢化物、含磷氟化物及含磷氢化物。其他气体包括用于共同注入(氢与氦)、物质增强(氮)、表面钝化或共同注入(含硅或锗或碳的氟化物),以及光阻移除和/或处理室清洁(氧气)等的气体。真空泵328耦接于在衬底支撑件316和侧壁312之间界定的抽取环带330。
在衬底40上方的制程区46中激发制程气体。适合在制程区46激发制程气体的气体激发器333包含一对外部凹曲导管334、336,外部凹曲导管334、336建立凹曲环状路径以供等离子体流通过且交切于制程区46。每一导管334、336具有一对末端338,末端338耦接至处理室310的相对侧。每一导管334、336为中空导电管并具有一D.C.绝缘环340,D.C.绝缘环340防止在导管两末端间形成闭合回路导电路径。每一导管334、336的环状部分为环状磁芯342所围绕。励磁线圈344围绕磁芯342并经由阻抗匹配装置348耦接至RF功率源346。两个耦接至各自磁芯344的RF功率源346可具有两种稍微不同的频率。举例而言,藉由施加频率为400kHz及15MHz的RF电流,气体激发器333可自制程气体形成感应耦合等离子体。耦接自RF功率产生器346的RF电源在于封闭环状路径制造等离子体离子流,其中该封闭环状路径延伸穿过每个个别导管334、336并穿过制程区46。这些离子流以各自RF功率源的频率震荡。
在离子注入制程期间,气体激发器333自RF功率产生器346向凹曲导管334、336施加源功率,以在导管内及制程区46内建立环状等离子体流。藉偏压功率产生器349,将偏压功率经由阻抗匹配电路350施于衬底支撑件316。离子注入深度由RF偏压功率产生器349所施加的衬底偏压确定。离子注入速度或通量,亦即每秒每平方厘米注入的离子数,由等离子体密度所确定,该等离子体密度则由RF功率产生器346所施加的RF功率水平所控制。衬底40中累积的注入剂量(离子/cm2)系由通量及该通量所维持的时间两者所确定。
当多孔覆盖层54沉积在衬底40上,源功率产生器346可在不需使用偏压功率产生器349的情况下即可用以产生等离子体而不需加速离子朝向衬底40。在该制程中,制程气体解离形成彼此互相反应或与衬底表面反应的离子、中性粒子及其它种类,以在衬底40上沉积多孔覆盖层54。
不论是离子注入或覆盖层沉积制程,不同能量源可用以形成等离子体、激发离子及活化制程气体。例如,取代感应耦合,等离子体亦可使用任何常规或高密度等离子体产生源(举例包括:电容式等离子体源、电子回旋加速器共振、或变压耦合等离子体)而产生。因此,本发明的当前权利要求的范围不应被限制于在此所举的示例性装置。
本发明在此藉由参考所列若干不同实施例加以叙述,然而,其他情形亦为可能。例如:亦可使用不同离子注入制程。同时,如本领域普通技术人员所知,不同物质亦可用于覆盖层54。因此,所附权利要求的精神与范围不应被局限于在此所描述的实施例。

Claims (13)

1.一种离子注入方法,包括:
(a)将离子注入衬底的区域内以形成离子注入区;
(b)沉积多孔覆盖层于所述离子注入区上;以及
(c)将所述衬底退火,并在退火制程期间使覆盖所述离子注入区的所述多孔覆盖层的至少百分之八十挥发。
2.如权利要求1所述的方法,其特征在于,(c)步骤包含将所述衬底上的所述离子注入区退火,以挥发所述多孔覆盖层的至少百分之九十,而在所述离子注入区保留所注入离子的至少百分之六十。
3.如权利要求1所述的方法,其特征在于,(b)步骤包含沉积多孔覆盖层,所述多孔覆盖层具有以下特性中的至少一种:
(i)孔隙度为至少百分之二十;或
(ii)连续状细孔的孔隙体积为至少百分之二十。
4.如权利要求1所述的方法,其特征在于,(b)步骤包含:通过将制程气体引入所述制程区并在室温激发所述制程气体形成等离子体来沉积所述多孔覆盖层。
5.如权利要求1所述的方法,其特征在于,(b)步骤包含:通过将包括含硅气体及含氧气体的制程气体引入所述制程区,激发所述制程气体以形成等离子体,并维持所述衬底温度低于30℃,以沉积包含二氧化硅的多孔覆盖层。
6.如权利要求5所述的方法,其特征在于,包括下述至少一个:
(i)含硅气体包括硅烷,且含氧气体包括氧气;
(ii)将所述制程气体的压力维持在约5mTorr至约500mTorr;或
(iii)通过以约1000至约10000瓦的功率水平向绕着所述制程区的天线提供功率来形成所述等离子体。
7.如权利要求1所述的方法,其特征在于,(a)步骤包括在下列步骤中的至少一个中注入离子:
(i)注入包括砷、硼或磷的离子;
(ii)以从1×1014atoms/cm3到1×1017atoms/cm3的剂量注入离子;
(iii)将离子注入到距所述衬底的表面少于
Figure FPA00001420625900021
的深度;
(iv)通过将包括含砷气体的制程气体引入所述制程区内、激发所述制程气体形成等离子体并维持所述衬底的温度低于30℃,以注入砷离子。
8.如权利要求7所述的方法,其特征在于,步骤(iv)包括以下步骤中的至少一个:
(i)将所述制程气体的压力维持在从约3mTorr到约5Torr;或
(ii)以约200至约8000伏特的电压向绕着所述制程区的天线提供功率。
9.如权利要求1所述的方法,其特征在于,步骤(a)与步骤(b)藉由将所述衬底放置于处理室的制程区中来执行。
10.一种中间产物,包括:
(a)衬底;
(b)所述衬底上的多个离子注入区;以及
(c)多孔覆盖层,所述多孔覆盖层覆盖在所述离子注入区上。
11.如权利要求10所述的中间产物,其特征在于,所述多孔覆盖层具有下列特性中的至少一种:
(i)孔隙度为至少百分之二十;或
(ii)连续状细孔的孔隙体积为至少百分之二十。
12.如权利要求10所述的中间产物,其特征在于,所述离子注入区包括下列特性中的至少一种:
(i)离子包括砷、硼或磷;
(ii)以从1×1014atoms/cm3到1×1017atoms/cm3的剂量注入离子;
(iii)将离子注入到距所述衬底的表面少于
Figure FPA00001420625900022
的深度;或
(iv)p-型掺杂区邻近于n-型掺杂区。
13.如权利要求10所述的中间产物,其特征在于,所述衬底包含氧化硅、碳化硅、晶体硅、应变硅、硅锗、掺杂或非掺杂多晶硅、掺杂或非掺杂硅片、掺杂硅、锗、砷化镓、氮化镓、玻璃、蓝宝石(sapphire)和石英中的至少一种。
CN2009801564831A 2009-02-06 2009-12-29 具有覆盖层的经离子注入的衬底及方法 Pending CN102308371A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/367,306 US7858503B2 (en) 2009-02-06 2009-02-06 Ion implanted substrate having capping layer and method
US12/367,306 2009-02-06
PCT/US2009/069754 WO2010090693A2 (en) 2009-02-06 2009-12-29 Ion implanted substrate having capping layer and method

Publications (1)

Publication Number Publication Date
CN102308371A true CN102308371A (zh) 2012-01-04

Family

ID=42539730

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009801564831A Pending CN102308371A (zh) 2009-02-06 2009-12-29 具有覆盖层的经离子注入的衬底及方法

Country Status (7)

Country Link
US (2) US7858503B2 (zh)
EP (1) EP2394293A4 (zh)
JP (1) JP2012517698A (zh)
KR (1) KR20110122700A (zh)
CN (1) CN102308371A (zh)
TW (1) TWI469190B (zh)
WO (1) WO2010090693A2 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119316A (zh) * 2014-03-03 2019-01-01 普莱克斯技术有限公司 含硼掺杂剂组合物、使用其的系统和方法
CN110085499A (zh) * 2014-09-01 2019-08-02 恩特格里斯公司 利用增强源技术进行磷或砷离子植入

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8471307B2 (en) * 2008-06-13 2013-06-25 Texas Instruments Incorporated In-situ carbon doped e-SiGeCB stack for MOS transistor
DE102008035816B4 (de) 2008-07-31 2011-08-25 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG, 01109 Leistungssteigerung in PMOS- und NMOS-Transistoren durch Verwendung eines eingebetteten verformten Halbleitermaterials
US7977224B2 (en) * 2008-12-03 2011-07-12 The United States Of America As Represented By The Secretary Of The Army Method using multiple layer annealing cap for fabricating group III-nitride semiconductor device structures and devices formed thereby
US7858503B2 (en) * 2009-02-06 2010-12-28 Applied Materials, Inc. Ion implanted substrate having capping layer and method
WO2011056515A2 (en) * 2009-10-27 2011-05-12 Advanced Technology Materials, Inc. Ion implantation system and method
JP5238780B2 (ja) * 2010-09-17 2013-07-17 株式会社東芝 磁気記録媒体とその製造方法及び磁気記録装置
TWI462285B (zh) * 2010-12-30 2014-11-21 Lextar Electronics Corp 半導體結構及其製造方法
WO2012129454A2 (en) * 2011-03-24 2012-09-27 Advanced Technology Materials, Inc. Cluster ion implantation of arsenic and phosphorus
US9011968B2 (en) 2011-09-16 2015-04-21 Empire Technology Development Llc Alteration of graphene defects
US9812291B2 (en) 2012-02-14 2017-11-07 Entegris, Inc. Alternate materials and mixtures to minimize phosphorus buildup in implant applications
TWI522490B (zh) * 2012-05-10 2016-02-21 應用材料股份有限公司 利用微波電漿化學氣相沈積在基板上沈積膜的方法
SG11201601015RA (en) * 2013-08-16 2016-03-30 Entegris Inc Silicon implantation in substrates and provision of silicon precursor compositions therefor
US10460941B2 (en) * 2016-11-08 2019-10-29 Varian Semiconductor Equipment Associates, Inc. Plasma doping using a solid dopant source
CN108962734B (zh) * 2018-06-27 2021-01-01 武汉华星光电半导体显示技术有限公司 一种多晶硅半导体层的制备方法、薄膜晶体管及制备方法
US11127601B2 (en) 2019-05-21 2021-09-21 Applied Materials, Inc. Phosphorus fugitive emission control
US20230420219A1 (en) * 2022-06-27 2023-12-28 Austin Lo Plasma-Enhanced Chemical Vapor Deposition for Structurally-Complex Substrates

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5552342A (en) * 1993-08-20 1996-09-03 Nippondenso Co., Ltd. Method for producing a contact hole in a semiconductor device using reflow and etch
JP2004111638A (ja) * 2002-09-18 2004-04-08 Sharp Corp 半導体基板の製造方法およびこの方法を用いた半導体装置の製造方法および半導体装置
KR20050035981A (ko) * 2003-10-14 2005-04-20 매그나칩 반도체 유한회사 반도체 소자의 제조 방법
US20050158957A1 (en) * 2004-01-21 2005-07-21 Jack Hwang Creating shallow junction transistors
CN101208792A (zh) * 2005-06-27 2008-06-25 加利福尼亚大学董事会 制造浅沟槽的方法

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2662452B2 (ja) * 1990-08-04 1997-10-15 住友電気工業株式会社 化合物半導体ウエハの熱処理方法
US6171945B1 (en) * 1998-10-22 2001-01-09 Applied Materials, Inc. CVD nanoporous silica low dielectric constant films
EP1094506A3 (en) * 1999-10-18 2004-03-03 Applied Materials, Inc. Capping layer for extreme low dielectric constant films
US6875687B1 (en) * 1999-10-18 2005-04-05 Applied Materials, Inc. Capping layer for extreme low dielectric constant films
JP4382219B2 (ja) * 1999-10-29 2009-12-09 日本電気株式会社 多結晶シリコン膜の水素化処理方法および薄膜トランジスタの製造方法
US6541367B1 (en) * 2000-01-18 2003-04-01 Applied Materials, Inc. Very low dielectric constant plasma-enhanced CVD films
US6559070B1 (en) * 2000-04-11 2003-05-06 Applied Materials, Inc. Mesoporous silica films with mobile ion gettering and accelerated processing
US7166524B2 (en) * 2000-08-11 2007-01-23 Applied Materials, Inc. Method for ion implanting insulator material to reduce dielectric constant
US7294563B2 (en) * 2000-08-10 2007-11-13 Applied Materials, Inc. Semiconductor on insulator vertical transistor fabrication and doping process
US6841006B2 (en) * 2001-08-23 2005-01-11 Applied Materials, Inc. Atmospheric substrate processing apparatus for depositing multiple layers on a substrate
US7431585B2 (en) * 2002-01-24 2008-10-07 Applied Materials, Inc. Apparatus and method for heating substrates
US6656840B2 (en) * 2002-04-29 2003-12-02 Applied Materials Inc. Method for forming silicon containing layers on a substrate
US6936551B2 (en) * 2002-05-08 2005-08-30 Applied Materials Inc. Methods and apparatus for E-beam treatment used to fabricate integrated circuit devices
JP2007516607A (ja) * 2003-05-29 2007-06-21 アプライド マテリアルズ インコーポレイテッド 埋込式導波路検出器
KR20060031801A (ko) * 2003-05-29 2006-04-13 어플라이드 머티어리얼스, 인코포레이티드 불순물 베이스의 광도파관 검출기
US7611996B2 (en) * 2004-03-31 2009-11-03 Applied Materials, Inc. Multi-stage curing of low K nano-porous films
US20050227502A1 (en) * 2004-04-12 2005-10-13 Applied Materials, Inc. Method for forming an ultra low dielectric film by forming an organosilicon matrix and large porogens as a template for increased porosity
US20080194086A1 (en) * 2004-06-04 2008-08-14 Yuichiro Sasaki Method of Introducing Impurity
US7413957B2 (en) * 2004-06-24 2008-08-19 Applied Materials, Inc. Methods for forming a transistor
US7316960B2 (en) * 2004-07-13 2008-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Strain enhanced ultra shallow junction formation
US20060019032A1 (en) 2004-07-23 2006-01-26 Yaxin Wang Low thermal budget silicon nitride formation for advance transistor fabrication
US7422776B2 (en) * 2004-08-24 2008-09-09 Applied Materials, Inc. Low temperature process to produce low-K dielectrics with low stress by plasma-enhanced chemical vapor deposition (PECVD)
US7501354B2 (en) * 2005-01-18 2009-03-10 Applied Materials, Inc. Formation of low K material utilizing process having readily cleaned by-products
US7365378B2 (en) * 2005-03-31 2008-04-29 International Business Machines Corporation MOSFET structure with ultra-low K spacer
EP1897132A4 (en) * 2005-06-27 2014-11-26 Univ California METHOD FOR MANUFACTURING SMALL DEEP TRENCHES
US20070254491A1 (en) * 2006-04-29 2007-11-01 Applied Materials, Inc. Protective layer for a low k dielectric film and methods of forming the same
US20080009141A1 (en) * 2006-07-05 2008-01-10 International Business Machines Corporation Methods to form SiCOH or SiCNH dielectrics and structures including the same
US7297376B1 (en) * 2006-07-07 2007-11-20 Applied Materials, Inc. Method to reduce gas-phase reactions in a PECVD process with silicon and organic precursors to deposit defect-free initial layers
JP5134223B2 (ja) * 2006-09-06 2013-01-30 株式会社日立国際電気 半導体装置の製造方法及び基板処理装置
US7410916B2 (en) * 2006-11-21 2008-08-12 Applied Materials, Inc. Method of improving initiation layer for low-k dielectric film by digital liquid flow meter
WO2008077020A2 (en) * 2006-12-18 2008-06-26 Applied Materials, Inc. Safe handling of low energy, high dose arsenic, phosphorus, and boron implanted wafers
CN101595559B (zh) * 2007-01-29 2012-01-04 应用材料股份有限公司 形成镶嵌结构的方法
WO2009045964A1 (en) * 2007-10-01 2009-04-09 Applied Materials, Inc. Low temperature conformal oxide formation and applications
US20100087062A1 (en) * 2008-10-06 2010-04-08 Applied Materials, Inc. High temperature bd development for memory applications
US7858503B2 (en) * 2009-02-06 2010-12-28 Applied Materials, Inc. Ion implanted substrate having capping layer and method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5552342A (en) * 1993-08-20 1996-09-03 Nippondenso Co., Ltd. Method for producing a contact hole in a semiconductor device using reflow and etch
JP2004111638A (ja) * 2002-09-18 2004-04-08 Sharp Corp 半導体基板の製造方法およびこの方法を用いた半導体装置の製造方法および半導体装置
KR20050035981A (ko) * 2003-10-14 2005-04-20 매그나칩 반도체 유한회사 반도체 소자의 제조 방법
US20050158957A1 (en) * 2004-01-21 2005-07-21 Jack Hwang Creating shallow junction transistors
CN101208792A (zh) * 2005-06-27 2008-06-25 加利福尼亚大学董事会 制造浅沟槽的方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119316A (zh) * 2014-03-03 2019-01-01 普莱克斯技术有限公司 含硼掺杂剂组合物、使用其的系统和方法
CN109119316B (zh) * 2014-03-03 2022-02-08 普莱克斯技术有限公司 含硼掺杂剂组合物、使用其的系统和方法
CN110085499A (zh) * 2014-09-01 2019-08-02 恩特格里斯公司 利用增强源技术进行磷或砷离子植入
CN110085499B (zh) * 2014-09-01 2022-03-04 恩特格里斯公司 利用增强源技术进行磷或砷离子植入

Also Published As

Publication number Publication date
US7858503B2 (en) 2010-12-28
KR20110122700A (ko) 2011-11-10
US20100200954A1 (en) 2010-08-12
US20110092058A1 (en) 2011-04-21
EP2394293A2 (en) 2011-12-14
US8198180B2 (en) 2012-06-12
WO2010090693A3 (en) 2010-10-14
WO2010090693A2 (en) 2010-08-12
JP2012517698A (ja) 2012-08-02
EP2394293A4 (en) 2012-12-12
TWI469190B (zh) 2015-01-11
TW201034059A (en) 2010-09-16

Similar Documents

Publication Publication Date Title
CN102308371A (zh) 具有覆盖层的经离子注入的衬底及方法
US6846745B1 (en) High-density plasma process for filling high aspect ratio structures
US9754779B1 (en) Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US8501605B2 (en) Methods and apparatus for conformal doping
KR101519036B1 (ko) 프로세스 챔버에 코팅하기 위한 장치 및 방법
US8298887B2 (en) High mobility monolithic p-i-n diodes
US6596654B1 (en) Gap fill for high aspect ratio structures
US7482245B1 (en) Stress profile modulation in STI gap fill
US9799749B1 (en) Vertical transport FET devices with uniform bottom spacer
US20130260564A1 (en) Insensitive dry removal process for semiconductor integration
CN107980172B (zh) Vnand拉伸厚teos氧化物
TW201735256A (zh) 製造用於半導體應用的環繞式水平閘極裝置的奈米線的方法
US7001854B1 (en) Hydrogen-based phosphosilicate glass process for gap fill of high aspect ratio structures
US9478437B2 (en) Methods for repairing low-k dielectrics using carbon plasma immersion
US8288257B2 (en) Doping profile modification in P3I process
US20020187628A1 (en) Low k interlevel dielectric layer fabrication methods
US5763021A (en) Method of forming a dielectric film
CN102203912A (zh) 改善p3i腔室中共形掺杂的方法
KR100759649B1 (ko) 고 밀도 화학 기상 증착법을 이용하여 재료를 증착하는방법 및 갭을 충진시키는 방법
US9059245B2 (en) Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides
US9312167B1 (en) Air-gap structure formation with ultra low-k dielectric layer on PECVD low-k chamber
US20120302048A1 (en) Pre or post-implant plasma treatment for plasma immersed ion implantation process
Gweon et al. Effect of DC bias voltage on the characteristics of low temperature silicon–nitride films deposited by internal linear antenna inductively coupled plasma source
US11393689B2 (en) Method for forming spacers of a transistor
Xia et al. Thin Film Growth Equipment

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120104