CN102306684B - Selective emitter of a kind of three grades of doped level and preparation method thereof - Google Patents
Selective emitter of a kind of three grades of doped level and preparation method thereof Download PDFInfo
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- CN102306684B CN102306684B CN201110276579.0A CN201110276579A CN102306684B CN 102306684 B CN102306684 B CN 102306684B CN 201110276579 A CN201110276579 A CN 201110276579A CN 102306684 B CN102306684 B CN 102306684B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
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Abstract
The present invention relates to a kind of selective emitter and preparation method thereof, be applicable to the preparation of crystalline silicon solar battery selective emitter.Secondary doping selective emitter Problems existing is prepared for printing doping method, as adulterate effect by indirectly to extend influence large, ink reaction is residual many, the rear silicon chip of the diffusion not problem such as easy cleaning, the present invention makes full use of the function difference characteristic of solar cell metal electrode main line and by-pass, to adopt adulterated oil ink print containing the printed patterns of low rate main line of stopping out on silicon chip, after Overheating Treatment, the selective emitting electrode structure of three grades of doped level can be prepared: the by-pass 1 covering ink and the main line graphic array 3 covering ink obtain severe doping; Non-electrode region 2 without ink obtains slight doping; Main line white space 4 without ink obtains medium doped.This method can reduce by more than 20% consumption of adulterating ink, thus effectively reduces indirectly extending influence from main line region ink, and ink reaction residue tails off, and after diffusion, silicon chip more easily cleans up.
Description
Art
The present invention relates to a kind of selective emitter its preparation method of three grades of doped level, be applicable to the selective emitter preparation of crystal-silicon solar cell.
Background technology
The impurity element mixing opposite types on the top layer of P type or N-type silicon chip can prepare the core texture of the crystalline silicon sun: PN junction, this doping thin layer is also referred to as emitter.Relative to the same sex emitter of top layer Uniform Doped, selective emitter can make solar cell obtain higher photoelectric conversion efficiency.Current selective emitter mostly is secondary doped structure: on silicon chip metal electrode to be prepared region and near carry out severe doping, and slightly to adulterate in non-electrode region.Its preparation method has mask diffusion method, anti-etching method, laser doping method, printing doping method etc., wherein printing doping method adopts complete electrode pattern to print doping ink, main line region is covered by ink completely, and main line area accounts for the nearly half of whole electrode area, cause doping quantity of ink in main line region many and concentrated, during High temperature diffusion, this region in a large number impurity element more than needed evaporate in atmosphere, comparatively serious to the remote-effects in the non-electrode region of main line periphery, cause selective doping poor effect, and ink reaction residue is more, after diffusion, silicon chip is not easily cleaned up.
Summary of the invention
The object of the invention is: overcome above-mentioned printing doping method and prepare Second Order Selectivity emitter Problems existing, propose selective emitter of a kind of three grades of doped structures and preparation method thereof, can requirement on industrial application be met.
The technical solution used in the present invention is:
The main line pattern of low rate of stopping out is adopted to substitute conventional main line pattern of stopping out completely, by adulterated oil ink print on pending silicon chip, after Overheating Treatment, the by-pass region covering ink and the main line graphic array region covering ink can form severe doping, the non-electrode region not covering ink forms slight doping, and the main line white space not covering ink then forms medium doped.Like this, whole selective emitter has severe, moderate, slight three grades of doped structures.
Above-mentioned three grades of doped level selective emitting electrode structures have taken into full account the function difference of crystal-silicon solar cell metal electrode main line and by-pass, the by-pass region of silicon chip obtains severe doping, the ohmic contact of silicon chip and metal electrode by-pass can be improved, be beneficial to collected current; And main line region is severe doping and moderate intersection, enough sintering junction depths can be ensured, although with the contact performance of metal electrode main line is slightly poor, but this affects the performance of solar cell hardly, this is because the Main Function of metal electrode main line collects the electric current on metal electrode by-pass, instead of from silicon substrate collected current.
The invention has the beneficial effects as follows: can reduce by the doping ink total burn-off of more than 20%, reduce the impact of indirect diffusion couple doping effect, the reaction residue of ink tails off, and after diffusion, silicon chip is more prone to clean up, and is applicable to the preparation of crystalline silicon solar battery selective emitter.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is further described
Fig. 1 is the ink distribution situation schematic diagram that in the present invention, silicon chip adulterates
In figure, 1. cover the by-pass of ink; 2. without the non-electrode region of ink; 3. cover the main line graphic array region of ink; 4. without the main line white space of ink.
Specific implementation method
First, doping ink is printed onto pending silicon chip front surface according to specific pattern, and this specific printed patterns comprises four parts: the by-pass 1 covering ink; Cover the main line graphic array region 3 of ink, these figures are distributed in main line region relatively uniformly, and its shape comprises rectangle, but is not limited only to rectangle, and also can be circle, polygon, linear etc., their area sums account for 10% ~ 60% of main line area; Without the main line white space 4 of ink; Without the non-electrode region 3 of ink.The live width of main line and by-pass is not less than corresponding metal electrode main line and the live width of by-pass.
Then, the silicon chip printing doping ink is carried out middle Low Temperature Heat Treatment, and temperature is: between 100 DEG C ~ 400 DEG C, make the solvent evaporated away in ink, and this process can be carried out in special equipment, also slowly can be sent in the process of diffusion furnace at silicon chip and complete.
Finally, above-mentioned silicon chip is slowly sent into high temperature dispersing furnace, diffusion temperature: 800 DEG C ~ 950 DEG C, in 20 minutes ~ 120 minutes processing time, whole process silicon chip remains in stove.
Like this, acquisition severe is adulterated by the by-pass region 1 covered by ink and main line graphic array region 3, and its square resistance is: 20 Ω/ ~ 50 Ω/; The indirect diffusion be subject to without the non-electrode region 2 of ink is less, formed slightly adulterate, can be able to pass into during High temperature diffusion take impurity source gas to regulate doping level, its square resistance is: 60 Ω/ ~ 150 Ω/; Main line white space 4 without ink obtains medium doped because of the more indirect diffusion be subject to from graphic array region 3 ink, and its square resistance is between severe doped region and slight doped region.
Claims (4)
1. the preparation method of the selective emitter of three grades of doped level, it is characterized in that comprising following steps: doping ink is printed onto on silicon chip according to specific pattern, wherein specific pattern comprises main line graphic array region, main line white space, by-pass region and non-electrode region, then silicon chip is heat-treated, severe doping is obtained in main line graphic array region and by-pass region, medium doped is obtained at main line white space, slight doping is obtained, the obtained selective emitter possessing severe, moderate, slight three grades of doped level in non-electrode region.
2. the preparation method of the selective emitter of three grades of doped level as claimed in claim 1, is characterized in that: described main line graphic array region is made up of rectangle, circle, ellipse, polygon and lines, and its area accounts for the 10%-60% of described main line area.
3. the preparation method of the selective emitter of three grades of doped level as claimed in claim 1, is characterized in that: it is High temperature diffusion two processes that the Low Temperature Heat Treatment of 100 DEG C-400 DEG C and temperature are 800 DEG C-950 DEG C, the time is 20 minutes-120 minutes that described heat treatment comprises temperature.
4. the preparation method of the selective emitter of three grades of doped level as claimed in claim 1, it is characterized in that: after described heat treatment completes, by-pass region silicon chip covering ink and the main line graphic array region covering ink obtain severe doping, and its square resistance is: 20 Ω/ ~ 50 Ω/; The non-electrode region covered without ink obtains slight doping, and its square resistance is: 60 Ω/ ~ 150 Ω/; The main line white space covered without ink obtains medium doped, and its square resistance is between the square resistance and the square resistance of slight doped region of above-mentioned severe doped region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110276579.0A CN102306684B (en) | 2011-09-19 | 2011-09-19 | Selective emitter of a kind of three grades of doped level and preparation method thereof |
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| CN201110276579.0A CN102306684B (en) | 2011-09-19 | 2011-09-19 | Selective emitter of a kind of three grades of doped level and preparation method thereof |
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| CN102306684A CN102306684A (en) | 2012-01-04 |
| CN102306684B true CN102306684B (en) | 2016-01-20 |
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| CN110010704B (en) * | 2018-12-11 | 2022-07-15 | 艾尔碧全球绿色科技有限公司 | Multicolor solar power generation module and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1241298A (en) * | 1996-12-24 | 2000-01-12 | 依麦克Vzw | Semiconductor device with selectively diffused regions |
| CN101523615A (en) * | 2006-08-22 | 2009-09-02 | Bp太阳能旗舰股份有限公司 | Photovoltaic cell and production thereof |
| CN201490199U (en) * | 2009-08-04 | 2010-05-26 | 天威新能源(成都)电池有限公司 | Crystalline silicon solar battery of selective emitter |
| CN101826573A (en) * | 2009-12-25 | 2010-09-08 | 欧贝黎新能源科技股份有限公司 | Method for preparing semiconductor secondary grid-metal primary grid crystalline silicon solar battery |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8129216B2 (en) * | 2009-04-29 | 2012-03-06 | International Business Machines Corporation | Method of manufacturing solar cell with doping patterns and contacts |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1241298A (en) * | 1996-12-24 | 2000-01-12 | 依麦克Vzw | Semiconductor device with selectively diffused regions |
| CN101523615A (en) * | 2006-08-22 | 2009-09-02 | Bp太阳能旗舰股份有限公司 | Photovoltaic cell and production thereof |
| CN201490199U (en) * | 2009-08-04 | 2010-05-26 | 天威新能源(成都)电池有限公司 | Crystalline silicon solar battery of selective emitter |
| CN101826573A (en) * | 2009-12-25 | 2010-09-08 | 欧贝黎新能源科技股份有限公司 | Method for preparing semiconductor secondary grid-metal primary grid crystalline silicon solar battery |
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Owner name: SUZHOU SOLARING TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: LIU FENG Effective date: 20130802 |
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Effective date of registration: 20130802 Address after: Wujiang Economic Development Zone, Suzhou City, Jiangsu province 215200 Pang Pang Jin Road No. 1801 gold industrial square 2 Applicant after: Suzhou SolaRing Technology Co., Ltd. Address before: 104 room 800, solar energy research institute, physics building, Shanghai Jiao Tong University, 200240 Dongchuan Road, Shanghai, Minhang District Applicant before: Liu Feng |
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