CN102306127A - Novel method for identifying and initializing DDRIII (double-data-rate III) memory - Google Patents
Novel method for identifying and initializing DDRIII (double-data-rate III) memory Download PDFInfo
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Abstract
The invention relates to a novel method for identifying and initializing a DDRIII (double-data-rate III) memory. The DDRIII memory is a memory bare chip, a CPLD (complex programmable logic device) is used for storing related information of a memory chip, and a data storage format has four different points on the basis of an SPD (serial presence detection) specification; a local parallel bus which is usually arranged on a processor is adopted for the processor to access the CPLD, a system start-up program bootloader of the processor reads the memory-related information stored in the CPLD by virtue of the local parallel bus, the read information is used for initializing a memory controller, and storage of the memory-related information and a logic interface accessed by the bus of the memory are realized by carrying out logics in the CPLD. The novel method for identifying and initializing the DDRIII (double-data-rate III) memory provided by the invention can be used for reducing development difficulty, expandability of a circuit design is better, debugging is simple and convenient, and selection range of production materials is wider.
Description
Technical field
The present invention relates to identification of DDRIII internal memory and initialization technique field in the Embedded System Design, is a kind of novel DDRIII internal memory identification and initial method specifically.
Background technology
In the Embedded System Design, increasing use DDRIII (the Double Data Rate synchronous DRAM third generation) internal memory, and because space and reliability reasons generally all are that the DDRIII memory chip is affixed on the circuit board.As everyone knows; Be different from other chips; The DDRIII memory chip itself is that interface accessing and the inner identification number that memory chip can be set yet are not provided; So; If in the time of need using and discern the internal memory of different model and amount of capacity during the system single board design; Just face the identification of internal memory and read the problem with allocate memory controller correlation timing parameter, can not be correct identify internal memory, initialization internal memory that just can not be correct.
In traditional Embedded System Design; One of method that solves correct identification DDRIII memory problem is to use the DDRIII memory chip of fixing a kind of model; Initialization data is solidificated in the start-up code; The shortcoming of this method is that development difficulty is big; Debugging cycle is long; Production material buying scope is little, and the producer's production capacity influence that is subject to supply.
Another kind of method commonly used; Such as memory bar; Be to use the erasable formula ROM (read-only memory) of a slice electronics EEPROM; Store according to parameters such as certain data format (SPD (series arrangement detection) standard that electronic component industrial combination meeting JEDEC formulates) the memory capacity size that internal memory is relevant, type of memory, sequential, physical sizes; Processor reads this information through I2C (internal integration circuit) interface, and BootLoader (system start-up program) uses these information initializings DDRIII controller and memory chip.With respect to Embedded System Design; The shortcoming of this method is dumb; EEPROM will be welded on the circuit board; After the product approval; Change a kind of model memory chip, its content is also wanted corresponding renewal, and it is inconvenient that EEPROM is upgraded in programming; Need upgrade the configuration of time sequence parameter during debugging repeatedly, that is not just more.
Summary of the invention
To the defective that exists in the prior art, the object of the present invention is to provide a kind of novel DDRIII internal memory identification and initial method, reduce development difficulty, the circuit design extensibility is better, debugs simple and conveniently, and the production material range of choice is wider.
For reaching above purpose, the technical scheme that the present invention takes is:
A kind of novel DDRIII internal memory identification and initial method; Save as the internal memory nude film in the said DDRIII; It is characterized in that: adopt programmable logic device (CPLD) stored memory chip relevant information, and data memory format has 4 differences on series arrangement detection SPD normative foundation:
E, 1 place, address are the version numbers of PPD;
F, 3 places, address, definition be the pattern of memory chip group access, non-buffer-type is still deposited type;
G, 32 places, address, definition be the corresponding coding of memory chip manufacturer;
H, address 33 to 125 and address 128 to 255 all are the subsequent use of definition;
The data memory format that this kind is new is called parallel configuration and surveys the PPD standard,
The local parallel bus that the bus of processor access programmable logic device (CPLD) adopts processor all to possess usually,
The system start-up program bootloader program of processor reads the internal memory relevant information that is stored in the CPLD through local parallel bus, uses the information that reads that Memory Controller Hub is carried out initialization then,
The storage of internal memory relevant information and bus access logic interfacing thereof realize through in CPLD, doing logic.
On the basis of technique scheme, the internal memory relevant information in the said CPLD of being stored in comprises at least: the density of memory chip and physics sheet select the line number of number, chip address and columns, time sequence parameter, the pattern of memory chip group access, memory chip manufacturer correspondence to encode.
On the basis of technique scheme, the CPLD logic is set address and the data width that bootloader will visit, and the internal memory relevant information that will be stored in the CPLD according to the address arrangement order of setting reads out.
On the basis of technique scheme, address and data width that CPLD logic setting bootloader will visit are got 8 bit data width and 8 bit address width.
On the basis of technique scheme; Utilize the file destination of CPLD to organize jtag interface to pass through PC client cables real-time online download function, change the configuration of the memory parameters of the needs adjustment in the internal memory relevant information that is stored in the CPLD through its joint test behavior.
On the basis of technique scheme, concrete steps are:
Step 1 has disposed PPD, and logic is compiled into file destination, and the file destination of compiling is downloaded cable through JTAG and downloaded among the CPLD,
Step 2, with processor and CPLD place circuit reset or re-power, the beginning test process,
Step 3, the BootLoader program reads memory parameters through local parallel bus, and its internal processes calculates the register value that processor needs automatically according to the information of reading, with the automatic initialization of register of the controller of One's name is legion and start,
Step 4, the user tests memory read-write through debug port, as tests unsuccessfully, returns, and the PPD configuration parameter is revised in inspection, and repeating step 1 is to step 4, until testing successfully again.
Novel DDRIII internal memory identification of the present invention and initial method adopt new storage mode and bus access mode, the reduction development difficulty, and the circuit design extensibility is better, debugs simple and conveniently, and the production material range of choice is wider.
Description of drawings
The present invention has following accompanying drawing:
The local parallel bus interface principle schematic of Fig. 1,
Fig. 2 DDRIII initialization debugging process flow diagram.
Embodiment
Below in conjunction with accompanying drawing the present invention is done further explain.
Novel DDRIII internal memory identification of the present invention and initial method; The storage medium of stored memory chip relevant information adopts CPLD (programmable logic device (PLD)); Data memory format and DDR3SPD standard have only 4 different; We claim that the data memory format of this redetermination is PPD (parallel configuration an is surveyed) standard; These 4 differences are specifically: 1 place, address; The SPD standard is a SPD version number, and the PPD standard is the version number of PPD; 3 places, address, the SPD normalized definition be the type of memory modules, the PPD normalized definition be the pattern of memory chip group access, non-buffer-type is still deposited type; 32 places, address, the SPD normalized definition be subsequent use, the PPD normalized definition be the corresponding coding of memory chip manufacturer; It all is the subsequent use of definition with address 128 to 255 that last point is not both address in the PPD standard 33 to 125, and some has the definition particular content in the SPD standard, has plenty of the subsequent use of definition.The local parallel bus (the present invention only is applicable to the processor of local parallel bus) that the bus of processor access storage medium (being CPLD) adopts processor all to possess usually.
The bootloader program of processor (system start-up program) can read the internal memory relevant information that is stored in the CPLD through local parallel bus; The line number of selecting number, chip address such as the density and the physics sheet of memory chip and columns, time sequence parameter or the like use the information that reads that Memory Controller Hub is carried out initialization then.And the storage of internal memory relevant information and bus access logic interfacing thereof realize through in CPLD, doing logic.
Here the dual core processor P2020 with Freescale is an example, and DDRIII message transmission rate 667MT/s uses 2 physics sheet choosings, and the DDR3 memory chip uses the MT41J128M16HA-15E (memory chip model, individual particle capacity 2G bit) of 8 companies of Micron Technology.The instance of FPGA (Field Programmable Gate Array) descriptive language that provides CPLD is following:
Top CPLD logic is set address and the data width that bootloader will visit; 8 bit data width and 8 bit address width are got in suggestion, will be stored in internal memory relevant information in CPLD parameters such as () internal memory correlation timings according to the address arrangement order of setting and read out.
We know; The file destination of CPLD can pass through its JTAG (joint test behavior tissue) interface to be downloaded through the PC client cables, and supports real-time online to download, like this; We just can be than the configuration that is easier to change memory parameters no matter when debugging is still produced.And BootLoader still can use the related function of SPD to calculate the register value of DDR3 controller automatically; And omitted the more loaded down with trivial details human configuration register process of carrying out, only need the driving of original I2C interface just passable with the driving replacement of local parallel bus.
Adopt the method to carry out internal memory identification and initialization in the Embedded System Design, biggest advantage is convenient and flexible, saves the development time, reduces development difficulty.Need only used processor support, can change internal memory model and the capacity and the quantity of your system easily, accomplish that the compatibility of veneer and extendability are better, also help the buying of production material.This flexible and convenient with regard to more embodying during debugging, the BootLoader program need not to do any change, also can carry out the debugging of internal memory sequential, has avoided use programmable device programming BootLoader program repeatedly.Why adopting local parallel bus, be because its interface logic at CPLD takies few resources and just can use, and access rate is higher, also makes things convenient for CPLD to realize other functions.Need the CPLD chip on the embedded board often, so also can not increase cost, the following CPLD of in fact present 1 U.S. dollar is also a lot.
Fig. 1 is the principle schematic of processor through local parallel bus visit CPLD (programmable logic device (PLD)), and data line can be set at 8 bit wides, and address wire also is set at 8 bit wides, and control line generally comprises the sheet choosing, reads to enable and write enable line.CPLD is different because of manufacturer; The cable that connects PC and CPLD is slightly different; It is also different to develop software; But realize that finally the result is the same; Through carrying out logical design at CPLD; Realize the control of read-write sequence, the realization of different processor logic designs is different, but all fairly simple.
Fig. 2 has described the flow process of DDRIII initialization and developing and debugging; A most important step of developing and debugging is exactly a configuration parameter of revising internal memory; It is the configuration of each the address memory contents in the foregoing PPD standard; This step is very similar with the configuration of the content of the SPD standard of DDR3 memory bar; Different is; The SPD normalized definition the relevant data of a lot of memory bar modules; And we use is the internal memory nude film; So as previously mentioned, a lot of relevant bytes can be defined as subsequent use in the PPD standard.The information of back 128～256 bytes store all is and the irrelevant data of memory chip; Can be defined as subsequent use; 0～127 byte except byte 3 with byte 32 be fully with the SPD compatibility, can design relevant parameter with reference to the circuit design of byte and the databook of memory chip according to the SPD standard.Byte 3 is the type of memory modules in SPD standard the inside, and to change expression into be non-buffer-type to this byte content or deposit the type main memory circuit in the PPD standard; Byte 32 is revised as the manufacturer of expression memory chip; Here the processor with the PowerPC framework is an example with the common 2G byte capacity of the DDR3 memory chip MT41J128M16HA-15E that adopts 8 Micron Technologys; Bus data transfer rate 667MT/s; 64 of highway widths; Processor controller is launched 2 physics sheet choosings; Non-buffer-type pattern, MT41J128M16HA-15E is 8 Banks, monolithic capacity 2Gbit.Row address and column address are respectively 14X10.Concrete byte information is with reference to following PPD authority data storage format definition and the tabulation of above-mentioned instance value.
Disposed PPD; Just logic can be compiled into file destination; Such as the EPM240T100C5 (device model) of the MAX II series CPLD that uses altera corp, the file destination of compiling can be downloaded cable and download among the EPM240T100C5 through the special-purpose JTAG that the said firm provides.Just the beginning test process can or be re-powered with processor and CPLD place circuit reset.The BootLoader program reads memory parameters through local parallel bus; Its internal processes can be according to the information of reading; Such as the quantity of bus data transfer rate, used choosing, time sequence parameter or the like; Automatically calculate the register value that processor needs, with the automatic initialization of register of the controller of One's name is legion and start, the user can test memory read-write through debug ports such as serial ports; As test unsuccessful; Return, the PPD configuration parameter is revised in inspection, repeats this process again.The emphasis of whole process is exactly guarantee local parallel bus logical design and configuration PPD parameter correct, and other parts all are the things of the maturation of empirical tests, so, simplified performance history greatly, convenient production.
Definition of PPD authority data storage format and above-mentioned instance value are tabulated as follows:
The content of not doing in this instructions to describe in detail belongs to this area professional and technical personnel's known prior art.
Claims (6)
1. a novel DDRIII internal memory is discerned and initial method; Save as the internal memory nude film in the said DDRIII; It is characterized in that: adopt programmable logic device (CPLD) stored memory chip relevant information, and data memory format has 4 differences on series arrangement detection SPD normative foundation:
A, 1 place, address are the version numbers of PPD;
B, 3 places, address, definition be the pattern of memory chip group access, non-buffer-type is still deposited type;
C, 32 places, address, definition be the corresponding coding of memory chip manufacturer;
D, address 33 to 125 and address 128 to 255 all are the subsequent use of definition;
The data memory format that this kind is new is called parallel configuration and surveys the PPD standard,
The local parallel bus that the bus of processor access programmable logic device (CPLD) adopts processor all to possess usually,
The system start-up program bootloader program of processor reads the internal memory relevant information that is stored in the CPLD through local parallel bus, uses the information that reads that Memory Controller Hub is carried out initialization then,
The storage of internal memory relevant information and bus access logic interfacing thereof realize through in CPLD, doing logic.
2. novel DDRIII internal memory identification as claimed in claim 1 and initial method, it is characterized in that: the internal memory relevant information in the said CPLD of being stored in comprises at least: the density of memory chip and physics sheet select the line number of number, chip address and columns, time sequence parameter, the pattern of memory chip group access, memory chip manufacturer correspondence to encode.
3. novel DDRIII internal memory identification as claimed in claim 1 and initial method; It is characterized in that: the CPLD logic is set address and the data width that bootloader will visit, and the internal memory relevant information that will be stored in the CPLD according to the address arrangement order of setting reads out.
4. novel DDRIII internal memory identification as claimed in claim 3 and initial method is characterized in that: address and data width that CPLD logic setting bootloader will visit are got 8 bit data width and 8 bit address width.
5. novel DDRIII internal memory identification as claimed in claim 1 and initial method; It is characterized in that: utilize the file destination of CPLD to organize jtag interface to pass through PC client cables real-time online download function, change the configuration of the memory parameters of the needs adjustment in the internal memory relevant information that is stored in the CPLD through its joint test behavior.
6. novel DDRIII internal memory identification as claimed in claim 1 and initial method is characterized in that concrete steps are:
Step 1 has disposed PPD, and logic is compiled into file destination, and the file destination of compiling is downloaded cable through JTAG and downloaded among the CPLD,
Step 2, with processor and CPLD place circuit reset or re-power, the beginning test process,
Step 3, the BootLoader program reads memory parameters through local parallel bus, and its internal processes calculates the register value that processor needs automatically according to the information of reading, with the automatic initialization of register of the controller of One's name is legion and start,
Step 4, the user tests memory read-write through debug port, as tests unsuccessfully, returns, and the PPD configuration parameter is revised in inspection, and repeating step 1 is to step 4, until testing successfully again.
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| CN102984007A (en) * | 2012-12-06 | 2013-03-20 | 中兴通讯股份有限公司 | Initialization processing for stored data and initializing method and device |
| CN107122279A (en) * | 2017-06-08 | 2017-09-01 | 济南浪潮高新科技投资发展有限公司 | A kind of method by U Boot fast debugging DDR memory grains |
| CN107657980A (en) * | 2017-10-24 | 2018-02-02 | 济南浪潮高新科技投资发展有限公司 | A kind of method of the onboard DDR particles of auto-initiation |
| CN108845899A (en) * | 2018-05-29 | 2018-11-20 | 郑州云海信息技术有限公司 | A kind of method and system of M.3 SSD power-up initializing |
| CN110309374A (en) * | 2019-05-22 | 2019-10-08 | 深圳市金泰克半导体有限公司 | A kind of analytic method, system, terminal device and computer readable storage medium |
| CN110941454A (en) * | 2019-11-08 | 2020-03-31 | 山东超越数控电子股份有限公司 | Method and system for realizing memory self-adaption |
| CN112099733A (en) * | 2020-08-26 | 2020-12-18 | 瑞芯微电子股份有限公司 | DRAM memory time sequence configuration method and device |
| CN112732186A (en) * | 2020-12-31 | 2021-04-30 | 深圳创维－Rgb电子有限公司 | DDR self-adaptation method, device and computer readable storage medium |
| CN116594922A (en) * | 2023-07-14 | 2023-08-15 | 深圳砺驰半导体科技有限公司 | Data access circuit, method and system-level chip |
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| CN102984007A (en) * | 2012-12-06 | 2013-03-20 | 中兴通讯股份有限公司 | Initialization processing for stored data and initializing method and device |
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| CN110309374A (en) * | 2019-05-22 | 2019-10-08 | 深圳市金泰克半导体有限公司 | A kind of analytic method, system, terminal device and computer readable storage medium |
| CN110941454A (en) * | 2019-11-08 | 2020-03-31 | 山东超越数控电子股份有限公司 | Method and system for realizing memory self-adaption |
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| CN112732186A (en) * | 2020-12-31 | 2021-04-30 | 深圳创维－Rgb电子有限公司 | DDR self-adaptation method, device and computer readable storage medium |
| CN116594922A (en) * | 2023-07-14 | 2023-08-15 | 深圳砺驰半导体科技有限公司 | Data access circuit, method and system-level chip |
| CN116594922B (en) * | 2023-07-14 | 2023-10-31 | 深圳砺驰半导体科技有限公司 | Data access circuit, method and system-level chip |
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