CN101950368B - Recognition method of storage capacity of 24C series chip - Google Patents
Recognition method of storage capacity of 24C series chip Download PDFInfo
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- CN101950368B CN101950368B CN 201010287900 CN201010287900A CN101950368B CN 101950368 B CN101950368 B CN 101950368B CN 201010287900 CN201010287900 CN 201010287900 CN 201010287900 A CN201010287900 A CN 201010287900A CN 101950368 B CN101950368 B CN 101950368B
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Abstract
The invention provides a recognition method of storage capacity of a 24C series chip, comprising the following steps of: first, selecting any one byte with a storage address which is smaller than 7FH in the 24C series chip and recording the storage address of the byte as a first address; second, writing first data into a corresponding byte of the first address, adding an effective binary number before the top bit of the first address, recording the effective binary number as a second address, reading second data stored by the corresponding byte of the second address; judging whether the second data is equal to the first data; if so, determining the storage capacity of the chip according to the effective bit of the first address; otherwise, executing a third step; and third, selecting any one byte that the effective bit of the storage address in the chip is equal to the effective bit of the second address, recording the storage address of the byte as a new first address and returning and executing the second step. According to the provided method, the size and the storage capacity of the 24C series chip can be conveniently and quickly recognized and recognition work efficiency and recognition accuracy are improved.
Description
Technical field
The present invention relates to a kind of recognition methods of chip, especially relate to the recognition methods of 24C family chip memory capacity.
Background technology
The 24C family chip is widely used in the field of low capacity storage, as using in ink box chip or the carbon powder box chip.The 24C family chip includes 24C01,24C02,24C04,24C08 ... Models such as 24C1024, wherein " 24C " representes the serial model No. of chip, and the numeral of back is some powers of 2, and the chip storage capacity of different model is different.For example, the chip storage capacity address wire of 24C01 model is 7, and the represented scope of its memory address is from 00H to 7FH, just 0000000 of binary number to 1111111, and memory capacity is 128 bytes.The chip storage capacity address wire of 24C02 model is 8, the represented scope of its memory address from 00H to FFH, just 00000000 of binary number to 11111111, memory capacity is 256 bytes.The chip storage capacity address wire of 24C04 model is 9, the represented scope of its memory address from 00H to 1FFH, promptly 000000000 of binary number to 111111111, memory capacity is 512 bytes.By that analogy, the chip-stored address wire of 24C512 model is 16, and its memory capacity is the 512K byte, and the chip-stored address wire of 24C1024 model is 17, and its memory capacity is the 1024K byte.
It is thus clear that in the 24C family chip, along with increasing progressively of type figure, the address wire of memory capacity also increases progressively, its memory capacity also increases progressively thereupon.And in the chip of adjacent two models, the chip of back one model increases by one than the chip storage capacity address wire of last model, and memory capacity also is the twice of last model chip storage capacity.
Because the ID sign indicating number that is used for the identification chip model is not stored in 24C family chip inside; The method of therefore existing identification 24C family chip model and memory capacity has following two kinds: a kind of is through naked eyes Direct observation chip seal silk; Be the quantity of chip storage capacity address wire; This method work efficiency is low, and accuracy is not high; Another kind method is through instrument the data of being stored in the chip to be read; By the memory capacity of technician according to the data analysis chip of being read; This method needs instrument constantly to read the data of chip, thereby and requires the technician data of each chip to be analyzed model and the memory capacity of judging chip.Above-mentioned two kinds of methods all need be carried out manually-operated and analysis to each chip, and work efficiency is not high.
Simultaneously; Each byte of 24C family chip all has own corresponding memory address; And when the 24C family chip receives the address greater than its memory capacity; It can't send information because of the address exceeds the storage inside address, but will exceed removing of memory address part, directly visits the corresponding byte of effective address.
For example, it is 80H that main frame sends the access stored address to 24C01 model chip, i.e. the order of the byte of binary number 10000000; Because the maximum storage address of 24C01 model chip is 7FH; Its address wire is merely 7, so 24C01 model chip will exceed 7 address date and remove, and " 1 " that is about to most significant digit is removed; To hang down seven effective reference address of conduct, this moment, 24C01 model chip was the byte of 00H with the access stored address.
In addition, model is that the chip of 24C04 and 24C08 has response to A3 order in the 24C family chip, and to have only model be that the chip of 24C08 has response to A4 and A8 order, but uses the model of mentioned order identification chip.
Summary of the invention
Fundamental purpose of the present invention provides the 24C family chip memory capacity recognition methods accurately of a kind of convenience.
Another object of the present invention provides the high 24C family chip memory capacity recognition methods of a kind of recognition efficiency.
For realizing above-mentioned fundamental purpose, 24C family chip memory capacity provided by the invention recognition methods comprises step 1: choose the arbitrary byte of 24C family chip stored address less than 7FH, this bytes of memory address is designated as first address; Step 2: the byte corresponding to first address writes first data; Before the most significant digit of first address, increase an effective binary number and be designated as second address; Read second data that the corresponding byte of second address is stored, judge whether second data equate with first data, if equate; Then confirm the memory capacity of chip according to the number of significant digit of first address, otherwise execution in step three; Step 3: choose arbitrary byte that chip stored address number of significant digit equates with the second address number of significant digit, this bytes of memory address is designated as the first new address, return execution in step two.
Visible by such scheme; After the data in the read-write 24C family chip; Can whether equate to confirm how many roots the address data line of 24C family chip has through judging first data and second data, thereby judge the concrete model of 24C family chip, and then calculate the memory capacity of this chip.And, in 24C family chip identifying, do not need artificial the participation, improve identification efficiency greatly.
A preferred scheme is, in the step 2, write first data before, the data of the corresponding byte in first address are saved in the register.Like this, can guarantee that the raw data of the corresponding byte in first address is able to preserve, so that follow-up use.
Further scheme is, in the step 1, choose first address before, the storer of chip is carried out clear operation; And in the step 2, first data that write are non-zero.Like this, first data that can guarantee to write are inequality with the raw data that the corresponding byte in first address is stored, and guarantee the accuracy that detects.
Realize that method of the present invention can also be to comprise step 1: choose the arbitrary byte of 24C family chip stored address, this bytes of memory address is designated as first address less than 7FH; Step 2: the byte corresponding to first address writes first data; Before the most significant digit of first address, increase an effective binary number and be designated as second address, read second data that the corresponding byte of second address is stored, judge whether second data equate with first data; If equate; Judge that chip is the 24C01 cake core, and the memory capacity of definite chip, otherwise execution in step three; Step 3: send the A3 order to chip, judge whether chip has return message, if there is not execution in step four; If have, further send the A4 order, and judge once more whether chip has return message to chip, if having, judge that chip is the 24C08 cake core, if do not have, judge that chip is the 24C04 cake core; Step 4: choosing chip stored address is the arbitrary byte between the 400H to 4FFH, and this bytes of memory address is designated as three-address; Step 5: the byte corresponding to three-address writes the 3rd data; Before the most significant digit of three-address, increase an effective binary number and be designated as the four-address; Read the 4th data that four address corresponding byte is stored, judge whether the 4th data equate with the 3rd data, if equate; Then confirm the memory capacity of chip according to the number of significant digit of three-address, otherwise execution in step six; Step 6: choose arbitrary byte that chip stored address number of significant digit equates with four-address number of significant digit, the bytes of memory address is designated as new three-address, return execution in step five.
This shows that use A3, A4 to order and discern 24C04 or 24C08 cake core, the complicacy that can simplify procedures helps program development.
Further scheme is, in the step 3, after chip transmission A4 orders and receives return signal, sends the A8 order to chip, judges whether to receive return message, if receive return message, the affirmation chip is the 24C08 cake core, otherwise the judgement chip is made mistakes.
This shows,, can confirm further that the model of chip is 24C08, can further improve the accuracy of identification through sending the A8 order.Whether simultaneously, can also detect chip makes mistakes.
The present invention can also use another method and realize, the method comprising the steps of one: choose the arbitrary byte of 24C family chip stored address less than 7F, this bytes of memory address is designated as first address; Step 2: the byte corresponding to first address writes first data; Before the most significant digit of first address, increase an effective binary number and be designated as second address; Corresponding byte to second address writes second data different with first data; Read the data that the corresponding byte in first address stores and be saved in the register, judge whether first data equate with data that register is stored, as if unequal; Then confirm the memory capacity of chip according to the number of significant digit of first address, otherwise execution in step three; Step 3: choose arbitrary byte that chip stored address number of significant digit equates with the second address number of significant digit, the bytes of memory address is designated as the first new address, return execution in step two.
Visible by such scheme; Write first data inequality and second data respectively through byte to first address and second address; Data and first data that read first address once more are relatively the time; Can judge whether chip exists the byte of second address through two data are whether identical, thereby can judge the model of chip, and then calculate the memory capacity of chip.
Method of the present invention also can be to comprise step 1: choose the arbitrary byte of 24C family chip stored address less than 7F, this bytes of memory address is designated as first address; Step 2: the byte corresponding to first address writes first data; Before the most significant digit of first address, increase an effective binary number and be designated as second address; Corresponding byte to second address writes second data different with first data, reads the data that the corresponding byte in first address stores and is saved in the register, judges whether first data equate with data that said register is stored; If it is unequal; Judge that chip is the 24C01 cake core, and the memory capacity of definite chip, otherwise execution in step three; Step 3: send the A3 order to chip, judge whether chip has return message, if there is not execution in step four; If have, further send the A4 order, and judge once more whether chip has return message to chip, if having, judge that chip is the 24C08 cake core, if do not have, judge that chip is the 24C04 cake core; Step 4: choosing chip stored address is the arbitrary byte between the 400H to 4FFH, and this bytes of memory address is designated as three-address; Step 5: the byte corresponding to three-address writes the 3rd data; Before the most significant digit of three-address, increase an effective binary number and be designated as the four-address; Write four data different to four address corresponding byte, read the data that the corresponding byte of three-address stores and be saved in the register, judge whether the 3rd data equate with data that said register is stored with the 3rd data; If it is unequal; Then confirm the memory capacity of chip according to the number of significant digit of three-address, otherwise, execution in step six; Step 6: choose arbitrary byte that chip stored address number of significant digit equates with four-address number of significant digit, this bytes of memory address is designated as new three-address, return execution in step five.
Visible by such scheme, judge that through using A3 order and A4 to order chip whether as 24C04 or 24C08 cake core, can reduce the complicacy of determining program, and the accuracy of judgement is provided.
Description of drawings
Fig. 1 is the process flow diagram of first embodiment of the invention.
Fig. 2 a is the process flow diagram first of second embodiment of the invention.
Fig. 2 b is the process flow diagram second portion of second embodiment of the invention.
Below in conjunction with accompanying drawing and embodiment the present invention is described further.
Embodiment
First embodiment.
Present embodiment is to write a recognizer to pick-up unit, through pick-up unit chip is carried out read-write operation and realizes the identification to chip.
The pick-up unit of present embodiment is as shown in Figure 1 to the identification process of chip.At first, pick-up unit execution in step S1 sends read command to chip under test.Because the 24C family chip of arbitrary model all can be discerned the A1 order, so this read command is the A1 order.Then, pick-up unit execution in step S2 judges whether to receive the return message of chip, and whether order responds to A1 promptly to judge chip, if response is arranged, expression has chip to exist, execution in step S3, otherwise identification process finishes.
Among the step S3, pick-up unit is chosen one first address, and first address of initially choosing should be the address that the 24C family chip of arbitrary model all can be discerned, and therefore should between 00H and 7FH, choose.For example, choose 00H in the present embodiment as first address.After choosing first address, the byte corresponding to first address writes first data, i.e. execution in step S4.Certainly, in order to preserve the original data of the corresponding byte in first address, write first data before, should the raw data of 00H byte be saved in the register, flow process to be identified writes back the 00H byte with raw data after finishing.
Then, pick-up unit execution in step S5 calculates second address on the basis of first address.Second address is on the basis of first address, to increase a most significant digit, promptly before the most significant digit of first address, increases " 1 ", and the number of significant digit that makes second address is than many one of the number of significant digit of first address.Number of significant digit of the present invention is the address wire radical of the actual use in this address, and for example the number of significant digit of 00H to 7FH is 7, and the number of significant digit of 80H to FFH is 8, and the number of significant digit of 100H to 1FFH is 9 etc., by that analogy.According to mentioned above principle, second address that step S5 calculated is 80H.
Then, pick-up unit execution in step S6 reads the corresponding byte in second address, i.e. 80H byte second data of being stored, and execution in step S7 judge whether second data that read are identical with first data.If first data are identical with second data, second address that expression is visited is first address in fact, i.e. 00H byte in the present embodiment; This moment is execution in step S8 then; According to the number of significant digit of first address, i.e. the model of 7 definite chips, and confirm the memory capacity of chip with this.
According to above-mentioned analysis, can judge address wire be 7 be the 24C01 cake core, its memory capacity is 128 bytes.
If first data and second data are unequal, there is the byte of 80H in the expression chip, and can get rid of this chip is the 24C01 cake core, so execution in step S9, confirms first address again and returns execution in step S4.Again first address of confirming should be the address that number of significant digit equates with the former second address number of significant digit, calculates for ease, can former second address be used as the first new address, and the first promptly new address is 80H, has 8 number of significant digit.Subsequently, execution in step S4 once more is till the model of confirming chip.
Certainly, in order to ensure the accuracy of identification, before choosing first address, should carry out clear operation to the storer of chip, the data that promptly all bytes of chip write are " 0 ".Then, first data that the byte of first address is write are non-zero, can effectively distinguish second data that read the corresponding byte in second address like this and whether be different from first data.
Visible by such scheme; Pick-up unit is through above-mentioned flow process; Can discern the model and the memory capacity thereof of 24C family chip quickly and easily; Need not the workman and analyze, not only can improve the work efficiency of identification, can also improve the accuracy of detection through the data that visual inspection seal silk quantity perhaps reads chip.
Second embodiment.
Present embodiment also is through the pick-up unit with trace routine chip to be carried out read-write operation to realize the identification to chip, and the identification process of pick-up unit is shown in Fig. 2 a and Fig. 2 b.
At first, pick-up unit execution in step S11 sends read command, i.e. A1 order, and execution in step S12 judge whether to receive return message, if receive return message, expression has chip to exist, execution in step S13, otherwise finish identification process.
Among the step S13, pick-up unit is chosen first address, like 00H, and writes first data to the 00H byte.
Then, pick-up unit execution in step S14 calculates second address; Second address calculation method is identical with the second address computation method of first embodiment; Therefore calculate 80H as second address, and write second data that are different from first data, execution in step S15 then to the 80H byte; Read the data of 00H byte, and the data that read are saved in the register.
Subsequently, execution in step S16 judges whether the data that first data and register are stored equate, if unequal, it is the byte of 80H that there is not memory address in the expression chip.Because if there is memory address in chip is the byte of 80H, after the 80H byte write second data, the data that the 00H byte is stored still were first data.Having only chip not have memory address is that chip writes the 00H byte with second data under the byte situation of 80H, and what then register was stored is second data, inequality with first data.At this moment, but execution in step S17, the model of confirming chip is 24C01, its memory capacity is 128 bytes.
If first data equate that with data that register is stored the expression chip is not the 24C01 cake core, then execution in step S18 sends the A3 order to chip, and execution in step S19, judges whether to receive return signal, judges promptly whether chip responds.Can know that by aforementioned analysis order has response to A3 to have only 24C04 cake core and 24C08 cake core, if pick-up unit receives return signal; Represent that this chip is 24C04 cake core or 24C08 cake core, then execution in step S20 sends the A4 order to chip; And execution in step S21, judge whether to receive return message, if receive return message; Represent that this chip can discern A4 order, execution in step S23, the person does not represent that chip can not discern the A4 order; Then execution in step S22 judges that this chip is the 24C04 cake core, confirms that its memory capacity is 512 bytes.
Among the step S23, pick-up unit further sends the A8 order, and execution in step S24, judges whether to receive return signal, if receive return signal, can confirm that this chip is the 24C08 cake core, and its memory capacity is 1024 bytes.If do not receive return signal, the judgement chip is made mistakes, the information that can give a warning, and finish identification process.
In step S19, if pick-up unit does not receive return signal, represent that this chip is not 24C04 and 24C08 cake core, further execution in step S26 chooses three-address.This moment, the three-address chosen should be that the 24C16 cake core can be discerned, and the address that can not discern of 24C08 cake core, promptly between 400H to 4FFH, chose.For example, choose 400H as three-address.
Then, execution in step S27, to the corresponding byte of three-address, promptly the 400H byte writes the 3rd data, and execution in step S28, calculates the four-address.Four address calculating principle is identical with the calculating principle and the method for the method and second address, and therefore the four-address is 800H.Simultaneously, the byte corresponding to the four-address writes the 4th data, and the 4th data and the 3rd data are inequality.
Then, execution in step S29 reads the corresponding byte of three-address, i.e. the byte of 400H data of storing, and the data that read are saved in the register.Subsequently, execution in step S30 judges that whether the 3rd data equate with the data that register is stored; If it is unequal; There is not the byte of 400H address in the expression chip, and then execution in step S31 judges the model of chip and the memory capacity of identification chip according to the number of significant digit of three-address.When execution in step S31 first, the model that can confirm chip is not the above model of 24C01,24C04,24C08 or 24C16, therefore can confirm that the model of chip is 24C02, and its memory capacity is 256 bytes.
If the 3rd data are identical with the data that register is stored, the expression chip is not the 24C02 cake core, and execution in step S32 calculates new three-address.The method of new first address of calculating is identical among new three-address computing method and first embodiment, and the new three-address of calculating should have identical number of significant digit with the four-address.Preferably, use the four-address, promptly 800H is as new three-address.Simultaneously, return execution in step S27, till the model and memory capacity of identification chip.
Certainly, before choosing first address, can carry out clear operation, and first data that write, second data, the 3rd data and the 4th data are non-zero to chip.
This shows, use said method can let pick-up unit discern the model of 24C family chip automatically, thus the memory capacity of identification chip, and identifying need not manually-operated, when improving the identification work efficiency, also improves the accuracy rate of identification.
During practical application, first embodiment uses A3, A4 and A8 to order and discern 24C04 or 2408 cake cores, just increases the step to A3, A4 and A8 command recognition.And among second embodiment, also can be not use A3, A4 and A8 to order to discern 24C04 or 2408 cake cores, but constantly circulation be chosen first address, is calculated model and memory capacity that chip is confirmed in second address.In addition, during identification 24C08 cake core, also can not use the A8 order, when chip can be discerned the A4 order, the model that can judge this chip was 24C08.
Certainly, the foregoing description only is the preferable embodiment of the present invention, during practical application more variation can also be arranged, and for example, among first embodiment, first address of newly choosing is not to use former second address, but in optional scope, chooses other addresses; Perhaps, in first embodiment, use A3 order or A4 command recognition 24C04 and 24C08 cake core; Or, before choosing first address, do not send the read message order to chip, directly chip is carried out read-write operation etc., these changes can realize the object of the invention equally.
Require emphasis at last the time, the variations of choosing such as new three-address among the change of choosing first address, second embodiment such as change are also contained in the protection domain of claim of the present invention.
Claims (10)
1.24C the recognition methods of family chip memory capacity comprises
Step 1: choose the arbitrary byte of 24C family chip stored address, said bytes of memory address is designated as first address less than 7FH;
Step 2: the byte corresponding to said first address writes first data; Before the most significant digit of said first address, increase an effective binary number and be designated as second address; Read second data that the corresponding byte of said second address is stored, judge whether said second data equate with said first data, if equate; Then confirm the memory capacity of said chip according to the number of significant digit of said first address, otherwise execution in step three;
Step 3: choose said chip stored address number of significant digit and arbitrary byte that the said second address number of significant digit equates, said bytes of memory address is designated as the first new address, return execution in step two.
2. 24C family chip memory capacity according to claim 1 recognition methods is characterized in that:
In the said step 3, the said first new address is second address of using in the said step 2.
3. 24C family chip memory capacity according to claim 1 and 2 recognition methods is characterized in that:
In the said step 2, write said first data before, the data of the corresponding byte in said first address are saved in the register.
4. 24C family chip memory capacity according to claim 1 and 2 recognition methods is characterized in that:
In the said step 1, choose said first address before, the storer of said chip is carried out clear operation;
In the said step 2, first data that write are non-zero.
5.24C the recognition methods of family chip memory capacity comprises
Step 1: choose the arbitrary byte of 24C family chip stored address, said bytes of memory address is designated as first address less than 7FH;
Step 2: the byte corresponding to said first address writes first data; Before the most significant digit of said first address, increase an effective binary number and be designated as second address, read second data that the corresponding byte of said second address is stored, judge whether said second data equate with said first data; If equate; Judge that said chip is the 24C01 cake core, and confirm the memory capacity of said chip, otherwise execution in step three;
Step 3: send the A3 order to said chip, judge whether said chip has return message, if there is not execution in step four; If have, further send the A4 order, and judge once more whether said chip has return message to said chip, if having, judge that said chip is the 24C08 cake core, if do not have, judge that said chip is the 24C04 cake core;
Step 4: choosing said chip stored address is the arbitrary byte between the 400H to 4FFH, and said bytes of memory address is designated as three-address;
Step 5: the byte corresponding to said three-address writes the 3rd data; Before the most significant digit of said three-address, increase an effective binary number and be designated as the four-address; Read the 4th data that said four address corresponding byte is stored, judge whether said the 4th data equate with said the 3rd data, if equate; Then confirm the memory capacity of said chip according to the number of significant digit of said three-address, otherwise execution in step six;
Step 6: choose arbitrary byte that said chip stored address number of significant digit equates with said four-address number of significant digit, said bytes of memory address is designated as new three-address, return execution in step five.
6. 24C family chip memory capacity according to claim 5 recognition methods is characterized in that:
In the said step 3, after said chip sends the A4 order and receives return signal, send the A8 order to said chip; Judge whether to receive return message; If receive return message, confirm that said chip is the 24C08 cake core, otherwise judge that said chip makes mistakes.
7.24C the recognition methods of family chip memory capacity comprises
Step 1: choose the arbitrary byte of 24C family chip stored address, said bytes of memory address is designated as first address less than 7F;
Step 2: the byte corresponding to said first address writes first data; Before the most significant digit of said first address, increase an effective binary number and be designated as second address; Corresponding byte to said second address writes second data different with first data; Read the data that the corresponding byte in first address stores and be saved in the register, judge whether said first data equate with data that said register is stored, as if unequal; Then confirm the memory capacity of said chip according to the number of significant digit of said first address, otherwise execution in step three;
Step 3: choose said chip stored address number of significant digit and arbitrary byte that the said second address number of significant digit equates, said bytes of memory address is designated as the first new address, return execution in step two.
8. 24C family chip memory capacity according to claim 7 recognition methods is characterized in that:
In the said step 1, choose said first address before, send the read message order to said chip, judge whether to receive the information of returning, if any choosing said first address, otherwise judge do not have chip under test to exist.
9.24C the recognition methods of family chip memory capacity comprises
Step 1: choose the arbitrary byte of 24C family chip stored address, said bytes of memory address is designated as first address less than 7F;
Step 2: the byte corresponding to said first address writes first data; Before the most significant digit of said first address, increase an effective binary number and be designated as second address; Corresponding byte to said second address writes second data different with first data, reads the data that the corresponding byte in first address stores and is saved in the register, judges whether said first data equate with data that said register is stored; If it is unequal; Judge that said chip is the 24C01 cake core, and confirm the memory capacity of said chip, otherwise execution in step three;
Step 3: send the A3 order to said chip, judge whether said chip has return message, if there is not execution in step four; If have, further send the A4 order, and judge once more whether said chip has return message to said chip, if having, judge that said chip is the 24C08 cake core, if do not have, judge that said chip is the 24C04 cake core;
Step 4: choosing said chip stored address is the arbitrary byte between the 400H to 4FFH, and said bytes of memory address is designated as three-address;
Step 5: the byte corresponding to said three-address writes the 3rd data; Before the most significant digit of said three-address, increase an effective binary number and be designated as the four-address; Write four data different to said four address corresponding byte, read the data that the corresponding byte of three-address stores and be saved in the said register, judge whether said the 3rd data equate with data that said register is stored with the 3rd data; If it is unequal; Then confirm the memory capacity of said chip according to the number of significant digit of said three-address, otherwise, execution in step six;
Step 6: choose arbitrary byte that said chip stored address number of significant digit equates with said four-address number of significant digit, said bytes of memory address is designated as new three-address, return execution in step five.
10. 24C family chip memory capacity according to claim 9 recognition methods is characterized in that:
In the said step 3, after said chip sends the A4 order and receives return signal, send the A8 order to said chip; Judge whether to receive return message; If receive return message, confirm that said chip is the 24C08 cake core, otherwise judge that said chip makes mistakes.
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| CN109634534B (en) * | 2019-01-02 | 2022-04-01 | 威胜集团有限公司 | Method for quickly judging capacity of memory chip |
| CN111061651B (en) * | 2019-12-06 | 2022-04-22 | 广州瑞普医疗科技有限公司 | Method and device for identifying serial EEPROM (electrically erasable programmable read-Only memory) model and storage medium |
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| JPH03224041A (en) * | 1990-01-30 | 1991-10-03 | New Japan Radio Co Ltd | Capacity recognizing method for externally connected ram |
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2010
- 2010-09-20 CN CN 201010287900 patent/CN101950368B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0421447A2 (en) * | 1989-10-05 | 1991-04-10 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| CN1315732A (en) * | 2000-03-30 | 2001-10-03 | 华为技术有限公司 | Automatic test method and circuit for RAM |
| CN101241752A (en) * | 2007-02-06 | 2008-08-13 | 三星电子株式会社 | Memory card and memory system having the same |
| CN101419843A (en) * | 2008-12-04 | 2009-04-29 | 北京中星微电子有限公司 | Flash memory recognition method, recognition device and chip controller |
Non-Patent Citations (1)
| Title |
|---|
| JP平3-224041A 1991.10.03 |
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