CN116594922A

CN116594922A - Data access circuit, method and system-level chip

Info

Publication number: CN116594922A
Application number: CN202310862094.2A
Authority: CN
Inventors: 李丹
Original assignee: Shenzhen Lichi Semiconductor Technology Co ltd
Current assignee: Shenzhen Lichi Semiconductor Technology Co ltd
Priority date: 2023-07-14
Filing date: 2023-07-14
Publication date: 2023-08-15
Anticipated expiration: 2043-07-14
Also published as: CN116594922B

Abstract

The disclosure provides a data access circuit, a method and a system-level chip, and relates to the technical field of electric automobiles, wherein the circuit comprises: a register configuration sub-circuit and a logic address decoding chip selection sub-circuit; the register configuration sub-circuit is used for receiving and sending logic address grouping information and associated configuration information of a plurality of external devices to the logic address decoding chip selection sub-circuit; the logic address decoding chip selection sub-circuit is used for receiving and analyzing the access type, the control signal and the access address sent by the host, and if the control signal is an effective control signal, the type of the access address is a logic address type and the access type is a writing operation type, confirming at least two first external devices based on the access address, the logic address grouping information and the associated configuration information of a plurality of external devices so as to enable the host to access the at least two first external devices in parallel; the parallel access of the host to the plurality of first external devices is realized, and the time delay of the host for accessing the external devices is shortened.

Description

Data access circuit, method and system-level chip

Technical Field

The disclosure relates to the technical field of electric automobiles, and in particular relates to a data access circuit, a data access method and a system-level chip.

Background

Along with the intelligent process of the automobile, the number of Electronic Control Units (ECUs) in the automobile is also rapidly increased, and the electric and electronic architecture of the automobile is gradually changed from a distributed mode to a centralized mode, namely, all hardware in the automobile is controlled through a central processing unit and an operating system, so that a single system-on-chip (SOC) needs to be connected with more hardware resources to bear more functions; the external equipment is used as a part of the system-on-chip and widely exists at the access terminal of the SOC; when the host in the SOC accesses a plurality of external devices, the information interaction between the host and the peripheral is completed by accessing an address space inside the external devices; along with the development of intellectualization, the number of external devices connected by the SOC is increased sharply, and due to the limitation of mainstream decoding logic or topological structure, serial access can only be performed on the external devices, so that limitation exists on partial delay-sensitive application scenarios.

Disclosure of Invention

The present disclosure provides a data access circuit, method and system-on-a-chip to at least solve the above technical problems in the prior art.

According to a first aspect of the present disclosure, there is provided a data access circuit, the circuit being applied to a system-on-chip, the circuit comprising: the register is provided with a sub-circuit, a logic address decoding chip selecting sub-circuit and a physical address decoding chip selecting sub-circuit;

The register configuration sub-circuit is connected with a logic address decoding chip selection sub-circuit in the system level chip and is used for receiving and sending logic address grouping information and associated configuration information of a plurality of external devices to the logic address decoding chip selection sub-circuit;

the logic address decoding chip selection sub-circuit is connected with a host in the system-in-chip and is used for receiving an access type, a control signal and an access address sent by the host, the logic address decoding chip selection sub-circuit analyzes the access type, the control signal and the access address, and if the control signal is an effective control signal, the type of the access address is a logic address type and the access type meets a write operation type, at least two first external devices in the plurality of external devices are confirmed based on the access address, the logic address grouping information and the associated configuration information of the plurality of external devices so that the host can access the at least two first external devices in parallel;

the logic address grouping information comprises a start address segment and an end address segment corresponding to each logic address grouping, and the association configuration information of the external equipment comprises an enabling relation between the external equipment and at least one logic address grouping.

According to a second aspect of the present disclosure, there is provided a data access method applied to a system-on-chip, including:

the register configuration sub-circuit receives and transmits logic address grouping information and associated configuration information of a plurality of external devices to the logic address decoding chip selection sub-circuit;

the logic address decoding chip selector circuit receives an access type, a control signal and an access address sent by a host, and the logic address decoding chip selector circuit analyzes the access type, the control signal and the access address, and if the control signal is an effective control signal, the access address type is a logic address type and the access type meets a write operation type, at least two first external devices in the plurality of external devices are confirmed based on the access address, the logic address grouping information and the associated configuration information of the plurality of external devices, so that the host accesses the at least two first external devices in parallel;

According to a third aspect of the present disclosure, there is provided a system-on-chip comprising: the register configuration sub-circuit, the logic address decoding chip selection sub-circuit, the host and at least one external device;

The data access circuit comprises a register configuration sub-circuit, a logic address decoding chip selection sub-circuit and a logic address processing sub-circuit, wherein the register configuration sub-circuit is connected with the logic address decoding chip selection sub-circuit in a system-in-chip and is used for receiving and sending logic address grouping information and associated configuration information of a plurality of external devices to the logic address decoding chip selection sub-circuit; the logic address decoding chip selection sub-circuit is connected with a host in the system-in-chip and is used for receiving an access type, a control signal and an access address sent by the host, the logic address decoding chip selection sub-circuit analyzes the access type, the control signal and the access address, and if the control signal is an effective control signal, the type of the access address is a logic address type and the access type meets a write operation type, at least two first external devices in the plurality of external devices are confirmed based on the access address, the logic address grouping information and the associated configuration information of the plurality of external devices so that the host can access the at least two first external devices in parallel; the logic address grouping information comprises a start address segment and an end address segment corresponding to each logic address grouping, and the associated configuration information of the external devices comprises an enabling relation between the external devices and at least one logic address grouping, so that the plurality of first external devices can be determined through the logic address in the access information, the logic address grouping information and the associated configuration information of the plurality of external devices, parallel access of the host to the plurality of first external devices is achieved, and time delay of the host accessing the external devices is shortened.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:

in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

FIG. 1 shows an alternative architecture diagram of a system-on-chip in the related art;

FIG. 2 is a schematic diagram of a related art host accessing an external device;

FIG. 3 is a schematic diagram of a first alternative architecture of a data access circuit provided by an embodiment of the present disclosure;

fig. 4 illustrates logical address grouping information and associated configuration information of a plurality of external devices provided by an embodiment of the present disclosure;

FIG. 5 illustrates a schematic diagram of a parallel access external device provided by an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a second alternative architecture of a data access circuit provided by an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a first alternative flow of a data access method provided by an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a second alternative flow of a data access apparatus provided by an embodiment of the present disclosure;

fig. 9 shows a schematic diagram of a composition structure of an electronic device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the present disclosure is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

It should be understood that, in various embodiments of the present disclosure, the size of the sequence number of each implementation process does not mean that the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

Before explaining the embodiments of the present disclosure in further detail, terms and terminology involved in the embodiments of the present disclosure are explained, and the terms and terminology involved in the embodiments of the present disclosure are applicable to the following explanation.

1) A system-on-chip.

Conventional chips mainly comprise a single unit, such as a conventional Central Processing Unit (CPU) mainly comprising a computing unit; and the system-in-chip can also comprise a memory, a power supply controller, a clock controller, an interrupt controller, a processor core and other components.

2) Hardware domain.

The system-on-chip may be implemented based on a scheme of hard isolation. That is, the plurality of hardware resources inside the system-in-chip are divided into several groups, each group includes resources required by one or more units (such as a computing unit, a clock controller, an interrupt controller, a processor core, etc.), and the resources in each group use the same number, respond to the data access requirement mutually, and do not affect the hardware access requirements of other groups. Each set hardware resource group is a hardware domain, each hardware domain independently runs an operating system, and data interaction is completed between different hardware domains in a mode of inter-core communication.

Different hardware resources can be divided into different groups as required, for example, one or more processor cores, GPUs and other hardware resources suitable for high-performance computing are divided into one group, and an operating system is operated to execute tasks with high-performance requirements; meanwhile, one or more processor cores and other hardware resources are divided into a group, an Rtos operating system is operated, and tasks with high real-time requirements are executed. Different groups, i.e. different hardware domains.

3) Inter-core communication.

There is also a need for information communication between different hardware domains, and this communication mode is called inter-core communication, and has more advantages than chip-to-chip communication, such as no need to transmit signals off-chip, and thus security and speed are improved greatly. Inter-core communication takes many forms, such as a mailbox mechanism adapted to transfer instructions, and a shared memory mechanism adapted to share data.

4) And (3) isomerism.

There may be differences between the multiple hardware domains that are considered heterogeneous if they reach a point where they cannot be uniformly scheduled by the operating system, even though the same processor core is used. Multiple hardware domains may be homogenous or heterogeneous. It should be noted that heterogeneous is an additional limitation on multiple hardware domains, and multi-core heterogeneous is a hardware concept, not a software concept.

5) External equipment

External devices (peripherals for short) are widely present at the access end of the SOC as part of the SOC system. The method mainly completes information interaction between a processor (or a host) and an external device by reading, writing and accessing an address space inside the external device through an advanced high-performance BUS (Advanced High Performance Bus, AHB BUS) or a peripheral BUS (Advanced Peripheral Bus, APB).

Along with the progress of intelligent automobiles, the number of electronic control units (Electronic Control Unit, ECU) required for a bicycle is also rapidly increasing. The traditional automobile electronic control system is gradually eliminated by connecting each ECU unit through a copper wire cable, and the automobile electric and electronic architecture is gradually moving from a distributed type to a centralized type.

The centralized electronic and electric architecture controls all hardware on the vehicle through a central processing unit and an operating system, so that a single SOC needs to be connected with more hardware resources and bears more functions. Although the data bandwidth requirement of a single external device is unchanged or has a growing trend, the number of external devices is increased sharply, and the requirement on the bandwidth of the SOC system is increased.

In an application scene meeting automobile specifications (abbreviated as automobile specifications, the requirement on safety is inferior to that of aerospace and military industry), or an application scene of an automobile, in the engineering practice, in order to realize that a single SOC controls the hardware resources of the whole automobile as much as possible, a plurality of or even dozens of external devices with the same or similar functions are often connected. The external devices with the same functions are distributed with different physical address spaces (absolute addresses), the decoding selection unit in the SOC distinguishes the accesses to the different external devices through decoding the high-order bits of the physical addresses, and the external devices distinguish the accesses to the different internal address spaces through decoding the low-order bits of the physical addresses. Wherein the same or similar (or similar) functions may include the same or similar (or similar) processing of data.

Fig. 1 shows an alternative structural schematic diagram of a system-on-chip in the related art.

As shown in fig. 1, the SOC includes a host, a decoding selection unit, and three external devices (ADC 1, ADC2, and ADC 3), where the host is connected to the decoding selection unit, and the three external devices are connected to the decoding selection unit.

The host computer includes the physical address in the visit information sent to the decoding selection unit, the physical address includes high order and low order; the physical address high-order sign target external device physical address is used for determining the external device (or the external device to be accessed) receiving the access information, and the physical address low-order sign accesses the internal storage space of the external device; the host sends access information carrying a physical address to the decoding selection unit, the decoding selection unit determines an external device for receiving the access information based on the high-order physical address, and after the external device receives the access information, the host confirms the internal storage space accessed based on the low-order physical address to complete data reading or writing of the host to the external device.

In some alternative embodiments, the SOC includes a plurality of external devices with the same or similar functions, the physical addresses of the external devices are different, and related registers need to be configured to complete initialization before working, but due to the limitation of the current mainstream decoding logic or topology structure, the decoding logic of the decoding selection unit is physical address decoding, only one external device can be determined at a time based on the physical address high bits, after the host accesses the external device, the next external device to be accessed can be determined, that is, the host can only perform serial access to the external device, and cannot access a plurality of external devices with the same or similar functions at the same time.

Fig. 2 is a schematic diagram of a related art host accessing an external device.

As shown in fig. 1 and fig. 2, if the host needs to access ADC1, ADC2 and ADC3, access to ADC2 needs to be performed only when access to ADC1 is completed, and similarly access to ADC3 cannot be performed only when access to ADC2 is completed, that is, the host cannot access multiple external devices in parallel at the same time, write data into the multiple external devices, and limit the delay-sensitive application scenario.

Aiming at the defect that a host cannot write data into a plurality of external devices in parallel (or simultaneously) in the related art, the disclosure provides a data access circuit, a data access method and a system-in-chip so as to solve part or all of the technical problems.

Fig. 3 is a schematic diagram showing a first alternative structure of a data access circuit provided in an embodiment of the present disclosure, which will be described in terms of the respective parts.

In some embodiments, as shown in FIG. 3, the data access circuit 100 includes a register configuration sub-circuit 101 and a logic address decode chip select sub-circuit 102.

The register configuration sub-circuit 101 is connected to the logic address decoding chip selection sub-circuit 102, and is configured to send logic address grouping information and associated configuration information of a plurality of external devices to the logic address decoding chip selection sub-circuit 102.

In some embodiments, the register configuration sub-circuit 100 may further be connected to a host device, and receive, based on the APB bus or the AHB bus, logical address packet information and associated configuration information of a plurality of external devices sent by the host device. The host device may be a host as shown in fig. 4, or may be a host device other than the host of fig. 4, and the disclosure is not particularly limited.

Fig. 4 illustrates logical address grouping information and associated configuration information of a plurality of external devices provided by an embodiment of the present disclosure.

In some embodiments, as shown in fig. 4, the logical address packet information includes a start address segment and an end address segment of each logical address packet, e.g., the start address segment of logical address packet 0 is 1 and the end address segment is 100; the start address segment of the logical address packet 1 is 101, the end address segment is 200, etc., and it should be noted that the start address segment and the end address segment are only illustrative, and may be set according to the requirements in practical applications, and are not limited to the ranges in the embodiments of the present disclosure.

In some embodiments, the association configuration information of the plurality of external devices includes an enabling relationship between any one of the plurality of external devices and at least one logical address packet, where the enabling relationship may be understood that a storage space of the external device includes a certain logical address packet (with an enabling relationship or association enabling), or a storage space of the external device does not include a certain logical address packet (without an enabling relationship or unassociated enabling).

In implementation, if the storage space of the external device comprises a first logical address group, enabling association between the external device and the first logical address group; or if the storage space of the external device does not comprise the first logical address packet, enabling the external device and the first logical address packet in an unassociated manner.

As shown in fig. 4, for the enabling relationship between the external device n and at least one logical address packet (peripheral n association configuration in fig. 4), it may be determined that the external device n is enabled at least in association with a logical address packet 0 (packet 0 in fig. 4), a logical address packet 1 (packet 1 in fig. 4), and a logical address packet m (packet m in fig. 4), that is, the storage space of the external device n includes at least a logical address packet 0, a logical address packet 1, and a logical address packet m, further, taking the start address segment of the logical address packet 0 as 1, the end address segment as 100, the start address segment of the logical address packet 1 as 101, the end address segment as 200 as an example, the storage space of the external device n includes at least an address segment of 1, the end address segment as 200, and the start address segment as m×100+1, and the end address segment as an address space of (m+1) ×100. The logical address groups corresponding to the at least two first external devices confirmed by the logical address decoding chip selection sub-circuit are the same, wherein m and n are positive integers.

The logic address decoding chip selecting sub-circuit 102 is respectively connected with the register configuration sub-circuit 101, the host and the plurality of external devices, and the data access circuit 100, the host, the plurality of external devices and the above-mentioned host device (if any) are all disposed in the same system-in-chip.

The logic address decoding chip selection sub-circuit 102 is configured to receive an access type, a control signal and an access address sent by the host, where the logic address decoding chip selection sub-circuit parses the access type, the control signal and the access address, and if the control signal is an effective control signal, the access address type is a logic address type, and the access type satisfies a write operation type, confirms at least two first external devices in the plurality of external devices based on the access address, the logic address grouping information and associated configuration information of the plurality of external devices, so that the host accesses the at least two first external devices in parallel. The control signal is used for implementing writing operation based on the high and low levels included in the control signal when the host accesses the external device. The at least two first external devices are external devices with the same or similar functions, namely, the data processing modes are the same or similar.

In some embodiments, as shown in fig. 3, after the logic address decoding chip selection sub-circuit 102 confirms at least one first external device, a control signal and access data are sent to the external device, so that the external device writes the access data into a corresponding storage space of the external device based on a high level and a low level of the control signal. The external device 1 chip selection/external device n chip selection refers to that the logic address decoding chip selection sub-circuit 102 confirms that the external device corresponding to the access address is external device 1/external device n based on the access address; and the address is controlled to be a control signal, or the access data is written into the corresponding storage space of the external device based on the high and low levels of the control signal.

In some embodiments, the active control signal may include a designated signal under a different communication protocol, for example, a Psel signal in the APB protocol, an Hsel signal or an Htrans signal in the AHB protocol. If the control signal is a valid control signal, the control signal is a Psel signal, an Hsel signal or an Htrans signal.

In some embodiments, the logic address decoding chip select sub-circuit 102 may decode a logic address, and if the type of the access address is a logic address type, the logic address decoding chip select sub-circuit 102 decodes the logic address; if the type of the access address is a physical address type, the logic address decoding chip selection sub-circuit 102 does not send an access error message to the host for the access address; and if the access type is the read operation type, transmitting error access information to the host.

That is, the data access method or the data access circuit according to the embodiments of the present disclosure is applicable to writing operation, and the host may write the same data into a plurality of external devices with the same or similar functions in parallel.

In some embodiments, the logic address decoding chip selecting sub-circuit 102 is specifically configured to confirm, based on the access address and the logic address packet information, a first logic address packet corresponding to the access address; and based on the first logical address packet and the associated configuration information of the at least one external device, confirming at least two first external devices corresponding to the first logical address packet.

In specific implementation, the logic address decoding chip selecting sub-circuit 102 determines which range of the logic address packet the access address belongs to, and still takes the initial address segment of the logic address packet 0 as 1 and the end address segment as 100 as an example, assuming that the access address is 56, the access address falls into the logic address packet 0 (i.e. the first logic address packet); further, at least two external devices which are enabled by association with the logical address packet 0 are confirmed as the at least two first external devices.

Fig. 5 shows a schematic diagram of a parallel access external device provided by an embodiment of the present disclosure.

As shown in fig. 5, when the host wants to access the external devices ADC1, ADC2 and ADC3, based on the access address, the logical address grouping information and the associated configuration information of the plurality of external devices, the external devices ADC1, ADC2 and ADC3 may be determined, so as to implement parallel access from the host to the external devices ADC1, ADC2 and ADC 3.

In some optional embodiments, after the host accesses the at least two first external devices, there may be an access error (such as a peripheral failure), so the logic address decoding chip selecting sub-circuit 102 is further configured to receive logic address error access information sent by any one of the at least two first external devices, and send the logic address error access information and an identifier of a corresponding first external device to the register configuration sub-circuit 101, where the corresponding first external device refers to an external device that sends the logic address error access information; any one of the at least two first external devices includes all external devices (one or at least two) with access errors.

The register configuration sub-circuit 101 is further configured to receive the logical address error access information and the identifier of the corresponding first external device sent by the logical address decoding chip selection sub-circuit 102, and send the logical address error access information and the identifier of the corresponding first external device to the host through the interrupt sub-circuit in the chip, so that the host initiates access to the corresponding first external device again.

In some embodiments, the interrupt sub-circuit is connected to the register configuration sub-circuit 100 and the host, and is configured to receive and send the logical address error access information and the identifier of the corresponding first external device to the host, so that the host initiates access to the corresponding first external device again.

In some alternative embodiments, the interrupt sub-circuit may be internal to the data access circuit 100 or external to the data access circuit 100, the interrupt sub-circuit being a circuit internal to the system-in-chip.

Thus, through the data access circuit provided by the embodiment of the disclosure, when a host wants to access to a plurality of external devices, the logic address decoding chip selection sub-circuit can confirm at least two first external devices based on the access address, the logic address grouping information and the associated configuration information of the plurality of external devices, so that the host can write data into the at least two first external devices in parallel, the parallel access of the host to the plurality of external devices is realized, and the limitation brought by the time-delay sensitive application scenario is solved.

Fig. 6 shows a second alternative architecture diagram of a data access circuit provided by an embodiment of the present disclosure.

In some embodiments, the data access circuit 100 includes a register configuration sub-circuit 101, a logic address decoding chip select sub-circuit 102, a physical address decoding chip select sub-circuit 103, and at least one or logic sub-circuit (as distinguished by 1041 to 104n in fig. 6), wherein each or logic sub-circuit corresponds to one external device, as shown in fig. 6, or logic sub-circuit 1041 (in fig. 6 or logic 1041) corresponds to external device 1, or logic sub-circuit 104n (in fig. 6 or logic 104 n) corresponds to external device n.

As shown in fig. 5, the register configuration sub-circuit 101 is connected to the logic address decoding chip selection sub-circuit 102, and its input end is used for receiving logic address grouping information sent by a host device in a system-in-chip and associated configuration information of a plurality of external devices, and its output end is used for sending the logic address grouping information and associated configuration information of the plurality of external devices to the logic address decoding chip selection sub-circuit 102; when an access error occurs, the input end of the access error is further used for receiving the logic address error access information and the identifier of the corresponding first external device sent by the logic address decoding chip selection sub-circuit 102, and the output end of the access error is further used for sending the logic address error access information and the identifier of the corresponding first external device to the host. Alternatively, the register configuration sub-circuit 101 may include at least one input terminal and at least one output terminal, and may receive information sent by the host or the logic address decoding chip selection sub-circuit 102 through one or two different input terminals, and may also send information to the host or the logic address decoding chip selection sub-circuit 102 through one or two different output terminals.

The logic address decoding chip selection sub-circuit 102 is respectively connected with the host, the register configuration sub-circuit 101 and the at least one or logic sub-circuit; the input end is used for receiving the access type, the access address and the control signal sent by the host, and the logic address grouping information and the associated configuration information of a plurality of external devices sent by the register configuration sub-circuit 101; the logic address decoding chip selecting sub-circuit 102 determines whether the access type, the type of the access address and the control signal meet a first preset condition, and if so, confirms at least two first external devices to be accessed by the host based on the access address, the logic address grouping information and the associated configuration information of the plurality of external devices.

Wherein the first preset condition includes: the access type is a write access, the type of access address is a logical address type, and the control signal is a valid control signal.

The output end of the logic address decoding chip selection sub-circuit 102 is configured to send a control signal and/or data to be written (i.e. access data) to the or logic sub-circuits corresponding to the at least two first external devices. The data to be written is sent by the host to the logical address decode chip select subcircuit 102.

In some optional embodiments, the input terminal of the logic address decoding chip selection sub-circuit 102 is further configured to receive logic address error access information and an identifier of a corresponding first external device sent by any one of the at least two first external devices, and send the logic address error access information and the identifier of the corresponding first external device to the register configuration sub-circuit 101 through the output terminal. Optionally, the logic address decoding chip selecting sub-circuit 102 may include at least one input terminal and at least one output terminal, and may receive information sent by the host, the register configuration sub-circuit 101, and the at least one first external device through one or more different input terminals, and may also send information to the host, the register configuration sub-circuit 101, and the at least one first external device through one or more different output terminals.

Specific applications of the register configuration sub-circuit 101 and the logic address decoding chip selection sub-circuit 102, including a processing manner of the received information, etc., may refer to the description of fig. 3, and will not be repeated here.

In some embodiments, the physical decode chip select sub-circuit 103 is configured to receive an access address and a control signal sent by the host, and if the control signal is a valid control signal and the type of the access address is a physical address type, confirm a second external device of the plurality of external devices based on the access address, so that the host accesses the second external device. I.e. the physical decode chip select sub-circuit 103 is adapted to handle accesses having an access address type of physical address.

In some embodiments, the physical decoding chip selection sub-circuit 103 is further configured to, if the control signal is not the valid control signal, not perform a subsequent operation, wait for receiving other access information sent by the host, where the valid control signal includes a specified signal under a different communication protocol; and if the type of the access address is a logic address type, sending access error information to the host so that the host sends the control signal and the access address to the logic address decoding chip selection sub-circuit.

In some embodiments, the physical address decoding chip select sub-circuit 103 can only determine one second external device based on the access address, because the physical address of each external device is different. It should be noted that the first external device and the second external device are both external devices inside the system-in-chip, that is, the external device 1, … … shown in fig. 3 or fig. 5, and any external device of the external devices n.

In some embodiments, the physical address decoding chip selecting sub-circuit 103 is connected to a second external device, and after the host accesses the second external device, the physical address decoding chip selecting sub-circuit 103 is further configured to receive physical address error access information sent by the second external device, and send the physical address error access information to the host, so that the host initiates access to the second external device again.

Because the physical address decoding chip selection sub-circuit 103 can only determine one external device at each access, the physical address error access information can be directly sent to the host without interruption, and the host knows the external device with the error access, because the type of the access address is the physical address type, only one external device can be determined, and the access address is sent by the host, and therefore, when the error access occurs, the host knows the external device with the error access.

In some embodiments, each or logic sub-circuit is configured to receive access information sent by the host through the logic address decoding chip selection sub-circuit or the physical address decoding chip selection sub-circuit, confirm whether an address of a first external device corresponding to the access information or an address of a second external device corresponding to the or logic sub-circuit matches an address of an external device corresponding to the or logic sub-circuit, and if so, allow the host to write data into the external device corresponding to the or logic sub-circuit, and if not, allow the host to write data into the external device corresponding to the or logic sub-circuit; the external equipment comprises any one of at least two first external equipment and second external equipment;

In other embodiments, the or logic sub-circuit functions as or logic, that is, the access information sent by the logic address decoding chip selection sub-circuit or the physical address decoding chip selection sub-circuit accords with logic, so that access to the corresponding external device can be realized.

Thus, by the data access circuit provided by the embodiment of the present disclosure, when a host wants to access to a plurality of external devices, the logic address decoding chip selection sub-circuit and the physical address decoding chip selection sub-circuit can respectively process access addresses of a logic address type and a physical address type, determine a peripheral to be accessed, and specifically, the logic address decoding chip selection sub-circuit can confirm at least two first external devices based on the access addresses, logic address grouping information and associated configuration information of the plurality of external devices; the physical address decoding chip selection sub-circuit can determine the second external equipment based on the access address, so that the host can write data into the at least two first external equipment in parallel, parallel access is realized, and the limitation caused by a time delay sensitive application scene is solved, or the data is written into the second external equipment.

Fig. 7 shows a first alternative flow diagram of a data access method provided by an embodiment of the present disclosure.

In step S601, the register configuration sub-circuit receives and transmits the logical address packet information and the associated configuration information of the plurality of external devices to the logical address decoding chip selection sub-circuit.

In some embodiments, the logical address packet information includes a start address segment and an end address segment corresponding to each logical address packet, and the association configuration information of the external device includes an enabling relationship between the external device and at least one logical address packet.

In step S602, the logic address decoding chip selector circuit parses the access type, the control signal and the access address, and performs a corresponding operation based on the parsing result.

In some embodiments, the logic address decoding chip selector circuit confirms whether the control signal is a valid control signal, if the control signal is not a valid control signal, the logic address decoding chip selector circuit does not execute subsequent operations, and waits for receiving other access information sent by the host;

if the control signal is an effective control signal, confirming the type of the access address, and if the type of the access address is a physical address type, sending access error information to the host so that the host sends the control signal and the access address to the physical address decoding chip selection sub-circuit; if the access address type is a logical address type, confirming whether the access type is a write operation type, and if the access type is a read operation type, sending access error information to the host; and if the access type is a write operation type, confirming at least two first external devices in the plurality of external devices based on the access address, the logical address grouping information and the associated configuration information of the plurality of external devices, so that the host accesses the at least two first external devices in parallel.

In the implementation, the logic address decoding chip selection sub-circuit confirms that the control signal is an effective control signal, the type of the access address is a logic address type, the access type meets the writing operation type, and confirms at least two first external devices in the external devices based on the access address, the logic address grouping information and the associated configuration information of the external devices; if any condition is not satisfied, no subsequent operation is performed.

In some embodiments, the logic address decoding chip select sub-circuit may acknowledge in order of control signal, type of access address, and access type, or in any order, and the disclosure is not particularly limited.

When the method is implemented, the logic address decoding chip selection sub-circuit confirms a first logic address packet corresponding to the access address based on the access address and logic address packet information; and based on the first logical address packet and the associated configuration information of the at least one external device, confirming at least two first external devices corresponding to the first logical address packet.

In some alternative embodiments, the method further comprises: receiving logic address error access information sent by any one of the at least two first external devices, and sending the logic address error access information and the identification of the corresponding first external device to the register configuration sub-circuit; the register configuration sub-circuit receives the logic address error access information and the identification corresponding to the first external device, which are sent by the logic address decoding chip selection sub-circuit, and sends the logic address error access information and the identification corresponding to the first external device to the host through the interrupt sub-circuit in the chip, so that the host initiates access to the corresponding first external device again.

Fig. 8 shows a second alternative flow diagram of a data access device provided by an embodiment of the present disclosure.

In step S701, a register configuration sub-circuit is initialized.

In some embodiments, the data access circuit initializes the register configuration sub-circuit, the register configuration sub-circuit receives the logical address grouping information and the associated configuration information of the plurality of external devices sent by the host device, and sends the logical address grouping information and the associated configuration information of the plurality of external devices to the physical address decoding chip selection sub-circuit.

In step S702, the data access circuit confirms whether the host transmits the access information.

In some embodiments, the data access circuit receives the information sent by the host, confirms whether the control signal included in the information is a valid control signal, if the control signal is a valid control signal, the data access circuit confirms that the host sends access information, that is, the access information, and if the control signal is not a valid control signal, the data access circuit confirms that the host does not send access information, waits for receiving other access information sent by the host, and repeats step S702. The access information may include at least one of an access type, an access address, and a control signal.

In some embodiments, step S702 may be performed by at least one of a logical address decoding chip select sub-circuit and a physical address decoding chip select sub-circuit included in the data access circuit.

If the step S702 is executed by a logic address decoding chip selecting sub-circuit, the step S703 is executed, and if the step S702 is executed by a physical address decoding chip selecting sub-circuit, the step S704 is executed; if both the logic address decoding chip select sub-circuit and the physical address decoding chip select sub-circuit execute the step S702, then step S703 and step S704 are executed.

In step S703, the logic address decoding chip select sub-circuit parses the access information.

In some embodiments, the access information includes a control signal, an access type, and an access address; the logic address decoding chip selection sub-circuit confirms whether the type of the access address is a logic address type, if the type of the access address is a physical address type, the access error information is sent to the host, and the subsequent steps are not executed any more. Specifically, if the type of the access address is a physical address type, the physical address decoding chip selection sub-circuit is used for processing, and the logic address decoding chip selection sub-circuit is not required to continue processing.

If the type of the access address included in the access information is a logical address type, confirming whether the access type is a write operation type, and if the access type is a read operation type, sending access error information to the host; and if the access type is a write operation type, confirming at least two first external devices in the plurality of external devices based on the access address, the logical address grouping information and the associated configuration information of the plurality of external devices, so that the host accesses the at least two first external devices in parallel.

In some embodiments, the logical address decode chip select sub-circuit may acknowledge in order of control signal, type of access address, and type of access.

In the implementation, the logic address decoding chip selection sub-circuit confirms that the control signal is an effective control signal, the type of the access address is a logic address type, the access type meets the writing operation type, and confirms at least two first external devices in the external devices based on the access address, the logic address grouping information and the associated configuration information of the external devices; if any condition is not satisfied, not executing

In step S704, the physical address decoding chip select sub-circuit parses the access information.

In some embodiments, the physical address decoding chip select sub-circuit confirms whether the type of the access address included in the access information is a logical address type, and if so, sends an access error message to the host.

And if the type of the access address is a physical address type, the physical address decoding chip selection sub-circuit confirms a second external device to be accessed based on the access address.

Step S705, the host accesses the external device to be accessed.

In some embodiments, the external device to be accessed may be at least two first external devices or second external devices.

Thus, by the data access method provided by the embodiment of the present disclosure, when a host wants to access to a plurality of external devices, the logic address decoding chip selection sub-circuit and the physical address decoding chip selection sub-circuit can respectively process access addresses of a logic address type and a physical address type, determine a peripheral to be accessed, and specifically, the logic address decoding chip selection sub-circuit can confirm at least two first external devices based on the access addresses, logic address grouping information and associated configuration information of the plurality of external devices; the physical address decoding chip selection sub-circuit can determine the second external equipment based on the access address, so that the host can write data into the at least two first external equipment in parallel, parallel access is realized, and the limitation caused by a time delay sensitive application scene is solved, or the data is written into the second external equipment.

In order to implement the data access method, an embodiment of the present disclosure further provides a system-on-chip, where the system-on-chip includes: the register configuration sub-circuit, the logic address decoding chip selection sub-circuit, the host and at least one external device;

In some alternative embodiments, the system on chip may further include a physical decode chip select sub-circuit; the connection relationship and the use of the register configuration sub-circuit, the logic address decoding chip selection sub-circuit, the physical address decoding chip selection sub-circuit, the host and the at least one external device are the same as those of the above (fig. 3 and 6), and the detailed description thereof will not be repeated.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

Fig. 9 shows a schematic block diagram of an example electronic device 800 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 9, the electronic device 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.

Various components in electronic device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the electronic device 800 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.

The computing unit 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as a data access method. For example, in some embodiments, the data access method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 800 via the ROM 802 and/or the communication unit 809. When a computer program is loaded into RAM 803 and executed by computing unit 801, one or more steps of the data access method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the data access method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A data access circuit for use with a system-on-chip, the data access circuit comprising: a register configuration sub-circuit and a logic address decoding chip selection sub-circuit;

2. The circuit of claim 1, wherein the logic address decoding chip select sub-circuit is connected to a plurality of first external devices, and after the host accesses the at least two first external devices, the logic address decoding chip select sub-circuit is further configured to receive logic address error access information sent by any one of the at least two first external devices, and send the logic address error access information and an identifier of a corresponding first external device to the register configuration sub-circuit;

the register configuration sub-circuit is further configured to receive the logic address error access information and the identifier of the corresponding first external device, which are sent by the logic address decoding chip selection sub-circuit, and send the logic address error access information and the identifier of the corresponding first external device to the host through the interrupt sub-circuit in the chip, so that the host initiates access to the corresponding first external device again.

3. The circuit of claim 1, wherein the logic address decode chip select sub-circuit is specifically configured for at least one of:

if the control signal is not the effective control signal, the subsequent operation is not executed, and other access information sent by the host is waited for to be received, wherein the effective control signal comprises specified signals under different communication protocols;

if the access type is a read operation type, sending access error information to the host;

and if the type of the access address is a physical address type, sending access error information to the host so that the host sends the control signal and the access address to a physical address decoding chip selection sub-circuit.

4. The circuit of claim 1, wherein the logic address decode chip select sub-circuit is specifically configured to:

confirming a first logical address packet corresponding to the access address based on the access address and the logical address packet information;

and based on the first logical address packet and the associated configuration information of the plurality of external devices, confirming at least two first external devices corresponding to the first logical address packet.

5. The circuit of claim 1, wherein the circuit further comprises:

And the physical address decoding chip selection sub-circuit is connected with the host, and is used for receiving an access address and a control signal sent by the host, and if the control signal is an effective control signal and the type of the access address is a physical address type, confirming a second external device in a plurality of external devices based on the access address so as to enable the host to access the second external device.

6. The circuit of claim 5, wherein the physical address decode chip select sub-circuit is coupled to the second peripheral device, the physical address decode chip select sub-circuit further configured to receive physical address error access information sent by the second peripheral device after the host accesses the second peripheral device, and send the physical address error access information to the host to cause the host to re-initiate access to the second peripheral device.

7. The circuit of claim 5, wherein the physical address decode chip select sub-circuit is specifically configured to at least one of:

And if the type of the access address is a logic address type, sending access error information to the host so that the host sends the control signal and the access address to the logic address decoding chip selection sub-circuit.

8. The circuit of claim 1 or 5, wherein the circuit further comprises:

each or logic sub-circuit is in one-to-one correspondence with an external device, and is respectively connected with the logic address decoding chip selection sub-circuit, a physical address decoding chip selection sub-circuit in the logic address decoding chip selection sub-circuit and the corresponding external device, and each or logic sub-circuit is used for receiving access information sent by the host through the logic address decoding chip selection sub-circuit or the physical address decoding chip selection sub-circuit, confirming whether an address of a first external device or an address of a second external device corresponding to the access information is matched with an address of the external device corresponding to the or logic sub-circuit, if so, allowing the host to write data into the external device corresponding to the or logic sub-circuit, and if not, not allowing the host to write data into the external device corresponding to the or logic sub-circuit;

The external equipment comprises any one of at least two first external equipment and second external equipment.

9. A method of data access, applied to a system-on-chip, the method comprising:

10. A system-on-chip, the system-on-chip comprising: the register configuration sub-circuit, the logic address decoding chip selection sub-circuit, the host and at least one external device;