CN116974957A

CN116974957A - System protection circuit, chip system, reset method, device and storage medium

Info

Publication number: CN116974957A
Application number: CN202310834111.1A
Authority: CN
Inventors: 王振
Original assignee: Nanjing Semidrive Technology Co Ltd
Current assignee: Nanjing Semidrive Technology Co Ltd
Priority date: 2023-07-07
Filing date: 2023-07-07
Publication date: 2023-10-31

Abstract

The application provides a system protection circuit, a chip system, a resetting method, equipment and a storage medium, wherein the circuit comprises: the system comprises a plurality of target modules, a bus circuit, a reset control circuit and a reset protection circuit, wherein the target modules are host circuits or slave circuits, the target modules comprise at least one host circuit and at least one slave circuit, the host circuits are connected with the slave circuits through the bus circuit, the reset control circuit is respectively connected with the bus circuit and the target modules, and the reset protection circuit is respectively connected with the bus circuit and the reset control circuit; the reset protection circuit is used for acquiring a reset request, processing a target task corresponding to the designated target module, and outputting a response signal when the bus circuit is idle; the system protection circuit provided by the application enables the system to work more smoothly and improves the system performance.

Description

System protection circuit, chip system, reset method, device and storage medium

Technical Field

The present application relates to the field of integrated circuits, and in particular, to a system protection circuit, a chip system, a reset method, a reset device, and a storage medium.

Background

A multichip system is generally a system in which a multi-master circuit and a multi-slave circuit are connected by a bus. In the system design, reset control needs to be added to each of the master circuit and the slave circuit. When the circuit system is designed, each system needs to have a control unit capable of correctly resetting the whole system, and when the system is powered on, the global reset control is carried out on each unit circuit and chip in the system. For the chip, it is also necessary to ensure that the chip resets when powered on, and initialize the various parts inside the chip to ensure that the various parts inside the chip enter a certain state.

When designing the circuit system, a special reset control module is generally arranged in the system, and the reset control module can transmit corresponding hard reset signals to the corresponding slave circuit or the corresponding master circuit so as to achieve the reset effect. Because the reset control module transmits the hard reset signal and the host circuit transmits the reset operation instruction, if the reset happens, the whole bus system is likely to hang up after the reset is released when the bus has the transaction which is not transmitted completely.

Disclosure of Invention

The application provides a system protection circuit, a chip system, a resetting method, equipment and a storage medium, which at least solve the technical problems in the prior art.

According to a first aspect of the present application, there is provided a system protection circuit, the circuit comprising: the system comprises a plurality of target modules, a bus circuit, a reset control circuit and a reset protection circuit, wherein the target modules are host circuits or slave circuits, the target modules comprise at least one host circuit and at least one slave circuit, the host circuit is connected with the slave circuits through the bus circuit, the reset control circuit is respectively connected with the bus circuit and the target modules, and the reset protection circuit is respectively connected with the bus circuit and the reset control circuit; the reset control circuit is used for outputting a reset request corresponding to a reset instruction, wherein the reset instruction is from the host circuit and is used for carrying out hard reset on a specified target module; the reset protection circuit is used for acquiring the reset request, processing the target task corresponding to the specified target module, and outputting a response signal when the bus state corresponding to the specified target module is idle; and the reset control circuit is also used for carrying out hard reset on the appointed target module when the response signal is acquired.

In an embodiment, the number of the host circuits and/or the slave circuits is plural, the bus circuit includes a bus control circuit, a first branch and a second branch, the first branch is connected between the bus control circuit and the host circuit, and the second branch is connected between the bus control circuit and the slave circuit; the bus control circuit is used for establishing a transmission relation between the host circuit and the slave circuit based on preset logic; the preset logic is as follows: at least one of circuit identification based control logic and priority based control logic.

In an implementation manner, the reset protection circuit comprises a first protection sub-circuit and a second protection sub-circuit, the first protection sub-circuit is connected with the first branch, the second protection sub-circuit is connected with the second branch, and the target task comprises a new transaction and/or a residual transaction; the first protection sub-circuit is used for limiting the first branch to transmit new transactions corresponding to the specified host circuit and/or transmit residual transactions corresponding to the specified host circuit based on a reset request of the corresponding specified host circuit, detecting signals of the first branch, and outputting response signals when the bus state corresponding to the specified host circuit is idle; and the second protection sub-circuit is used for limiting the second branch circuit to transmit new transactions corresponding to the appointed slave circuit and/or transmit residual transactions corresponding to the appointed slave circuit based on a reset request corresponding to the appointed slave circuit, detecting signals of the second branch circuit, and outputting response signals when the bus state corresponding to the appointed slave circuit is idle.

In an embodiment, the number of the slave circuits is a plurality, the reset control circuit includes a master reset control sub-circuit, the first protection sub-circuit includes a first limiting sub-circuit, a first transmission sub-circuit, and a first detection sub-circuit, and the first limiting sub-circuit, the first transmission sub-circuit, and the first detection sub-circuit are all connected with the first branch circuit; the host reset control sub-circuit is used for outputting a reset request of a corresponding appointed host circuit to the first protection sub-circuit; the first limiting sub-circuit is used for limiting a first command control signal transmitted by the first branch circuit, and the first command control signal is used for representing whether a new transaction corresponding to the designated host circuit exists or not; the first transmission sub-circuit is used for transmitting a first data control signal transmitted by the first branch circuit, and the first data control signal is used for representing whether residual transactions corresponding to the designated host circuit exist or not; the first detection sub-circuit is configured to detect a first bus state signal transmitted by the first branch, where the first bus state signal is used to characterize whether a bus state corresponding to the specified host circuit is idle.

In an embodiment, the first limiting sub-circuit includes: the first configuration unit is used for configuring a first command control signal, and when the first command control signal is at a low level, the first branch stops transmitting new transactions corresponding to the appointed host circuit; wherein the number of the first command control signals is at least one; the first transmission sub-circuit includes: the second configuration unit is used for configuring a first data control signal, and when the first data control signal is at a high level, the first branch transmits residual transactions corresponding to the appointed host circuit; wherein the number of the first data control signals is at least one; the first detection subcircuit includes: and the first detection unit is used for determining that the bus state corresponding to the specified host circuit is idle when the first bus state signal is detected to be at a high level.

In an embodiment, the first branches are multiple, and the multiple first branches are respectively connected with the bus control circuit and the designated host circuit, and each first branch is provided with the first protection subcircuit; a plurality of slave circuits configured as different slave IP addresses; the bus control circuit is used for establishing a slave machine transmission relation between a slave machine and a corresponding first branch circuit based on the slave machine IP address.

In an embodiment, the device further comprises a first fan-out circuit and a first response circuit, wherein the first fan-out circuit is respectively connected with the host reset control sub-circuit and the first branch circuit, and the first response circuit is respectively connected with the host reset control sub-circuit and the first branch circuit; the first fan-out circuit is used for transmitting the reset request to all first protection sub-circuits through fan-out logic; the first response circuit is used for sending an effective response signal to the host reset control sub-circuit when receiving response signals of all the first protection sub-circuits.

In an embodiment, the number of the host circuits is a plurality, the reset control circuit includes a slave reset control sub-circuit, the second protection sub-circuit includes a second limiting sub-circuit, a second transmission sub-circuit, and a second detection sub-circuit, and the second limiting sub-circuit, the second transmission sub-circuit, and the second detection sub-circuit are all connected with the second branch circuit; the slave reset control sub-circuit is used for outputting a reset request corresponding to the appointed slave circuit to the second protection sub-circuit; the second limiting sub-circuit is used for limiting a second command control signal transmitted by the second branch circuit, and the second command control signal is used for transmitting a new transaction corresponding to the appointed slave circuit; the second transmission sub-circuit is used for transmitting a second data control signal transmitted by the second branch circuit, and the second data control signal is used for transmitting a residual transaction corresponding to the appointed slave circuit; the second detection sub-circuit is configured to detect a second bus state signal transmitted by the second branch, where the second bus state signal is used to characterize whether the bus state corresponding to the specified slave circuit is idle.

In an embodiment, the second limiting sub-circuit includes: a third configuration unit, configured to configure a second command control signal, where when the second command control signal is at a low level, the second branch stops transmitting a new transaction corresponding to the specified slave circuit; wherein the number of the second command control signals is at least one; the second transmission sub-circuit includes: a fourth configuration unit, configured to configure a second data control signal, where when the second data control signal is at a high level, the second branch transmits a residual transaction corresponding to the specified slave circuit; wherein the number of the second data control signals is at least one; the second detection subcircuit includes: and the second detection unit is used for determining that the bus state corresponding to the specified host circuit is idle when the second bus state signal is detected to be at a high level.

In an embodiment, the number of the second branches is multiple, and the second branches are respectively connected with the bus control circuit and the designated slave circuit, and each second branch is provided with the second protection sub-circuit; a plurality of host circuits configured to different host index numbers; the bus control circuit is used for establishing a host transmission relation between the host circuit and the corresponding second branch circuit based on the host index number.

In an implementation manner, the system further comprises a second fan-out circuit and a second response circuit, wherein the second fan-out circuit is respectively connected with the slave reset control sub-circuit and the second branch circuit, and the second response circuit is respectively connected with the slave reset control sub-circuit and the second branch circuit; the second fan-out circuit is used for transmitting the reset request to all second protection sub-circuits through fan-out logic; and the second response circuit is used for sending an effective response signal to the slave reset control sub-circuit when receiving response signals of all the second protection sub-circuits.

According to a second aspect of the present application, there is provided a chip system comprising a system protection circuit, the circuit comprising: the device comprises a plurality of target chips, a bus circuit, a reset control circuit and a reset protection circuit, wherein the target chips are master chips or slave chips, the target chips comprise at least one master chip and at least one slave chip, the master chips are connected with the slave chips through the bus circuit, the reset control circuit is respectively connected with the bus circuit and the target chips, and the reset protection circuit is respectively connected with the bus circuit and the reset control circuit; the reset control circuit is used for outputting a reset request corresponding to a reset instruction, wherein the reset instruction is from the main chip, and the reset instruction is used for carrying out hard reset on a specified target chip; the reset protection circuit is used for acquiring the reset request, detecting the bus circuit, and outputting a response signal when the current task corresponding to the appointed target chip is detected to be completed; the reset control circuit is further used for performing hard reset on the specified target chip when the response signal is acquired.

According to a third aspect of the present application, there is provided a reset method, the method being applied to a system protection circuit, the circuit comprising: the device comprises a plurality of target modules, a bus circuit, a reset control circuit and a reset protection circuit, wherein the target modules are host circuits or slave circuits, the target modules comprise at least one host circuit and at least one slave circuit, the host circuit is connected with the slave circuits through the bus circuit, the reset control circuit is respectively connected with the bus circuit and the target modules, and the reset protection circuit is respectively connected with the bus circuit and the reset control circuit, and the method comprises the following steps: the reset control circuit outputs a reset request corresponding to a reset instruction, wherein the reset instruction is from the host circuit and is used for carrying out hard reset on a specified target module; the reset protection circuit acquires the reset request, processes the target task corresponding to the designated target module, and outputs a response signal when the bus state corresponding to the designated target module is idle; and the reset control circuit performs hard reset on the appointed target module when acquiring the response signal.

According to a fourth aspect of the present application, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of the present application.

According to a fifth aspect of the present application there is provided a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of the present application.

According to the system protection circuit, the chip system, the reset method, the device and the storage medium, provided by the embodiment of the application, the target tasks corresponding to the specified target modules are processed based on the reset protection circuit, so that the specified target modules can be subjected to hard reset when the bus states corresponding to the specified target modules are idle, the problem of system suspension caused by the fact that other target modules are not reset when the specified target modules are reset is solved, and the system stability is improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the application or to delineate the scope of the application. Other features of the present application will become apparent from the description that follows.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present application are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

FIG. 1 is a schematic diagram of a system protection circuit according to a first embodiment of the present application;

FIG. 2 is a schematic diagram of a system protection circuit according to a second embodiment of the present application;

FIG. 3 is a schematic diagram of a system protection circuit according to a third embodiment of the present application;

FIG. 4 is a schematic diagram of a system protection circuit according to a fourth embodiment of the present application;

fig. 5 is a schematic circuit diagram showing a system protection circuit according to a third embodiment of the present application;

FIG. 6 is a timing diagram of a system protection circuit according to a third embodiment of the present application;

fig. 7 is a schematic circuit diagram showing a system protection circuit according to a fourth embodiment of the present application;

FIG. 8 is a timing diagram of a system protection circuit according to a fourth embodiment of the present application;

FIG. 9 is a schematic diagram of an implementation module of a system-on-chip according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a reset method according to an embodiment of the present application;

fig. 11 is a schematic diagram showing a composition structure of an electronic device according to an embodiment of the present application.

Wherein, the reference numerals are as follows: 100. a reset control circuit; 110. a host reset control sub-circuit; 120. resetting a control sub-circuit of the slave; 200. a reset protection circuit; 210. a first protection subcircuit; 211. a first limiting sub-circuit; 212. a first transmission sub-circuit; 213. a first detection subcircuit; 220. a second protection subcircuit; 221. a second limiting sub-circuit; 222. a second transmission sub-circuit; 223. a second detection subcircuit; 300. a slave circuit; 400. a bus circuit; 410. a first branch; 420. a bus control circuit; 430. a second branch; 500. a host circuit; 610. a first fan-out circuit; 620. a first response circuit; 710. a second fan-out circuit; 720. a second response circuit; 800. a slave chip; 900. and a main chip.

Detailed Description

In order to make the objects, features and advantages of the present application more comprehensible, the technical solutions according to the embodiments of the present application will be clearly described in the following with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

FIG. 1 is a schematic diagram of a system protection circuit according to a first embodiment of the present application; FIG. 2 is a schematic diagram of a system protection circuit according to a second embodiment of the present application; FIG. 3 is a schematic diagram of a system protection circuit according to a third embodiment of the present application; fig. 4 is a schematic diagram of an implementation module of a system protection circuit according to a fourth embodiment of the present application.

With reference to fig. 1 to 4, according to a first aspect of the present application, there is provided a system protection circuit, the circuit comprising: the device comprises a plurality of target modules, a bus circuit 400, a reset control circuit 100 and a reset protection circuit 200, wherein the target modules are a host circuit 500 or a slave circuit 300, the plurality of target modules comprise at least one host circuit 500 and at least one slave circuit 300, the host circuit 500 is connected with the slave circuit 300 through the bus circuit 400, the reset control circuit 100 is respectively connected with the bus circuit 400 and the target modules, and the reset protection circuit 200 is respectively connected with the bus circuit 400 and the reset control circuit; the reset control circuit 100 is configured to output a reset request corresponding to a reset instruction, where the reset instruction is from the host circuit 500, and the reset instruction is used to perform hard reset on the specified target module; the reset protection circuit 200 is configured to obtain a reset request, process a target task corresponding to a specified target module, and output a response signal when a bus state corresponding to the specified target module is idle; the reset control circuit 100 is further configured to perform a hard reset on the specified target module when the response signal is acquired.

According to the system protection circuit provided by the embodiment of the application, the reset control circuit 100 and the reset protection circuit 200 are arranged in the circuit, the target tasks corresponding to the designated target modules are processed based on the reset protection circuit 200, and when the bus state corresponding to the designated target modules is idle, the response signals are output to the reset control circuit 100, so that the designated target modules can be subjected to hard reset when the corresponding bus state is idle, the tasks corresponding to the designated target modules cannot remain in the circuit, the problem that the other target modules cannot be reset when the designated target modules are reset, the system hanging problem possibly caused is solved, the system stability is improved, the system work is smoother, and the system performance is improved.

The system protection circuit provided by the embodiment of the application can be applied to a System On Chip (SOC). The target module may be one of the hardware used to construct the SOC chip, including but not limited to: core, memory module, interrupt module, clock module. The target modules may be divided into two types of the host circuit 500 and the slave circuit 300 according to target functions corresponding to different hardware, wherein the host circuit 500 is used to characterize hardware having authority to send a reset instruction, such as a core (core). The slave 300 is used to characterize hardware, such as a memory module, that does not have the authority to send a reset instruction.

Based on the specific number of master circuits 500 and slave circuits 300, the system protection circuit provided by the embodiments of the present application is applicable to the four scenarios shown in fig. 1 to 4: a scenario with one master circuit 500 and one slave circuit 300, a scenario with one master circuit 500 and multiple slave circuits 300, a scenario with multiple master circuits 500 and one slave circuit 300, a scenario with multiple master circuits 500 and multiple slave circuits 300.

Referring to fig. 1, a system protection circuit is provided having a master circuit 500 and a slave circuit 300. The master circuit 500 and the slave circuit 300 are connected by a bus circuit 400, and the bus circuit 400 is used for data and signal transfer between the master circuit 500 and the slave circuit 300.

The input end of the reset control circuit 100 is connected with the output ends of the bus circuit 400 and the reset protection circuit 200 respectively, and the output end of the reset control circuit 100 is connected with the input ends of the bus circuit 400, the reset protection circuit 200, the host circuit 500 and the slave circuit 300 respectively. The input terminal of the reset control circuit 100 acquires a reset instruction transmitted by the bus circuit 400, and the reset instruction is issued by the host circuit 500. The reset instruction may be an instruction for instructing the host circuit 500 to perform a self-reset or an instruction for instructing the slave circuit 300 to perform a hard reset.

After the reset control circuit 100 obtains the reset instruction, a specified target module is determined according to the reset instruction, that is, the specified target module is determined to be a specified host circuit or a specified slave circuit, and a reset request corresponding to the specified target module is output, where the reset request is used to instruct the reset protection circuit 200 to process a target task corresponding to the specified target module, and when a bus state corresponding to the specified target module is idle, a response signal is output.

The number of the reset protection circuits 200 may be kept identical to the number of the target modules, so that the reset protection circuits correspond to the target modules one by one. When there are a plurality of reset protection circuits, the plurality of reset protection circuits are all disposed on the bus circuit 400. The input of the reset protection circuit 200 obtains a reset request, and processes a target task corresponding to a specified target module according to the reset request, where the target task is a bus transmission transaction related to the specified target module, and the target task includes, but is not limited to, a new transaction related to the specified target module, which needs to be transmitted through the bus circuit 400, and a residual transaction related to the specified target module, which needs to be transmitted through the bus circuit 400.

The reset protection circuit 200 processes the target task, so that the bus state corresponding to the designated target module is idle as soon as possible, and the bus state corresponding to the designated target module is idle to represent that no bus transmission transaction related to the designated target module is performed on the bus circuit 400. The reset protection circuit 200 outputs a response signal through an output terminal when the bus state corresponding to the specified target module is idle.

The input end of the reset control circuit 100 acquires the response signal, and after the reset control circuit 100 acquires the response signal, the output end sends a hard reset instruction to the appointed target module, so that the appointed target module is subjected to hard reset. By the reset protection circuit 200, the specified target module can be ensured to be safely and smoothly reset hard without software control. Compared with the hard reset operation by software, the reset protection circuit 200 can enable the bus state corresponding to the designated target module to be idle as soon as possible, and can reduce the resource consumption without waiting for too long time.

Referring to fig. 2 to 4, in an embodiment, the number of the master circuit 500 and/or the slave circuit 300 is plural, the bus circuit 400 includes a bus control circuit 420, a first branch 410, and a second branch 430, the first branch 410 is connected between the bus control circuit 420 and the master circuit 500, and the second branch 430 is connected between the bus control circuit 420 and the slave circuit 300; a bus control circuit 420 for establishing a transmission relationship between the master circuit 500 and the slave circuit 300 based on preset logic; the preset logic is as follows: at least one of circuit identification based control logic and priority based control logic.

The circuit has three scenes of one master circuit 500 and a plurality of slave circuits 300, a circuit has a plurality of master circuits 500 and a plurality of slave circuits 300, and a circuit has a plurality of master circuits 500 and a plurality of slave circuits 300. Since the master circuit 500 and/or the slave circuit 300 may be plural, the bus circuit 400 includes a bus control circuit 420, a first branch 410, and a second branch 430. Each of the host circuits 500 is connected to the bus control circuit 420 through the first branch 410, each of the slave circuits 300 is connected to the bus control circuit 420 through the second branch 430, and a transmission relationship between any one of the host circuits 500 and any one of the slave circuits 300 is established through the bus control circuit 420 according to a preset logic, and further, the bus control circuit 420 can be further used for establishing a transmission relationship between any two of the host circuits 500 and a transmission relationship between any two of the slave circuits 300.

In one implementation scenario, different host circuits 500 may be configured with different host index numbers as circuit identifications of the host circuits, the host index number of each host circuit being fixed, and different slave circuits 300 may be configured with different slave IP addresses as circuit identifications of the slave circuits, and bus control circuit 420 may establish a transmission relationship through the host index numbers and the slave IP addresses.

In another implementation scenario, different host circuits 500 and slave circuits 300 may be configured with different priorities, and the bus control module may establish a transmission relationship between the plurality of host circuits 500 and/or the plurality of slave circuits 300 with different priorities to ensure that bus transmission transactions can proceed smoothly.

In yet another implementation scenario, the different host circuitry 500 and slave circuitry 300 have both corresponding IP addresses and corresponding priorities, and in a conventional transmission task, the bus control circuitry 420 may establish a transmission relationship through the host index number and the slave IP address. When there are multiple transmission transactions for the same master circuit 500 or slave circuit 300, the bus control module may order the multiple transmission transactions by priority to ensure that the bus transmission transactions can proceed smoothly.

In an embodiment, the reset protection circuit 200 includes a first protection sub-circuit 210 and a second protection sub-circuit 220, the first protection sub-circuit 210 is connected to the first branch 410, the second protection sub-circuit 220 is connected to the second branch 430, and the target task includes a new transaction and/or a residual transaction; the first protection sub-circuit 210 is configured to limit, based on a reset request corresponding to the specified host circuit, the first branch 410 to transmit a new transaction corresponding to the specified host circuit and/or transmit a residual transaction corresponding to the specified host circuit, and perform signal detection on the first branch 410, and output a response signal when a bus state corresponding to the specified host circuit is idle; the second protection sub-circuit 220 is configured to limit the second branch circuit 430 to transmit a new transaction corresponding to the specified slave circuit and/or transmit a residual transaction corresponding to the specified slave circuit based on a reset request corresponding to the specified slave circuit, and perform signal detection on the second branch circuit 430, and output a response signal when the bus state corresponding to the specified slave circuit is idle.

The circuit has three scenes of one master circuit 500 and a plurality of slave circuits 300, a circuit has a plurality of master circuits 500 and a plurality of slave circuits 300, and a circuit has a plurality of master circuits 500 and a plurality of slave circuits 300.

Because of a certain difference between the processing detection modes of the master circuit 500 and the slave circuit 300, the reset protection circuit 200 can accurately process and detect the designated target module. In the embodiment of the present application, the reset protection circuit 200 includes a first protection sub-circuit 210 and a second protection sub-circuit 220. The first protection sub-circuit 210 is connected to the first branch 410 and to the reset control circuit 100, and the first protection sub-circuit 210 acquires a reset request from the reset control circuit 100 for the specified host circuit, so as to process and detect a target task related to the specified host circuit. The second protection sub-circuit 220 is connected to the second branch circuit 430 and to the reset control circuit 100, and the second protection sub-circuit 220 acquires a reset request from the reset control circuit 100 for the specified slave circuit, and processes and detects the target task related to the specified slave circuit.

Specifically, the target tasks include new transactions and/or residual transactions. The newly created transaction is used to refer to various commands generated by the host circuit 500 for issuing to other slave circuits 300 and the host circuit 500. The residual transaction is used to refer to feedback information corresponding to the command, and the feedback information may be a simple feedback signal or a data signal fed back according to the command.

The first protection subcircuit 210 is configured to limit the first leg 410 from transmitting new transactions destined for the output of the host circuit. The first protection subcircuit 210 is also used to transfer the residual transaction to the designated host circuit to completion as soon as possible. The first protection sub-circuit 210 may determine whether the bus state corresponding to the first branch 410 is idle by detecting the bus state of the first branch 410, and output the response signal when the bus state corresponding to the first branch 410 is idle. When the first branch transmits a new transaction of the designated host circuit, if the first protection sub-circuit 210 has a reset request at this time, the first protection sub-circuit 210 will not transmit the new transaction to the slave circuit 300, so that the bus residual transaction can be processed as soon as possible, and the bus can reach an idle state as soon as possible.

Similarly, the second protection sub-circuit 220 is configured to limit the transmission of the second leg 430 to new transactions to the designated slave circuit, which may be from any host circuit 500. The second protection sub-circuit 220 is also used to send the residual transactions output by a given slave circuit to the corresponding master circuit 500 or other slave circuit 300 as soon as possible. The second protection sub-circuit 220 determines whether the bus state corresponding to the designated slave circuit is idle by detecting the bus state of the second branch circuit 430, and outputs a response signal when the bus state corresponding to the designated slave circuit is idle.

Referring to fig. 3 and 5, in an embodiment, the number of slave circuits 300 is plural, the reset control circuit 100 includes a master reset control sub-circuit 110, the first protection sub-circuit 210 includes a first limit sub-circuit 211, a first transmission sub-circuit 212, and a first detection sub-circuit 213, and the first limit sub-circuit 211, the first transmission sub-circuit 212, and the first detection sub-circuit 213 are all connected to the first branch circuit 410; a host reset control sub-circuit 110 for outputting a reset request corresponding to a designated host circuit to the first protection sub-circuit 210; a first limiting sub-circuit 211, configured to limit a first command control signal transmitted by the first branch 410, where the first command control signal is used to characterize whether a new transaction corresponding to the designated host circuit exists; a first transmitting sub-circuit 212, configured to transmit a first data control signal transmitted by the first branch 410, where the first data control signal is used to characterize whether a residual transaction corresponding to the specified host circuit exists; the first detection sub-circuit 213 is configured to detect a first bus state signal transmitted by the first branch 410, where the first bus state signal is used to indicate whether the bus state corresponding to the first branch 410 is idle.

One implementation specific scenario is provided below for the case where a circuit has one master circuit 500 and multiple slaves 300.

In this scenario, the number of slave circuits 300 is multiple, each slave circuit 300 being connected to the bus control circuit 420 through a corresponding second branch 430. The reset control circuit 100 includes a host reset control sub-circuit 110, the host reset control sub-circuit 110 being connected to the bus control circuit 420 for performing a host hard reset of a designated host circuit.

The first protection sub-circuit 210 may be disposed on the first branch 410, so that the signal transmitted by the first branch 410 can pass through the first protection sub-circuit 210. Correspondingly, when the first protection sub-circuit 210 does not acquire the reset request for the specified host circuit, the transparent state is maintained. When the first protection sub-circuit 210 acquires the reset request, the signal and the data transmitted by the first branch 410 are processed and detected by the first limiting sub-circuit 211, the first transmitting sub-circuit 212 and the first detecting sub-circuit 213, respectively.

Specifically, the first limiting sub-circuit 211 obtains the first command control signal, and determines whether the designated host circuit outputs the new transaction according to the first command control signal, and when the designated host circuit outputs the new transaction according to the first command control signal, the first command control signal is configured to limit the bus circuit 400 to transmit the new transaction output by the designated host circuit.

The first data control signal is acquired by the first transmission sub-circuit 212, and according to the first data control signal, whether the designated host circuit needs to receive the feedback residual transaction can be determined.

The first detection sub-circuit 213 obtains the first bus status signal, and can determine whether the bus status corresponding to the first branch 410 is idle according to the first bus status signal, and when the bus status corresponding to the first branch 410 is idle, it indicates that there is no new transaction corresponding to the designated host circuit or no residual transaction corresponding to the designated host circuit on the bus circuit 400. At this time, the response signal may be fed back to the host reset control sub-circuit 110, so that the host reset control sub-circuit 110 sends a host hard reset instruction to the specified host circuit, and performs host hard reset processing on the specified host circuit.

In one embodiment, the first limiting sub-circuit 211 includes: a first configuration unit (not shown in the figure) configured to configure the first command control signal, and when the first command control signal is at a low level, the first branch 410 stops transmitting the new transaction corresponding to the designated host circuit; wherein the number of the first command control signals is at least one; the first transmission sub-circuit 212 includes: a second configuration unit (not shown in the figure) configured to configure the first data control signal, and when the first data control signal is at a high level, the first branch 410 transmits the residual transaction corresponding to the designated host circuit; wherein the number of the first data control signals is at least one; the first detection subcircuit 213 includes: a first detecting unit (not shown in the figure) is configured to determine that the bus state corresponding to the designated host circuit is idle when the first bus state signal is detected to be at a high level.

The first configuration unit may be configured to control the first command control signal to remain at a low level, and when the first command control signal is at a low level, the bus circuit 400 stops transmitting a new transaction corresponding to a designated host circuit. Wherein the type and number of first command control signals used by different bus circuits 400 may be different depending on the bus type of the bus circuit 400. The embodiment of the present application determines the corresponding first command control signal according to the type of the bus circuit 400. For example, the first command control signal may be a read command flow control signal and a read command valid signal, and may further be selected as a read command flow control signal transmitted to a designated host circuit and a read command valid signal transmitted to any slave circuit 300.

Fig. 6 shows a timing diagram of a system protection circuit according to a third embodiment of the present application.

Referring to fig. 6, fig. 6 is a timing diagram for characterizing the first protection sub-circuit when the bus is an AXI bus. In the AXI bus, the first command control signals are selected as the array_m and the array_s, so that the array_m=0 sent to the designated host circuit and the array_s=0 sent to any slave circuit 300 achieve the purpose that the bus circuit 400 does not transmit the new transaction corresponding to the designated host circuit.

The second configuration unit may be configured to control the first data control signal to be kept at a high level, and when the first data control signal is at a high level, the bus circuit 400 may transmit the residual transaction required to be transmitted to the designated host circuit as soon as possible. Similarly, the type and number of first data control signals used by different bus circuits 400 may be different depending on the bus type of the bus circuit 400. For example, the first data control signal may be a read data flow control signal, further selected as a read data flow control signal transmitted to any slave circuit 300. For example, in the AXI bus, the first data control signal is selected as rready_s, so that rready_s=1 sent to any slave 300, and the purpose of the bus circuit 400 to transfer the residual transaction transferred to the designated host circuit as soon as possible is achieved.

Similarly, the first detecting unit may perform level detection on the passing first bus state signal, and determine that the bus state corresponding to the first branch 410 is idle when the first bus state signal is at a high level. The first bus state signals corresponding to the different bus circuits 400 are different, and in the AXI bus, the detection may be performed by the bus_idle signal, when the bus_idle signal is at a high level, the bus state corresponding to the first branch 410 is idle, and when the bus_idle signal is at a low level, the bus state corresponding to the first branch 410 is not idle.

It should be added that in the AXI bus, the rst_req signal corresponding to the host reset control sub-circuit is used to characterize the reset request, and when the reset request is sent to the first protection sub-circuit, the signal is configured to rst_req=1. The rst_ack signal is used to characterize the reply signal, and when the first protection subcircuit returns the reply signal, the signal is configured to rst_ack=1. The mst_rst signal is used for representing a hard reset instruction, the host reset control sub-circuit sends the hard reset instruction to the designated host circuit after receiving an effective response, the signal is configured to be mst_rst=0, and meanwhile, the host reset control sub-circuit stops sending a reset request, and the signal is configured to be rst_req=0. The hard reset is released, the signal is configured to be mst_rst=1, the transaction can be normally transmitted between the host circuit and the slave circuit, and the system works normally.

In an embodiment, the first branches 410 are plural, and the plural first branches 410 are respectively connected to the bus control circuit 420 and the designated host circuit, and each first branch 410 is provided with a first protection sub-circuit 210; a plurality of slave circuits 300 configured as different slave IP addresses; the bus control circuit 420 is configured to establish a slave transmission relationship between the slave circuit 300 and the corresponding first branch 410 based on the slave IP address.

A host circuit 500 may be connected to the bus control circuit 420 through a plurality of first branches 410, and a first protection sub-module is disposed on each first branch 410. So configured, when the circuit transaction is complex, the rapid transmission of signals and data can be achieved through the plurality of first branches 410. In such an implementation scenario, the plurality of slave circuits 300 may be configured as different slave IP addresses, and the bus control circuit 420 establishes a slave transmission relationship between the different slave circuits 300 and the corresponding first branches 410 based on the slave IP addresses, so as to achieve reasonable distribution and rapid transmission of signals and data on the first branches 410.

In an embodiment, the fan-out circuit further includes a first fan-out circuit 610 and a first response circuit 620, where the first fan-out circuit 610 is connected to the host reset control sub-circuit 110 and the first branch 410, and the first response circuit 620 is connected to the host reset control sub-circuit 110 and the first branch 410, respectively; a first fanout circuit 610 for transmitting a reset request to all the first protection sub-circuits 210 through the fanout logic; the first response circuit 620 is configured to send an effective response signal to the host reset control sub-circuit 110 when receiving response signals of all the first protection sub-circuits 210.

In the case where there are multiple first branches 410 and multiple first protection sub-modules, the host reset control sub-circuit 110 needs to transmit a reset request to each first protection sub-module associated with a given host circuit through the first fanout circuit 610. Correspondingly, a first response circuit 620 needs to be set in the circuit to receive the response signal sent by each first protection sub-module, and through response and logic, if all the first protection sub-modules send response signals, the response signal is forwarded to the host reset control sub-circuit 110, so that the host reset control sub-circuit 110 performs host hard reset on the designated host circuit.

Referring to fig. 4 and 7, in an embodiment, the number of the host circuits 500 is plural, the reset control circuit 100 includes a slave reset control sub-circuit 120, the second protection sub-circuit 220 includes a second limiting sub-circuit 221, a second transmitting sub-circuit 222, and a second detecting sub-circuit 223, and the second limiting sub-circuit 221, the second transmitting sub-circuit 222, and the second detecting sub-circuit 223 are all connected to the second branch circuit 430; a slave reset control sub-circuit 120 for outputting a reset request corresponding to a designated slave circuit to the second protection sub-circuit 220; a second limiting sub-circuit 221, configured to limit a second command control signal transmitted by the second branch 430, where the second command control signal is used to transmit a new transaction corresponding to the specified slave circuit; a second transmitting sub-circuit 222 for transmitting a second data control signal transmitted by the second branch 430, the second data control signal being used for transmitting a residual transaction corresponding to the specified slave circuit; the second detection subcircuit 223 is configured to detect a second bus state signal transmitted by the second branch 430, where the second bus state signal is used to indicate whether the bus state corresponding to the second branch 430 is idle.

One implementation specific scenario is provided below for the case where a circuit has multiple master circuits 500 and one slave circuit 300.

In this scenario, the number of host circuits 500 is multiple, each host circuit 500 being connected to the bus control circuit 420 through a corresponding first leg 410. The reset control circuit 100 includes a slave reset control sub-circuit 120, and the slave reset control sub-circuit 120 is connected to the bus control circuit 420 for performing a slave hard reset on a specified slave.

The second protection sub-circuit 220 may be disposed on the second branch 430 such that the signal transmitted by the second branch 430 can pass through the second protection sub-circuit 220. Correspondingly, when the second protection sub-circuit 220 does not acquire a reset request for the specified slave circuit, the transparent state is maintained. When the second protection sub-circuit 220 acquires the reset request, the second protection sub-circuit processes and detects the signal and the data transmitted by the second branch circuit 430 through the second limiting sub-circuit 221, the second transmitting sub-circuit 222 and the second detecting sub-circuit 223, respectively.

Specifically, the second limiting sub-circuit 221 obtains the second command control signal, and according to the second command control signal, it can be determined whether any host circuit 500 outputs the new transaction to the designated slave, and when it is determined that any host circuit 500 outputs the new transaction to the designated slave according to the second command control signal, the second command control signal is configured to limit the bus circuit 400 to transmit the new transaction that needs to be output to the designated slave.

The second data control signal passed through is obtained by the second transmission sub-circuit 222, and according to the second data control signal, it can be determined whether the designated slave circuit needs to transmit the residual transaction to the host circuit 500, and when it is determined that the designated slave circuit needs to transmit the residual transaction to the host circuit 500 according to the second data control signal, the bus circuit 400 is enabled to transmit the residual transaction output by the designated slave circuit as soon as possible by configuring the second data control signal.

The second detection sub-circuit 223 obtains the second bus state signal, and determines whether the bus state corresponding to the second branch circuit 430 is idle according to the second bus state signal, and when the bus state corresponding to the second branch circuit 430 is idle, the new transaction corresponding to the designated slave circuit is not existed on the bus circuit 400, and the residual transaction corresponding to the designated slave circuit is not existed. At this time, a response signal may be fed back to the slave reset control sub-circuit 120, so that the slave reset control sub-circuit 120 sends a hard reset instruction to the designated slave circuit, and performs slave hard reset processing on the designated slave circuit.

It is further added that the embodiment of the present application may further include a limiting program, where the limiting program may be implemented by a software or hardware circuit, and the limiting program may be disposed in any module having a data processing capability, such as the slave reset control sub-circuit 120. When the restriction program is set in the slave reset control sub-circuit 120, the slave reset control sub-circuit 120 issues a restriction generation new command request to the host circuit 500 while transmitting a reset request, so as to avoid congestion of the bus circuit 400. Correspondingly, after the slave reset control sub-circuit 120 sends a hard reset instruction to the designated slave circuit, a release instruction may be sent to the host circuit 500, causing the host circuit 500 to resume producing new commands.

In one embodiment, the second limiting sub-circuit 221 includes: a third configuration unit (not shown in the figure) for configuring the second command control signal, and when the second command control signal is at a low level, the second branch 430 stops transmitting the new transaction corresponding to the designated slave circuit; wherein the number of the second command control signals is at least one; the second transmission sub-circuit 222 includes: a fourth configuration unit (not shown in the figure) for configuring the second data control signal, and when the second data control signal is at a high level, the second branch 430 transmits the residual transaction corresponding to the designated slave circuit; wherein the number of second data control signals is at least one; the second detection subcircuit 223 includes: a second detecting unit (not shown in the figure) for determining that the bus state corresponding to the specified slave circuit is idle when the second bus state signal is detected to be at a high level.

The third configuration unit may be configured to control the second command control signal to remain at a low level, and when the second command control signal is at a low level, the bus circuit 400 stops transmitting a new transaction corresponding to the designated slave circuit. Wherein the type and number of second command control signals used by different bus circuits 400 may be different depending on the bus type of the bus circuit 400. The embodiment of the application determines the corresponding second command control signal according to the type of the bus circuit 400. For example, the second command control signal may be a read command flow control signal and a read command valid signal, and further may be selected as a read command flow control signal transmitted to any host circuit 500 and a read command valid signal transmitted to a specified slave circuit.

Fig. 8 shows a timing diagram of a system protection circuit according to a fourth embodiment of the present application.

Referring to fig. 8, fig. 8 is a timing diagram for the second protection sub-circuit when the bus is an AXI bus. In the AXI bus, the second command control signals are selected as the array_m and array_s, so that the array_m=0 sent to any host circuit 500 and the array_s=0 sent to the designated slave circuit are achieved, and the purpose that the bus circuit 400 does not transmit the newly created transaction corresponding to the designated slave circuit is achieved.

The fourth configuration unit may be configured to control the second data control signal to remain high, and when the second data control signal is high, the bus circuit 400 may transmit the residual transaction that needs to be specified to be output from the circuit as soon as possible. Similarly, the type and number of second data control signals used by different bus circuits 400 may be different depending on the bus type of the bus circuit 400. For example, the second data control signal may be a read data flow control signal, further selected as a read data flow control signal for transmission to a designated slave circuit. For example, in the AXI bus, the second data control signal is selected as rready_s, causing rready_s=1 sent to the designated slave circuit, enabling bus circuit 400 to transmit the residual transaction output by the designated host circuit.

Similarly, the second detecting unit may perform level detection on the second bus state signal passing through, and determine that the bus state corresponding to the second branch 430 is idle when the second bus state signal is at a high level. The second bus status signals corresponding to different bus circuits 400 are different, and in the AXI bus, the detection may be performed by the bus_idle signal, when the bus_idle signal is at a high level, the bus status corresponding to the second branch 430 is idle, and when the bus_idle signal is at a low level, the bus status corresponding to the second branch 430 is not idle.

Similarly, in the AXI bus, the rst_req signal corresponding to the slave reset control sub-circuit is used to characterize the reset request, and when the reset request is sent to the second protection sub-circuit, the signal is configured to rst_req=1. The rst_ack signal is used to characterize the reply signal, and when the second protection subcircuit returns a reply signal, the signal is configured rst_ack=1. The mst_rst signal is used for representing a hard reset instruction, the slave reset control sub-circuit sends the hard reset instruction to a designated slave circuit after receiving a valid response, the signal is configured to be mst_rst=0, and the slave reset control sub-circuit stops sending reset requests, and the signal is configured to be rst_req=0. The hard reset is released, the signal is configured to be mst_rst=1, the transaction can be normally transmitted between the host circuit and the slave circuit, and the system works normally.

In one embodiment, the second branches 430 are plural, and the plural second branches 430 are respectively connected to the bus control circuit 420 and the designated slave circuit, and each second branch 430 is provided with a second protection sub-circuit 220; a plurality of host circuits 500 configured as different host index numbers; the bus control circuit 420 is configured to establish a host transmission relationship between the host circuit 500 and the corresponding second branch 430 based on the host index number.

The slave circuit 300 may be connected to the bus control circuit 420 through a plurality of second branches 430, and a second protection sub-module is disposed on each second branch 430. So configured, when the circuit transaction is complex, the rapid transmission of signals and data can be achieved through the plurality of second branches 430. In such an implementation scenario, the plurality of host circuits 500 may be configured as different host index numbers, and the bus control circuit 420 establishes host transmission relationships between different slave circuits 300 and corresponding second branches 430 based on the host index numbers, so as to achieve reasonable distribution and rapid transmission of signals and data on the second branches 430.

In an embodiment, the circuit further includes a second fan-out circuit 710 and a second response circuit 720, where the second fan-out circuit 710 is connected to the slave reset control sub-circuit 120 and the second branch 430, and the second response circuit 720 is connected to the slave reset control sub-circuit 120 and the second branch 430, respectively; a second fanout circuit 710 for transmitting a reset request to all the second protection sub-circuits 220 through the fanout logic; the second response circuit 720 is configured to send an effective response signal to the slave reset control sub-circuit 120 when receiving response signals from all the second protection sub-circuits 220.

In the case where there are multiple second branches 430 and multiple second protection sub-modules, the slave reset control sub-circuit 120 needs to transmit a reset request to each second protection sub-module associated with the designated slave circuit through the second fanout circuit 710. Correspondingly, a second response circuit 720 is required to be arranged in the circuit to receive the response signal sent by each second protection sub-module, and the response signal is forwarded to the slave reset control sub-circuit 120 through response and logic under the condition that all the second protection sub-modules send response signals, so that the slave reset control sub-circuit 120 performs slave hard reset on the designated slave circuit.

Fig. 9 shows a schematic diagram of an implementation module of a chip system according to an embodiment of the present application.

With reference to fig. 1 to 4 and 9, according to a second aspect of the present application, there is provided a chip system including a system protection circuit including: the device comprises a plurality of target chips, a bus circuit 400, a reset control circuit 100 and a reset protection circuit 200, wherein the target chips are a master chip 900 or a slave chip 800, the plurality of target chips comprise at least one master chip 900 and at least one slave chip 800, the master chip 900 is connected with the slave chip 800 through the bus circuit 400, the reset control circuit 100 is respectively connected with the bus circuit 400 and the target chips, and the reset protection circuit 200 is respectively connected with the bus circuit 400 and the reset control circuit 100; the reset control circuit 100 is configured to output a reset request corresponding to a reset instruction from the main chip 900, where the reset instruction is used to perform hard reset on the specified target chip; the reset protection circuit 200 is configured to obtain a reset request, detect the bus circuit 400, and output a response signal when detecting that the current task corresponding to the specified target chip is completed; the reset control circuit 100 is further configured to perform a hard reset on the specified target chip when the response signal is acquired.

In an embodiment, the number of the master chip 900 and/or the slave chips 800 is plural, the bus circuit 400 includes a bus control circuit 420, a first branch 410 and a second branch 430, the first branch 410 is connected between the bus control circuit 420 and the master chip 900, and the second branch 430 is connected between the bus control circuit 420 and the slave chips 800; the bus control circuit 420 is configured to establish a transmission relationship between the master chip 900 and the slave chip 800 based on preset logic; the preset logic is as follows: at least one of circuit identification based control logic and priority based control logic.

In an embodiment, the reset protection circuit 200 includes a first protection sub-circuit 210 and a second protection sub-circuit 220, the first protection sub-circuit 210 is connected to the first branch 410, the second protection sub-circuit 220 is connected to the second branch 430, and the target task includes a new transaction and/or a residual transaction; the first protection sub-circuit 210 is configured to limit, based on a reset request corresponding to the designated main chip 900, the first branch 410 to transmit a new transaction corresponding to the designated main chip 900 and/or transmit a residual transaction corresponding to the designated main chip 900, and perform signal detection on the first branch 410, and output a response signal when the bus circuit 400 is idle; the second protection sub-circuit 220 is configured to limit the second branch circuit 430 to transmit the new transaction corresponding to the specified slave chip 800 and/or transmit the residual transaction corresponding to the specified slave chip 800 based on the reset request corresponding to the specified slave chip 800, and perform signal detection on the second branch circuit 430, and output a response signal when the bus circuit 400 is idle.

In one embodiment, the number of slave chips 800 is plural, the reset control circuit 100 includes a host reset control sub-circuit 110, the first protection sub-circuit 210 includes a first limiting sub-circuit 211, a first transmitting sub-circuit 212, and a first detecting sub-circuit 213, and the first limiting sub-circuit 211, the first transmitting sub-circuit 212, and the first detecting sub-circuit 213 are all connected to the first branch 410; a host reset control sub-circuit 110 for outputting a reset request corresponding to the designated main chip 900 to the first protection sub-circuit 210; a first limiting sub-circuit 211, configured to limit a first command control signal transmitted by the first branch 410, where the first command control signal is used to transmit a new transaction corresponding to the designated main chip 900; a first transmission sub-circuit 212, configured to transmit a first data control signal transmitted by the first branch 410, where the first data control signal is used to transmit a residual transaction corresponding to the designated main chip 900; the first detection sub-circuit 213 is configured to detect a first bus status signal transmitted by the first branch 410, where the first bus status signal is used to indicate whether the bus circuit 400 is idle.

In one embodiment, the first limiting sub-circuit 211 includes: a first configuration unit, configured to configure a first command control signal, and when the first command control signal is at a low level, the first branch 410 stops transmitting a new transaction corresponding to the designated main chip 900; wherein the number of the first command control signals is at least one; the first transmission sub-circuit 212 includes: a second configuration unit, configured to configure the first data control signal, and when the first data control signal is at a high level, the first branch 410 transmits the residual transaction corresponding to the designated main chip 900; wherein the number of the first data control signals is at least one; the first detection subcircuit 213 includes: the first detecting unit is configured to determine that the bus circuit 400 is idle when detecting that the first bus status signal is at a high level.

In an embodiment, the first branches 410 are plural, and the plural first branches 410 are respectively connected to the bus control circuit 420 and the designated main chip 900, and each first branch 410 is provided with a first protection sub-circuit 210; a plurality of slave chips 800 configured as different slave IP addresses; the bus control circuit 420 is configured to establish a slave transmission relationship between the slave chip 800 and the corresponding first branch 410 based on the slave IP address.

In one embodiment, the number of the master chips 900 is plural, the reset control circuit 100 includes a slave reset control sub-circuit 120, the second protection sub-circuit 220 includes a second limiting sub-circuit 221, a second transmitting sub-circuit 222, and a second detecting sub-circuit 223, and the second limiting sub-circuit 221, the second transmitting sub-circuit 222, and the second detecting sub-circuit 223 are all connected to the second branch circuit 430; a slave reset control sub-circuit 120 for outputting a reset request corresponding to the designated slave chip 800 to the second protection sub-circuit 220; a second limiting sub-circuit 221, configured to limit a second command control signal transmitted by the second branch 430, where the second command control signal is used to transmit a new transaction corresponding to the designated slave chip 800; a second transmitting sub-circuit 222 for transmitting a second data control signal transmitted by the second branch 430, the second data control signal being used for transmitting a residual transaction corresponding to the designated slave chip 800; the second detection subcircuit 223 is configured to detect a second bus state signal transmitted by the second branch 430, where the second bus state signal is used to indicate whether the bus circuit 400 is idle.

In one embodiment, the second limiting sub-circuit 221 includes: a third configuration unit, configured to configure the second command control signal, and when the second command control signal is at a low level, the second branch 430 stops transmitting the new transaction corresponding to the designated slave chip 800; wherein the number of the second command control signals is at least one; the second transmission sub-circuit 222 includes: a fourth configuration unit, configured to configure the second data control signal, and when the second data control signal is at a high level, the second branch 430 transmits the residual transaction corresponding to the designated slave chip 800; wherein the number of second data control signals is at least one; the second detection subcircuit 223 includes: the second detecting unit is configured to determine that the bus circuit 400 is idle when detecting that the second bus state signal is at a high level.

In one embodiment, the second branches 430 are plural, and the plural second branches 430 are respectively connected to the bus control circuit 420 and the designated slave chip 800, and each second branch 430 is provided with a second protection sub-circuit 220; a plurality of host chips 900 configured as different host index numbers; the bus control circuit 420 is configured to establish a host transmission relationship between the host chip 900 and the corresponding second branch 430 based on the host index number.

Fig. 10 is a schematic flow chart of an implementation of a reset method according to an embodiment of the present application.

Referring to fig. 1 to 4 and 10, according to a third aspect of the present application, there is provided a reset method, the method being applied to a system protection circuit, the circuit comprising: a plurality of target modules, a bus circuit 400, a reset control circuit 100 and a reset protection circuit 200, wherein the target modules are a host circuit 500 or a slave circuit 300, and the plurality of target modules comprise at least one host circuit 500 and at least one slave circuit 300, the host circuit 500 is connected with the slave circuit 300 through the bus circuit 400, the reset control circuit 100 is respectively connected with the bus circuit 400 and the target modules, and the reset protection circuit 200 is respectively connected with the bus circuit 400 and the reset control circuit 100, the method comprises the following steps: operation 801, the reset control circuit 100 outputs a reset request corresponding to a reset instruction from the host circuit 500, the reset instruction being used for hard resetting the specified target module; operation 802, the reset protection circuit 200 obtains a reset request, processes a target task corresponding to a specified target module, and outputs a response signal when a bus state corresponding to the specified target module is idle; in operation 803, the reset control circuit 100 performs a hard reset on the specified target module when the response signal is acquired.

In an embodiment, the number of the master circuit 500 and/or the slave circuit 300 is plural, the bus circuit 400 includes a bus control circuit 420, a first branch 410 and a second branch 430, the first branch 410 is connected between the bus control circuit 420 and the master circuit 500, and the second branch 430 is connected between the bus control circuit 420 and the slave circuit 300;

the method further comprises the steps of: the bus control circuit 420 establishes a transmission relationship between the master circuit 500 and the slave circuit 300 based on preset logic; the preset logic is as follows: at least one of circuit identification based control logic and priority based control logic.

In an embodiment, the reset protection circuit 200 includes a first protection sub-circuit 210 and a second protection sub-circuit 220, the first protection sub-circuit 210 is connected to the first branch 410, the second protection sub-circuit 220 is connected to the second branch 430, and the target task includes a new transaction and/or a residual transaction;

the reset protection circuit 200 processes the target task corresponding to the specified target module, and outputs a response signal when the bus state corresponding to the specified target module is idle, including:

the first protection sub-circuit 210 limits the first branch circuit 410 to transmit a new transaction corresponding to the specified host circuit and/or transmit a residual transaction corresponding to the specified host circuit based on a reset request corresponding to the specified host circuit, and performs signal detection on the first branch circuit 410, and outputs a response signal when the bus state corresponding to the specified host circuit is idle;

The second protection circuit 220 restricts the second branch circuit 430 from transmitting new transactions corresponding to the specified slave circuit and/or transmitting residual transactions corresponding to the specified slave circuit based on the reset request corresponding to the specified slave circuit, and performs signal detection on the second branch circuit 430, and outputs a response signal when the bus state corresponding to the specified slave circuit is idle.

In one embodiment, the number of slave circuits 300 is plural, the reset control circuit 100 includes a master reset control sub-circuit 110, the first protection sub-circuit 210 includes a first limiting sub-circuit 211, a first transmitting sub-circuit 212, and a first detecting sub-circuit 213, and the first limiting sub-circuit 211, the first transmitting sub-circuit 212, and the first detecting sub-circuit 213 are all connected to the first branch 410;

the reset control circuit 100 outputs a reset request corresponding to a reset instruction, including: the host reset control sub-circuit 110 outputs a reset request corresponding to the designated host circuit to the first protection sub-circuit 210;

the first protection sub-circuit 210 restricts, based on a reset request corresponding to the specified host circuit, the first branch 410 to transmit a new transaction corresponding to the specified host circuit and/or transmit a residual transaction corresponding to the specified host circuit, and performs signal detection on the first branch 410, and outputs a response signal when a bus state corresponding to the specified host circuit is idle, including:

The first limiting sub-circuit 211 limits the first command control signal transmitted by the first branch 410, where the first command control signal is used to characterize whether there is a new transaction corresponding to the designated host circuit;

the first transmitting sub-circuit 212 transmits a first data control signal transmitted by the first branch 410, where the first data control signal is used to characterize whether there is a residual transaction corresponding to the specified host circuit;

the first detection sub-circuit 213 detects a first bus state signal transmitted by the first branch 410, where the first bus state signal is used to indicate whether the bus state corresponding to the specified host circuit is idle.

In an embodiment, the first branches 410 are plural, and the plural first branches 410 are respectively connected to the bus control circuit 420 and the designated host circuit, and each first branch 410 is provided with a first protection sub-circuit 210;

the method further comprises the steps of:

the plurality of slave circuits 300 are configured as different slave IP addresses;

the bus control circuit 420 establishes a slave transmission relationship between the slave circuit 300 and the corresponding first leg 410 based on the slave IP address.

In an embodiment, the fan-out circuit further includes a first fan-out circuit 610 and a first response circuit 620, where the first fan-out circuit 610 is connected to the host reset control sub-circuit 110 and the first branch 410, and the first response circuit 620 is connected to the host reset control sub-circuit 110 and the first branch 410, respectively;

The method further comprises the steps of:

the first fanout circuit 610 transmits a reset request to all the first protection sub-circuits 210 through the fanout logic;

the first reply circuit 620, upon receiving reply signals from all of the first protection subcircuits 210, sends an active reply signal to the host reset control subcircuit 110.

In one embodiment, the number of the host circuits 500 is plural, the reset control circuit 100 includes a slave reset control sub-circuit 120, the second protection sub-circuit 220 includes a second limiting sub-circuit 221, a second transmitting sub-circuit 222, and a second detecting sub-circuit 223, and the second limiting sub-circuit 221, the second transmitting sub-circuit 222, and the second detecting sub-circuit 223 are all connected to the second branch circuit 430;

the reset control circuit 100 outputs a reset request corresponding to a reset instruction, including: the slave reset control sub-circuit 120 outputs a reset request corresponding to the designated slave circuit to the second protection sub-circuit 220;

the second protection circuit 220 restricts the second branch circuit 430 from transmitting new transactions corresponding to the specified slave circuit and/or transmitting residual transactions corresponding to the specified slave circuit based on the reset request corresponding to the specified slave circuit, and performs signal detection on the second branch circuit 430, and outputs a response signal when the bus state corresponding to the specified slave circuit is idle, including:

The second limiting circuit 221 limits the second command control signal transmitted by the second branch 430, where the second command control signal is used to transmit the new transaction corresponding to the specified slave circuit;

the second transmitting sub-circuit 222 transmits a second data control signal transmitted by the second branch 430, the second data control signal being used to transmit a residual transaction corresponding to the specified slave circuit;

the second detection sub-circuit 223 detects a second bus state signal transmitted by the second branch 430, where the second bus state signal is used to characterize whether the bus state corresponding to the specified slave circuit is idle.

In one embodiment, the second branches 430 are plural, and the plural second branches 430 are respectively connected to the bus control circuit 420 and the designated slave circuit, and each second branch 430 is provided with a second protection sub-circuit 220;

the method further comprises the steps of:

the plurality of host circuits 500 are configured as different host index numbers;

the bus control circuit 420 establishes a host transfer relationship between the host circuit 500 and the corresponding second leg 430 based on the host index number.

In an embodiment, the circuit further includes a second fan-out circuit 710 and a second response circuit 720, where the second fan-out circuit 710 is connected to the slave reset control sub-circuit 120 and the second branch 430, and the second response circuit 720 is connected to the slave reset control sub-circuit 120 and the second branch 430, respectively;

The method further comprises the steps of:

the second fanout circuit 710 transmits a reset request to all the second protection sub-circuits 220 through the fanout logic;

the second reply circuit 720, upon receiving reply signals from all of the second protection subcircuits 220, sends an effective reply signal to the slave reset control subcircuit 120.

According to a fourth aspect of the present application, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods of the present application.

According to a fifth aspect of the present application there is provided a non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of the present application.

According to an embodiment of the present application, the present application also provides an electronic device and a readable storage medium.

FIG. 11 shows a schematic block diagram of an example electronic device 900 that may be used to implement an embodiment of the application. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the applications described and/or claimed herein.

As shown in fig. 11, the apparatus 900 includes a computing unit 901 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 902 or a computer program loaded from a storage unit 908 into a Random Access Memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the device 900 can also be stored. The computing unit 901, the ROM 902, and the RAM 903 are connected to each other by a bus 904. An input/output (I/O) interface 905 is also connected to the bus 904.

Various components in device 900 are connected to I/O interface 905, including: an input unit 906 such as a keyboard, a mouse, or the like; an output unit 907 such as various types of displays, speakers, and the like; a storage unit 908 such as a magnetic disk, an optical disk, or the like; and a communication unit 909 such as a network card, modem, wireless communication transceiver, or the like. The communication unit 909 allows the device 900 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunications networks.

The computing unit 901 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 901 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the respective methods and processes described above, for example, a reset method. For example, in some embodiments, the reset method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 908. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 900 via the ROM 902 and/or the communication unit 909. When the computer program is loaded into the RAM 903 and executed by the computing unit 901, one or more steps of the reset method described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the reset method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present application may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present application, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present disclosure may be performed in parallel, sequentially, or in a different order, so long as the desired result of the technical solution of the present disclosure is achieved, and the present disclosure is not limited herein.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A system protection circuit, the circuit comprising: the system comprises a plurality of target modules, a bus circuit, a reset control circuit and a reset protection circuit, wherein the target modules are host circuits or slave circuits, the target modules comprise at least one host circuit and at least one slave circuit, the host circuit is connected with the slave circuits through the bus circuit, the reset control circuit is respectively connected with the bus circuit and the target modules, and the reset protection circuit is respectively connected with the bus circuit and the reset control circuit;

the reset control circuit is used for outputting a reset request corresponding to a reset instruction, wherein the reset instruction is from the host circuit and is used for carrying out hard reset on a specified target module;

the reset protection circuit is used for acquiring the reset request, processing the target task corresponding to the specified target module, and outputting a response signal when the bus state corresponding to the specified target module is idle;

and the reset control circuit is also used for carrying out hard reset on the appointed target module when the response signal is acquired.

2. The circuit of claim 1, wherein the number of host circuits and/or slave circuits is a plurality, the bus circuit comprising a bus control circuit, a first leg, and a second leg, the first leg being connected between the bus control circuit and the host circuit, the second leg being connected between the bus control circuit and the slave circuit;

the bus control circuit is used for establishing a transmission relation between the host circuit and the slave circuit based on preset logic;

the preset logic is as follows: at least one of circuit identification based control logic and priority based control logic.

3. The circuit of claim 2, wherein the reset protection circuit comprises a first protection subcircuit and a second protection subcircuit, the first protection subcircuit being connected to the first leg, the second protection subcircuit being connected to the second leg, the target task comprising a new transaction and/or a residual transaction;

the first protection sub-circuit is used for limiting the first branch to transmit new transactions corresponding to the specified host circuit and/or transmit residual transactions corresponding to the specified host circuit based on a reset request of the corresponding specified host circuit, detecting signals of the first branch, and outputting response signals when the bus state corresponding to the specified host circuit is idle;

And the second protection sub-circuit is used for limiting the second branch circuit to transmit new transactions corresponding to the appointed slave circuit and/or transmit residual transactions corresponding to the appointed slave circuit based on a reset request corresponding to the appointed slave circuit, detecting signals of the second branch circuit, and outputting response signals when the bus state corresponding to the appointed slave circuit is idle.

4. The circuit of claim 3, wherein the number of slave circuits is a plurality, the reset control circuit comprises a master reset control sub-circuit, the first protection sub-circuit comprises a first limit sub-circuit, a first transmit sub-circuit, and a first detect sub-circuit, and the first limit sub-circuit, the first transmit sub-circuit, and the first detect sub-circuit are all connected to the first leg;

the host reset control sub-circuit is used for outputting a reset request of a corresponding appointed host circuit to the first protection sub-circuit;

the first limiting sub-circuit is used for limiting a first command control signal transmitted by the first branch circuit, and the first command control signal is used for representing whether a new transaction corresponding to the designated host circuit exists or not;

The first transmission sub-circuit is used for transmitting a first data control signal transmitted by the first branch circuit, and the first data control signal is used for representing whether residual transactions corresponding to the designated host circuit exist or not;

the first detection sub-circuit is configured to detect a first bus state signal transmitted by the first branch, where the first bus state signal is used to characterize whether a bus state corresponding to the specified host circuit is idle.

5. The circuit of claim 4, wherein the circuit further comprises a logic circuit,

the first limiting sub-circuit includes: the first configuration unit is used for configuring a first command control signal, and when the first command control signal is at a low level, the first branch stops transmitting new transactions corresponding to the appointed host circuit; wherein the number of the first command control signals is at least one;

the first transmission sub-circuit includes: the second configuration unit is used for configuring a first data control signal, and when the first data control signal is at a high level, the first branch transmits residual transactions corresponding to the appointed host circuit; wherein the number of the first data control signals is at least one;

The first detection subcircuit includes: and the first detection unit is used for determining that the bus state corresponding to the specified host circuit is idle when the first bus state signal is detected to be at a high level.

6. The circuit of claim 4, wherein the first branch is plural, the plural first branches are respectively connected with the bus control circuit and the designated host circuit, and the first protection subcircuit is disposed on each first branch;

a plurality of slave circuits configured as different slave IP addresses;

the bus control circuit is used for establishing a slave machine transmission relation between a slave machine and a corresponding first branch circuit based on the slave machine IP address.

7. The circuit of claim 6, further comprising a first fan-out circuit and a first response circuit, the first fan-out circuit being connected to the host reset control sub-circuit and the first leg, respectively, the first response circuit being connected to the host reset control sub-circuit and the first leg, respectively;

the first fan-out circuit is used for transmitting the reset request to all first protection sub-circuits through fan-out logic;

The first response circuit is used for sending an effective response signal to the host reset control sub-circuit when receiving response signals of all the first protection sub-circuits.

8. A circuit according to claim 3, wherein the number of host circuits is plural, the reset control circuit comprises a slave reset control sub-circuit, the second protection sub-circuit comprises a second limit sub-circuit, a second transmission sub-circuit and a second detection sub-circuit, and the second limit sub-circuit, the second transmission sub-circuit and the second detection sub-circuit are all connected with the second branch circuit;

the slave reset control sub-circuit is used for outputting a reset request corresponding to the appointed slave circuit to the second protection sub-circuit;

the second limiting sub-circuit is used for limiting a second command control signal transmitted by the second branch circuit, and the second command control signal is used for transmitting a new transaction corresponding to the appointed slave circuit;

the second transmission sub-circuit is used for transmitting a second data control signal transmitted by the second branch circuit, and the second data control signal is used for transmitting a residual transaction corresponding to the appointed slave circuit;

The second detection sub-circuit is configured to detect a second bus state signal transmitted by the second branch, where the second bus state signal is used to characterize whether the bus state corresponding to the specified slave circuit is idle.

9. The circuit of claim 8, wherein the circuit further comprises a logic circuit,

the second limiting sub-circuit includes: a third configuration unit, configured to configure a second command control signal, where when the second command control signal is at a low level, the second branch stops transmitting a new transaction corresponding to the specified slave circuit; wherein the number of the second command control signals is at least one;

the second transmission sub-circuit includes: a fourth configuration unit, configured to configure a second data control signal, where when the second data control signal is at a high level, the second branch transmits a residual transaction corresponding to the specified slave circuit; wherein the number of the second data control signals is at least one;

the second detection subcircuit includes: and the second detection unit is used for determining that the bus state corresponding to the specified host circuit is idle when the second bus state signal is detected to be at a high level.

10. The circuit of claim 9, wherein a plurality of said second branches are provided, each of said second branches having said second protection subcircuit provided thereon, said plurality of said second branches being respectively connected to said bus control circuit and said designated slave circuit;

a plurality of host circuits configured to different host index numbers;

the bus control circuit is used for establishing a host transmission relation between the host circuit and the corresponding second branch circuit based on the host index number.

11. The circuit of claim 10, further comprising a second fan-out circuit and a second reply circuit, the second fan-out circuit being connected to the slave reset control sub-circuit and the second leg, respectively, the second reply circuit being connected to the slave reset control sub-circuit and the second leg, respectively;

the second fan-out circuit is used for transmitting the reset request to all second protection sub-circuits through fan-out logic;

and the second response circuit is used for sending an effective response signal to the slave reset control sub-circuit when receiving response signals of all the second protection sub-circuits.

12. A chip system comprising a system protection circuit, the circuit comprising: the device comprises a plurality of target chips, a bus circuit, a reset control circuit and a reset protection circuit, wherein the target chips are master chips or slave chips, the target chips comprise at least one master chip and at least one slave chip, the master chips are connected with the slave chips through the bus circuit, the reset control circuit is respectively connected with the bus circuit and the target chips, and the reset protection circuit is respectively connected with the bus circuit and the reset control circuit;

The reset control circuit is used for outputting a reset request corresponding to a reset instruction, wherein the reset instruction is from the main chip, and the reset instruction is used for carrying out hard reset on a specified target chip;

the reset protection circuit is used for acquiring the reset request, detecting the bus circuit, and outputting a response signal when the current task corresponding to the appointed target chip is detected to be completed;

the reset control circuit is further used for performing hard reset on the specified target chip when the response signal is acquired.

13. A reset method, the method being applied to a system protection circuit, the circuit comprising: the device comprises a plurality of target modules, a bus circuit, a reset control circuit and a reset protection circuit, wherein the target modules are host circuits or slave circuits, the target modules comprise at least one host circuit and at least one slave circuit, the host circuit is connected with the slave circuits through the bus circuit, the reset control circuit is respectively connected with the bus circuit and the target modules, and the reset protection circuit is respectively connected with the bus circuit and the reset control circuit, and the method comprises the following steps:

The reset control circuit outputs a reset request corresponding to a reset instruction, wherein the reset instruction is from the host circuit and is used for carrying out hard reset on a specified target module;

the reset protection circuit acquires the reset request, processes the target task corresponding to the designated target module, and outputs a response signal when the bus state corresponding to the designated target module is idle;

and the reset control circuit performs hard reset on the appointed target module when acquiring the response signal.

14. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the reset method of claim 13.

15. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of claim 13.