CN102280489A - Thin film transistor with offset structure - Google Patents

Thin film transistor with offset structure Download PDF

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Publication number
CN102280489A
CN102280489A CN2011101340079A CN201110134007A CN102280489A CN 102280489 A CN102280489 A CN 102280489A CN 2011101340079 A CN2011101340079 A CN 2011101340079A CN 201110134007 A CN201110134007 A CN 201110134007A CN 102280489 A CN102280489 A CN 102280489A
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source
drain electrode
drain
electrode
active area
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CN102280489B (en
Inventor
金起弘
金正晥
张龙在
金正贤
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TCL Huaxing Photoelectric Technology Co Ltd
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Samsung Mobile Display Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A thin film transistor (TFT) having an offset structure is disclosed. The TFT maintains a sufficiently low 'off' current and a sufficiently high 'on' current. The TFT includes an active region. The active region includes a gate electrode; an active layer that overlaps with the gate electrode; a gate insulating layer between the gate electrode and the active layer; and a source/drain electrode layer including source/drain electrodes that are electrically connected to the active region. Some of the source/drain electrodes overlap partially with the gate electrode. Other of the source/drain electrodes are offset from the gate electrode. The source/drain electrodes and the gate electrode are in a symmetrical arrangement.

Description

Thin-film transistor with off-set construction
CROSS-REFERENCE TO RELATED PATENT
The application requires priority and the rights and interests of the korean patent application No.10-2010-0053666 that submitted in Korea S Department of Intellectual Property on June 8th, 2010, and the full content of this application is incorporated herein by reference.
Technical field
Each side relates to thin-film transistor according to an embodiment of the invention, more particularly, relates to the high-voltage thin-film transistor with off-set construction.
Background technology
Thin-film transistor (TFT) is the field-effect transistor (FET) that forms the particular type of semiconductive thin film on the insulation supporting substrate.Similar with FET, TFT has three terminals, i.e. grid, drain electrode and source electrode, and carry out and switch as major function.Put on the voltage of grid by adjusting, TFT carries out switching, makes the electric current that flows between source electrode and drain electrode can be in " leading to " or " breaking " state.
Tradition high voltage TFT is applied in a high-tension class TFT.Tradition high voltage TFT can adopt off-set construction, thereby can have bigger resistance to high voltage.The tradition off-set construction has deviate region, and this deviate region is the high resistance area between source region and the drain region.In general, if apply high voltage between source region and drain region, then this high voltage also is passed to the high resistance deviate region, thereby prevents to form on channel layer high electric field.Therefore TFT can be maintained enough low-level " breaking " electric current I Off
Yet, because therefore the deviatoric stress that is caused when having a mind to adopt the high resistance deviate region to reduce applying high voltage in traditional high voltage TFT may cause " leading to " electric current I OnAmount reduce.
Summary of the invention
In order to solve or alleviate " leading to " electric current I of the traditional high-voltage thin-film transistor (TFT) with off-set construction OnThe seriousness of the problem that reduces of amount, one or more embodiment of the present invention provide a kind of thin-film transistor, in this thin-film transistor, low " breaking " electric current and high " leading to " electric current I OnCan be maintained at enough low level and sufficiently high level respectively.
In exemplary embodiment of the present invention, a kind of thin-film transistor (TFT) is disclosed.Described TFT includes the source region.Described active area is divided into first active area and second active area.Described active area comprises gate electrode, active layer, gate insulation layer and source/drain electrode layer.Described active layer comprises first active layer and second active layer.Described first active layer is corresponding with described first active area.Described second active layer is corresponding with described second active area.Described first active layer and described second active layer and described gate electrode.Described gate insulation layer is between described gate electrode and described active layer.Described source/drain electrode layer comprises first source/drain electrode, second source/drain electrode, the 3rd source/drain electrode and the 4th source/drain electrode.Described first and second sources/drain electrode is electrically connected to described first active layer.Described third and fourth source/drain electrode is electrically connected to described second active layer.Two source/drain electrodes and the described gate electrode selected from described first to fourth source/drain electrode are overlapped.Two source/drain electrodes of in described first to fourth source/drain electrode other are offset from described gate electrode.Described first to fourth source/drain electrode and described gate electrode are arranged symmetrically.
Described first and the 3rd source/drain electrode can be electrically connected to each other, make identical voltage be applied to described first and the 3rd source/drain electrode.Described second and the 4th source/drain electrode can be electrically connected to each other, make identical voltage be applied to described second and the 4th source/drain electrode.
Described first source/drain electrode and described the 3rd source/drain electrode can be connected to each other.Described second source/drain electrode and described the 4th source/drain electrode can be connected to each other.
Described TFT can comprise two TFT.Respective sources/the drain electrode of described two TFT and gate electrode can be connected in the mode of symmetric arrangement to be used as single TFT.
Described active layer can comprise the material of selecting from the group that comprises amorphous silicon, polysilicon, microcrystal silicon, oxide semiconductor, organic semiconductor and combination thereof.
Described active area may further include the ohmic contact layer between described active layer and described source/drain electrode layer.
Described first active layer can comprise first source/drain region, second source/drain region and first channel region.Described first source/drain region is corresponding with described first source/drain electrode.Described second source/drain region is corresponding with described second source/drain electrode.Described first channel region is between described first source/drain region and described second source/drain region.Described second active layer can comprise the 3rd source/drain region, the 4th source/drain region and second channel region.Described the 3rd source/drain region is corresponding with described the 3rd source/drain electrode.Described the 4th source/drain region is corresponding with described the 4th source/drain electrode.Described second channel region is between described the 3rd source/drain region and described the 4th source/drain region.
Described first channel region can comprise first deviate region.Described first deviate region not with described gate electrode, described first source/drain electrode and described second source/drain electrode in any is overlapping.Described second channel region can comprise second deviate region.Described second deviate region not with described gate electrode, described the 3rd source/drain electrode and described the 4th source/drain electrode in any is overlapping.
Source/drain electrode layer in described second active area can be symmetrical with the source/drain electrode layer rotation in described first active area.
In described first source/drain electrode and the described second source/drain electrode one can with described gate electrode.In described first source/drain electrode and the described second source/drain electrode another can be offset from described gate electrode.
Described first active area and described second active area can be insulated from each other.
Described gate electrode can comprise the first grid electrode and second gate electrode.Described first grid electrode and described second gate electrode are parallel to each other.
Described first and the 3rd source/drain electrode can be electrically connected to each other, make identical voltage be applied to described first and the 3rd source/drain electrode.Described second and the 4th source/drain electrode can be electrically connected to each other, make identical voltage be applied to described second and the 4th source/drain electrode.
Source/drain electrode layer in described second active area can be symmetrical with the source/drain electrode layer rotation in described first active area.
Can overlap with described first grid electrode for one in described first to fourth source/drain electrode.In described first to fourth source/drain electrode another can be overlapped with described second gate electrode.
Described first grid electrode with the overlapping width of described second active layer can be than described first grid electrode little with the overlapping width of described first active area.
Described active area may further include offset electrodes.Region overlapping between described offset electrodes and described first grid electrode and described second gate electrode.Described offset electrodes and the insulation of described active layer.
Described offset electrodes can comprise first offset electrodes and second offset electrodes.Region overlapping between described first offset electrodes and the described first and second sources/drain electrode.Described first offset electrodes and the insulation of described first active layer.Region overlapping between described second offset electrodes and the described third and fourth source/drain electrode.Described second offset electrodes and the insulation of described second active layer.
Described first and the 3rd source/drain electrode can be electrically connected to each other, make identical voltage be applied to described first and the 3rd source/drain electrode.Described second and the 4th source/drain electrode can be electrically connected to each other, make identical voltage be applied to described second and the 4th source/drain electrode.
Described offset electrodes can be electrically connected to described first grid electrode and described second gate electrode.
Described first active area and described second active area can be insulated from each other.
In another exemplary embodiment according to the present invention, a kind of thin-film transistor (TFT) is disclosed.Described TFT includes the source region.Described active area is divided into first active area, second active area and the 3rd active area.Described active area comprises gate electrode, active layer, gate insulation layer and source/drain electrode layer.Described active layer comprises first active layer, second active layer and the 3rd active layer.Described first active layer is corresponding with described first active area.Described second active layer is corresponding with described second active area.Described the 3rd active layer is corresponding with described the 3rd active area.Described first active layer, described second active layer and described the 3rd active layer and described gate electrode.Described gate insulation layer is between described gate electrode and described active layer.Described source/drain electrode layer comprises first source/drain electrode, second source/drain electrode, the 3rd source/drain electrode, the 4th source/drain electrode, the 5th source/drain electrode and the 6th source/drain electrode.Described first source/drain electrode and described second source/drain electrode are electrically connected to described first active layer.Described the 3rd source/drain electrode and described the 4th source/drain electrode are electrically connected to described second active layer.Described the 5th source/drain electrode and described the 6th source/drain electrode are electrically connected to described the 3rd active layer.Two source/drain electrodes and the described gate electrode selected from described first to fourth source/drain electrode are overlapped.Two source/drain electrodes of in described first to fourth source/drain electrode other are offset from described gate electrode.Described first to the 6th source/drain electrode and described gate electrode be arranged symmetrically.
Described first, the 3rd and the 5th source/drain electrode can be electrically connected to each other, make identical voltage be applied to described first, the 3rd and the 5th source/drain electrode.Described second, the 4th and the 6th source/drain electrode can be electrically connected to each other, make identical voltage be applied to described second, the 4th and the 6th source/drain electrode.
Source/drain electrode layer in described the 3rd active area can with the source/drain electrode layer symmetry in described first active area.
Described first source/drain electrode and described second source/drain electrode can be overlapped with described gate electrode.Described the 3rd source/drain electrode and described the 4th source/drain electrode can be offset from described gate electrode.
Described first active layer can comprise first source/drain region, second source/drain region and first channel region.Described first source/drain region is corresponding with described first source/drain electrode.Described second source/drain region is corresponding with described second source/drain electrode.Described first channel region is between described first source/drain region and described second source/drain region.Described second active layer can comprise the 3rd source/drain region, the 4th source/drain region and second channel region.Described the 3rd source/drain region is corresponding with described the 3rd source/drain electrode.Described the 4th source/drain region is corresponding with described the 4th source/drain electrode.Described second channel region is between described the 3rd source/drain region and described the 4th source/drain region.Described the 3rd active layer can comprise the 5th source/drain region, the 6th source/drain region and triple channel district.Described the 5th source/drain region is corresponding with described the 5th source/drain electrode.Described the 6th source/drain region is corresponding with described the 6th source/drain electrode.Described triple channel district is positioned between described the 5th source/drain region and described the 6th source/drain region.
Described second channel region can comprise deviate region.Described deviate region not with described gate electrode, described the 3rd source/drain electrode and described the 4th source/drain electrode in any is overlapping.
Described source/drain electrode layer and the described source/drain electrode layer in described the 3rd active area in described source/drain electrode layer in described first active area, described second active area can be along the symmetry axis symmetries.
Described gate electrode with the overlapping width of described second active layer can be than described gate electrode little with the overlapping width of the described first and the 3rd active area.
Described first to the 3rd active area can be insulated from each other.
In in accordance with a further exemplary embodiment of the present invention, a kind of thin-film transistor (TFT) is disclosed.Described TFT includes the source region.Described active area is divided into first active area, second active area, the 3rd active area and having ideals, morality, culture, and discipline source region.Described active area comprises gate electrode, active layer, gate insulation layer and source/drain electrode layer.Described active layer comprises first active layer, second active layer, the 3rd active layer and the 4th active layer.Described first active layer is corresponding with described first active area.Described second active layer is corresponding with described second active area.Described the 3rd active layer is corresponding with described the 3rd active area.Described the 4th active layer is corresponding with described having ideals, morality, culture, and discipline source region.Described first active layer, described second active layer, described the 3rd active layer and described the 4th active layer and described gate electrode.Described gate insulation layer is between described gate electrode and described active layer.Described source/drain electrode layer comprises first source/drain electrode, second source/drain electrode, the 3rd source/drain electrode, the 4th source/drain electrode, the 5th source/drain electrode, the 6th source/drain electrode, the 7th source/drain electrode and the 8th source/drain electrode.Described first source/drain electrode and described second source/drain electrode are electrically connected to described first active layer.Described the 3rd source/drain electrode and described the 4th source/drain electrode are electrically connected to described second active layer.Described the 5th source/drain electrode and described the 6th source/drain electrode are electrically connected to described the 3rd active layer.Described the 7th source/drain electrode and described the 8th source/drain electrode are electrically connected to described the 4th active layer.Overlap from the described the 3rd two source/drain electrodes and the described gate electrode of selecting to the 6th source/drain electrode.The described the 3rd other two source/drain electrodes to the 6th source/drain electrode are offset from described gate electrode.Described first to the 8th source/drain electrode and described gate electrode be arranged symmetrically.
Described first, the 3rd, the 5th and the 7th source/drain electrode can be electrically connected to each other, make identical voltage be applied to described first, the 3rd, the 5th and the 7th source/drain electrode.Described second, the 4th, the 6th and the 8th source/drain electrode can be electrically connected to each other, make identical voltage be applied to described second, the 4th, the 6th and the 8th source/drain electrode.
Described first active layer can comprise first source/drain region, second source/drain region and first channel region.Described first source/drain region is corresponding with described first source/drain electrode.Described second source/drain region is corresponding with described second source/drain electrode.Described first channel region is between described first source/drain region and described second source/drain region.Described second active layer can comprise the 3rd source/drain region, the 4th source/drain region and second channel region.Described the 3rd source/drain region is corresponding with described the 3rd source/drain electrode.Described the 4th source/drain region is corresponding with described the 4th source/drain electrode.Described second channel region is between described the 3rd source/drain region and described the 4th source/drain region.Described the 3rd active layer can comprise the 5th source/drain region, the 6th source/drain region and triple channel district.Described the 5th source/drain region is corresponding with described the 5th source/drain electrode.Described the 6th source/drain region is corresponding with described the 6th source/drain electrode.Described triple channel district is positioned between described the 5th source/drain region and described the 6th source/drain region.Described the 4th active layer can comprise the 7th source/drain region, the 8th source/drain region and the 4th channel region.Described the 7th source/drain region is corresponding with described the 7th source/drain electrode.Described the 8th source/drain region is corresponding with described the 8th source/drain electrode.Described the 4th channel region is between described the 7th source/drain region and described the 8th source/drain region.
Described second channel region can comprise first deviate region.Described first deviate region not with described gate electrode, described the 3rd source/drain electrode and described the 4th source/drain electrode in any is overlapping.Described triple channel district can comprise second deviate region.Described second deviate region not with described gate electrode, described the 5th source/drain electrode and described the 6th source/drain electrode in any is overlapping.
Source/drain electrode layer in described the 3rd active area can be symmetrical with the source/drain electrode layer rotation in described second active area.Source/drain electrode layer in the described having ideals, morality, culture, and discipline source region can with the source/drain electrode layer symmetry in described first active area.
Described first source/drain electrode and described second source/drain electrode can be overlapped with described gate electrode.
In described the 3rd source/drain electrode and described the 4th source/drain electrode one can with described gate electrode.In described the 3rd source/drain electrode and described the 4th source/drain electrode another can be offset from described gate electrode.
Described gate electrode with the overlapping width of the described second and the 3rd active area can than described gate electrode with described first and the overlapping width in having ideals, morality, culture, and discipline source region little.
Described first to fourth active area can be insulated from each other.
According to an exemplary embodiment more of the present invention, a kind of thin-film transistor (TFT) is disclosed.Described TFT includes the source region.Described active area comprises gate electrode, active layer, gate insulation layer and source/drain electrode layer.Described gate electrode comprises the first grid electrode and second gate electrode.Described first grid electrode and described second gate electrode are parallel to each other.Described active layer and described first grid electrode and described second gate electrode.Described gate insulation layer is between described gate electrode and described active layer.Described source/drain electrode layer comprises first source/drain electrode and second source/drain electrode.Described first source/drain electrode and described second source/drain electrode are electrically connected to described active layer.Described first source/drain electrode and described first grid electrode are overlapped.Described second source/drain electrode and described second gate electrode are overlapped.Described first and second sources/drain electrode and described gate electrode are arranged symmetrically.
Described active area may further include offset electrodes.Region overlapping between described offset electrodes and described first grid electrode and described second gate electrode.Described offset electrodes and the insulation of described active layer.
Described offset electrodes can be electrically connected to described first grid electrode and described second gate electrode.
Described active layer can comprise first source/drain region, second source/drain region and channel region.Described first source/drain region is corresponding with described first source/drain electrode.Described second source/drain region is corresponding with described second source/drain electrode.Described channel region is between described first source/drain region and described second source/drain region.
Described channel region can comprise deviate region.Described deviate region not with described first grid electrode, described second gate electrode, described first source/drain electrode and described second source/drain electrode in any is overlapping.
Description of drawings
Describe exemplary embodiment of the present invention in detail by the reference accompanying drawing, above and other feature of the present invention and aspect will become more obvious, in the accompanying drawing:
Figure 1A is the layout that the active area of the thin-film transistor (TFT) that has off-set construction according to an embodiment of the invention is shown;
Figure 1B is the sectional view along the line I-I intercepting of Figure 1A;
Fig. 1 C is the sectional view along the line II-II intercepting of Figure 1A;
Fig. 2 A is the layout that the active area of the TFT that has off-set construction according to another embodiment of the present invention is shown;
Fig. 2 B is the sectional view along the line I-I intercepting of Fig. 2 A;
Fig. 2 C is the sectional view along the line II-II intercepting of Fig. 2 A;
Fig. 3 A is the layout that the active area of the TFT that has off-set construction according to another embodiment of the present invention is shown;
Fig. 3 B is the sectional view along the line I-I intercepting of Fig. 3 A;
Fig. 3 C is the sectional view along the line II-II intercepting of Fig. 3 A;
Fig. 3 D is the sectional view along the line III-III intercepting of Fig. 3 A;
Fig. 4 A is the layout that the active area of the TFT that has off-set construction according to another embodiment of the present invention is shown;
Fig. 4 B is the sectional view along the line I-I intercepting of Fig. 4 A;
Fig. 4 C is the sectional view along the line II-II intercepting of Fig. 4 A;
Fig. 5 A is the layout that the active area of the TFT that has off-set construction according to another embodiment of the present invention is shown;
Fig. 5 B is the sectional view along the line I-I intercepting of Fig. 5 A;
Fig. 5 C is the sectional view along the line II-II intercepting of Fig. 5 A;
Fig. 6 A is the layout that the active area of the TFT that has off-set construction according to another embodiment of the present invention is shown;
Fig. 6 B is the sectional view along the line I-I intercepting of Fig. 6 A;
Fig. 7 A is the layout that the active area of the TFT that has off-set construction according to another embodiment of the present invention is shown;
Fig. 7 B is the sectional view along the line I-I intercepting of Fig. 7 A;
Fig. 8 is the layout that the active area of the TFT that has off-set construction according to another embodiment of the present invention is shown;
Fig. 9 is the layout that the active area of the TFT that has off-set construction according to another embodiment of the present invention is shown; And
Figure 10 illustrates according to the channel current of the TFT of the embodiment of the invention curve chart to the simulation result that compares of the characteristic of grid voltage and comparative example.
Embodiment
Hereinafter, describe exemplary embodiment of the present invention with reference to the accompanying drawings in detail.Yet the present invention can be with many different form specific implementations, and should not be construed as limited to the embodiment that proposes here.Exactly, it is in order to make the disclosure more thorough that these embodiment are provided, and more completely passes on feature of the present invention and aspect to those of ordinary skills.In the accompanying drawing, for the sake of clarity, the thickness in layer and zone may be exaggerated.In addition, in the accompanying drawings, identical Reference numeral is represented components identical all the time.
In the disclosure, source electrode and drain electrode are not distinguished each other, and be described as source/drain electrode simply.This is because (for example, in display unit) under many circumstances, and any one in source/drain electrode all can be served as source electrode or drain electrode according to the voltage that puts on respective films transistor (TFT).
In the disclosure, the channel region that term " deviate region " expression is separated from each other source/drain electrode and gate electrode on (for example, with the parallel direction of following laminar substrate) in the horizontal direction.For example, deviate region can be the channel region between one of gate electrode and source/drain electrode on the horizontal direction.Therefore, the resistance value of deviate region does not directly reduce by grid voltage, but is maintained at the level place than the higher level of removing the outer channel region of deviate region (for example, overlap with gate electrode but the channel region that do not overlap with source/drain electrode).
In addition, term " overlay region " expression source/drain electrode and gate electrode overlap each other (for example, with the vertical direction of following laminar substrate on overlap) source/drain region.At last, when comprising channel region (for example, gate electrode overlaps, but source/drain electrode does not overlap) again, source/drain electrode will be called as for " overlapping " with gate electrode when corresponding active layer had both comprised overlay region (for example, gate electrode and source/drain electrode coincidence).
Figure 1A is the layout that illustrates according to the active area 100 of the TFT with off-set construction of the embodiment of the invention.Figure 1B is the sectional view along the line I-I intercepting of Figure 1A.Fig. 1 C is the sectional view along the line II-II intercepting of Figure 1A.
Referring to Figure 1A to Fig. 1 C, the active area 100 of TFT has the structure of vertical stacking, and in this structure, gate electrode 121 is formed on the substrate 111, and gate insulation layer 123 is formed on gate electrode 121 and the substrate 111.Active layer 125 is formed on the gate insulation layer 123, and first source/drain electrode 133a and second source/drain electrode 133b are formed on the active layer 125. Ohmic contact layer 131a and 131b are respectively formed between active layer 125 and first source/drain electrode 133a and the second source/drain electrode 133b.
Substrate 111 can be formed by for example glass, quartz, plastics, silicon, pottery or metal.Gate electrode 121 can but be not limited to form by the electric conducting material of from the group that comprises Au, Ag, Cu, Ni, Pt, Pd, Al, Mo, W, Ti and alloy thereof, selecting.Gate insulation layer 123 can be formed by the insulating barrier such as silicon oxide layer or silicon nitride layer.Active layer 125 can be combined to form by amorphous silicon for example, polysilicon, microcrystal silicon, oxide semiconductor, organic semiconductor or its.First source/drain electrode the 133a and second source/drain electrode 133b also can but be not limited to form by the electric conducting material of from the group that comprises Au, Ag, Cu, Ni, Pt, Pd, Al, Mo, W, Ti and alloy thereof, selecting.Ohmic contact between among the first source/drain electrode 133a and second source/drain electrode 133b each and the active layer 125 utilizes ohmic contact layer 131a and 131b to form. Ohmic contact layer 131a and 131b can be high-concentration dopant amorphous silicon layers for example.
Shown in Figure 1A, active area 100 is divided into the first active area 100A and the second active area 100B, the center that the first active area 100A and the second active area 100B are wound with source region 100 rotates symmetry (for example, active area 100 can be obtained identical layout around its center rotation half cycle (180 °)) each other.In the first active area 100A, first source/drain electrode 133a and gate electrode 121 are overlapped, and second source/drain electrode 133b and gate electrode 121 in the horizontal direction (for example, parallel direction) with substrate 111 go up distance of separation d 1, shown in Figure 1B.
In the first active area 100A, active layer 125 comprises at first source below first source/drain electrode 133a/drain region 125a, at second source below second source/drain electrode 133b/drain region 125b and the first channel region 125ch_1 between first source/drain region and second source/drain region.The first channel region 125ch_1 comprise deviate region between gate electrode 121 and second source/drain electrode 133b (with the first channel region 125ch_1 among Figure 1B by distance d 1That part of correspondence that marks off, also and among Figure 1A between gate electrode 121 and the second source/drain electrode 133b by distance d 1The zone that marks off is corresponding).
Shown in Fig. 1 C, in the second active area 100B, the 3rd source/drain electrode 133c and gate electrode 121 distance of separation d 1, and the 4th source/drain electrode 133d and gate electrode 121 are overlapped.In the second active area 100B, active layer 125 comprises the 3rd source/drain region 125c that is positioned at the 3rd source/drain electrode 133c below, the 4th source/drain region 125d that is positioned at the 4th source/drain electrode 133d below, and the second channel region 125ch_2 between the 3rd source/drain region 125c and the 4th source/drain region 125d.The second channel region 125ch_2 comprise deviate region between the 3rd source/drain electrode 133c and gate electrode 121 (with the second channel region 125ch_2 among Fig. 1 C by distance d 1That part of correspondence that marks off, also and among Figure 1A between the 3rd source/drain electrode 133c and the gate electrode 121 by distance d 1The zone that marks off is corresponding).
Layout and three source/drain electrode 133c and four source/drain electrode 133d the layout rotation symmetry among second active area 100Bs of the first source/drain electrode 133a and second source/drain electrode 133b in the first active area 100A.When considering gate electrode 121, also present identical rotation symmetry, gate electrode 121 occupies similar size in the deviate region of the first active area 100A and the second active area 100B and overlay region, as following further described. Ohmic contact layer 131c and 131d are respectively formed between active layer 125 and the 3rd source/drain electrode 133c and the 4th source/drain electrode 133d.
First source among the first active area 100A/drain electrode 133a is electrically connected to the 3rd source/drain electrode 133c among the second active area 100B.Therefore, identical voltage is applied to first source/drain electrode 133a and the 3rd source/drain electrode 133c from identical source.Similarly, the second source/drain electrode 133b among the first active area 100A is electrically connected to the 4th source/drain electrode 133d among the second active area 100B.Therefore, identical voltage is applied to second source/drain electrode 133b and the 4th source/drain electrode 133d from identical source.
In the first active area 100A, if high voltage is applied to second source/drain electrode 133b, then electric current from first source/drain region 125a flows to the first channel region 125ch_1, flows to second source/drain region 125b then.In this case, the deviate region of the first channel region 125ch_1 prevents that high electric field is applied to the first channel region 125ch_1.Correspondingly, can prevent the performance degradation of TFT, thereby improve its current characteristics that " breaks ".In addition, first source/drain region 125a and gate electrode 121 are overlapping, and therefore improving it " leads to " current characteristics.
Change (for example, high voltage is applied to the first source/drain electrode 133a among the first active area 100A) if apply high-tension direction, then electric current from second source/drain region 125b flows to the first channel region 125ch_1, flows to first source/drain region 125a then.In this case, because deviate region and second source/drain region 125b and not adjacent with first source/drain region 125a, so deviate region different when being applied to second source/drain electrode 133b with respect to the relative position and the high voltage that have applied high-tension source/drain region 125a.Also different when therefore, the amount of the intensity of the electric field that forms in the first channel region 125ch_1 and " leading to " electric current and " breaking " electric current and high voltage are applied to second source/drain electrode 133b.
That is to say that if only consider the first active area 100A, then the deviate region among the first channel region 125ch_1 has applied the relative position difference of high-tension source/drain electrode with respect to those.In other words, when high voltage is applied to first source/drain electrode 133a, different when the relative position of the deviate region among the first channel region 125ch_1 and identical voltage are applied to second source/drain electrode 133b.Different when intensity and the identical voltage that puts on the electric field of the first channel region 125ch_1 when as a result, high voltage is applied to first source/drain electrode 133a is applied to second source/drain electrode 133b.Therefore, the flow through amount of electric current of the first channel region 125ch_1 is different when identical voltage is applied to first source/drain electrode 133a and second source/drain electrode 133b respectively.That is to say that the amount of electric current changes according to the direction that applies identical voltage.This may cause incorrect operation in the equipment that adopts TFT.For example, if this TFT is the part of display device, the mistake that gradient is expressed then may occurs, thereby cause showing mistake.
On the other hand, when considering to comprise the active area 100 of the first active area 100A and the second active area 100B, the layout of the layout of the second active area 100B and first active area 100A rotation symmetry.Therefore, if high voltage is applied to the second source/drain electrode 133b among the first active area 100A, the amount of the electric current of the first active area 100A that then flows through equal to flow through when (or equaling substantially) high voltage is applied to the 3rd source among the second active area 100B/drain electrode 133c amount of electric current of the second active area 100B.The amount of electric current of the first active area 100A of flowing through when similarly, high voltage is applied to first source among the first active area 100A/drain electrode 133a equal to flow through when (or equaling substantially) high voltage is applied to the 4th source among the second active area 100B/drain electrode 133d amount of electric current of the second active area 100B.
Therefore, when high voltage is applied to second source/drain electrode 133b among the first active area 100A and the 4th source among the second active area 100B/drain electrode 133d, identical when the total amount of the electric current of the active area 100 of flowing through is applied to first source/drain electrode 133a among the first active area 100A and the 3rd source among the second active area 100B/drain electrode 133c with identical voltage basically.That is to say that if the direction of identical voltage changes, then sense of current changes, but the total amount of the electric current of the active area 100 of flowing through is substantially the same.
In other embodiments, the first active area 100A and the second active area 100B can be insulated from each other, make can not flowed through another the influence of electric current of among win the active area 100A and the second active area 100B each.The first active area 100A and the second active area 100B can be for example insulated from each other by using insulating barrier to active layer 125.The shape of the first active area 100A and the second active area 100B can change according to the shape of the insulating barrier that is applied to active layer 125.
In another embodiment, in active area 100, first source/drain electrode 133a can be connected to the 3rd source/drain electrode 133c, and second source/drain electrode 133b can be connected to the 4th source/drain electrode 133d.In this case, can also keep deviate region, overlay region, and the symmetry between the first active area 100A and the second active area 100B (for example, rotation symmetry).In another embodiment, in active area 100, first source/drain electrode 133a can be connected to the 3rd source/drain electrode 133c, and second source/drain electrode 133b can be connected to the 4th source/drain electrode 133d, the first active area 100A and second active area 100B insulation simultaneously.
Fig. 2 A is the layout that the active area 200 of the TFT that has off-set construction according to another embodiment of the present invention is shown.Fig. 2 B is the sectional view along the line I-I intercepting of Fig. 2 A.Fig. 2 C is the sectional view along the line II-II intercepting of Fig. 2 A.According to vertical stacking structure and the above vertical stacking similar of the TFT of current embodiment, therefore will no longer be described here with reference to the described TFT of Figure 1A to Fig. 1 C.Similarly, under the situation of Fig. 2 A-2C and the following drawings, in order to describe for purpose of brevity, the difference of its Reference numeral only is that the first numeral and its structure and the essentially identical element of structure described in embodiment before may no longer be repeated in this description.
Shown in Fig. 2 A, active area 200 is divided into the first active area 200A, the second active area 200B and the 3rd active area 200C.The layout of the layout of the first active area 200A and the 3rd active area 200C is basic identical.In addition, among the first active area 200A, the second active area 200B and the 3rd active area 200C layout of each along vertical symmetry axis (for example, vertical and with the line of 221 pairs of branches of gate electrode) symmetry with line II-II among Fig. 2 A.Such symmetry is also referred to as " reflective symmetry " or " reflective symmetry ".The layout of each is also along horizontal symmetry axis (for example, the line II-II among Fig. 2 A) symmetry among the first active area 200A, the second active area 200B and the 3rd active area 200C.Further, the layout of each is wound with the center rotation symmetry in source region 200 among the first active area 200A, the second active area 200B and the 3rd active area 200C.The width of the part that the gate electrode 221 and the second active area 200B are overlapping can be more overlapping than gate electrode 221 and the first and the 3rd active area 200A and 200C the width little (shown in dotted line among Fig. 2 A) of part.
Shown in Fig. 2 B, in the first active area 200A, the first source/drain electrode 233a and second source/drain electrode 233b is overlapped with gate electrode 221 about gate electrode 221 symmetries simultaneously.In the first active area 200A, active layer 225 comprises the first source/drain region 225a that is positioned at first source/drain electrode 233a below, the second source/drain region 225b that is positioned at second source/drain electrode 233b below, and the first channel region 225ch_1 between first and second sources/ drain region 225a and 225b.
Shown in Fig. 2 C, in the second active area 200B, the 3rd source/drain electrode 233c and the 4th source/drain electrode 233d is about gate electrode 221 symmetries, and separately with gate electrode 221 distance of separation d 2In the second active area 200B, active layer 225 comprises the 3rd source/drain region 225c that is positioned at the 3rd source/drain electrode 233c below, the 4th source/drain region 225d that is positioned at the 4th source/drain electrode 233d below, and the second channel region 225ch_2 between third and fourth source/drain region 225c and 225d.The second channel region 225ch_2 also comprise the deviate region between the 3rd source/drain electrode 233c and the gate electrode 221 and the deviate region between gate electrode 221 and the 4th source/drain electrode 233d (with the second channel region 225ch_2 among Fig. 2 C by distance d 2The various piece correspondence that marks off, also and among Fig. 2 A between gate electrode 221 and third and fourth source/drain electrode 233c and the 233d by distance d 2The zone that marks off is corresponding).
Shown in Fig. 2 A, in the 3rd active area 200C, the 5th source/drain electrode 233e and the 6th source/drain electrode 233f is overlapped with gate electrode 221 about gate electrode 221 symmetries simultaneously.The 5th and the 6th source/ drain electrode 233e and 233f layout and first and second sources/drain electrode 233a and the layout of 233b in the first active area 200A in the 3rd active area 200C basic identical.Therefore, similar with the first active area 200A shown in Fig. 2 B, in the 3rd active area 200C, active layer 225 comprises the 5th source/drain region that is positioned at below, the 5th source/drain electrode 233e, the 6th source/drain region that is positioned at the 6th source/drain electrode 233f below, and the 5th and the 6th source/drain region between the triple channel district.
The 3rd source/drain electrode 233c among first source among the first active area 200A/drain electrode 233a, the second active area 200B and the 5th source/drain electrode 233e among the 3rd active area 200C are electrically connected to each other.Therefore, identical voltage be applied to first from identical source, the 3rd and the 5th source/ drain electrode 233a, 233c and 233e.Similarly, the second source/drain electrode 233b among the first active area 200A, the 4th source/drain electrode 233d among the second active area 200B and the 6th source/drain electrode 233f among the 3rd active area 200C are electrically connected to each other.Therefore, identical voltage be applied to second from identical source, the 4th and the 6th source/ drain electrode 233b, 233d and 233f.
In the first active area 200A, the first source/drain electrode 233a and second source/drain electrode 233b is about gate electrode 221 symmetries.In the second active area 200B, the 3rd source/drain electrode 233c and the 4th source/drain electrode 233d is about gate electrode 221 symmetries.In the 3rd active area 200C, the 5th source/drain electrode 233e and the 6th source/drain electrode 233f is about gate electrode 221 symmetries.Correspondingly, exchange with the voltage that is applied to the second, the 4th and the 6th electrode even be applied to the voltage of the first, the 3rd and the 5th electrode, the total amount of the electric current of the active area 200 of flowing through also can be maintained at constant level in the opposite direction.
In this case, in the first active area 200A and the 3rd active area 200C, first and second sources/ drain region 225a, 225b and the 5th and the two ends of the 6th source/drain region and gate electrode 221 overlapping, thereby increase the amount of " leading to " electric current.In the second active area 200B and since third and fourth source/ drain electrode 233c and 233d all with gate electrode 221 distance of separation d 2, therefore in the second channel region 225ch_2, exist deviate region (and among Fig. 2 A and Fig. 2 C between gate electrode 221 and third and fourth source/drain electrode 233c and the 233d by distance d 2The zone that marks off is corresponding).Therefore, can prevent that high electric field is applied to the second channel region 225ch_2 when voltage is applied to the second active area 200B.Correspondingly, when considering active area 200, can improve " breaking " current characteristics by the performance degradation that prevents TFT.
The first active area 200A, the second active area 200B and the 3rd active area 200C are about gate electrode 221 symmetries.Therefore, if the direction of identical voltage changes, then sense of current changes, but the total amount of the electric current of the active area 200 of flowing through is basic identical.Correspondingly, layout according to first to the 3rd active area 200A to 200C, when applying identical voltage, the total amount of flowing through according to the electric current of the active area among the TFT of current embodiment 200 can be identical, and with the orientation independent that applies voltage, thereby improved " breaking " current characteristics and " leading to " current characteristics.
In other embodiments, first to the 3rd active area 200A to 200C can be insulated from each other, makes the influence of the electric current of each other active area of can not flowed through of winning to the 3rd active area 200A to 200C.First to the 3rd active area 200A to 200C can be for example insulated from each other by using insulating barrier to active layer 225.The shape of first to the 3rd active area 200A to 200C can change according to the shape of the insulating barrier that is applied to active layer 225.
In another embodiment, in active area 200, first source/drain electrode 233a, the 3rd source/drain electrode 233c and the 5th source/drain electrode 233e can be connected to each other, and second source/drain electrode 233b, the 4th source/drain electrode 233d and the 6th source/drain electrode 233f can be connected to each other.In this case, also deviate region, overlay region can be kept, and the symmetry between first to the 3rd active area 200A to 200C (for example, reflective symmetry, rotation symmetry), thereby the total amount of the electric current of the active area 200 of flowing through can be kept.In another embodiment, in active area 200, first source/drain electrode 233a, the 3rd source/drain electrode 233c and the 5th source/drain electrode 233e can be connected to each other, and second source/drain electrode 233b, the 4th source/drain electrode 233d and the 6th source/drain electrode 233f can be connected to each other, and the first active area 200A, the second active area 200B and the 3rd active area 200C are insulated from each other simultaneously.
Fig. 3 A is the layout that the active area 300 of the TFT that has off-set construction according to another embodiment of the present invention is shown.Fig. 3 B is the sectional view along the line I-I intercepting of Fig. 3 A.Fig. 3 C is the sectional view along the line II-II intercepting of Fig. 3 A.Fig. 3 D is the sectional view along the line III-III intercepting of Fig. 3 A.According to vertical stacking structure and the above vertical stacking similar of the TFT of current embodiment, therefore will no longer be described here with reference to the described TFT of Figure 1A to Fig. 1 C.
As shown in Figure 3A, active area 300 is divided into the first active area 300A, the second active area 300B, the 3rd active area 300C and having ideals, morality, culture, and discipline source region 300D.The first active area 300A and having ideals, morality, culture, and discipline source region 300D are basic identical aspect layout, and (for example along vertical symmetry axis, vertical with line I-I among Fig. 3 A and with the line of 321 pairs of branches of gate electrode) symmetry, along horizontal symmetry axis (for example, the line that the second active area 300B and the 3rd active area 300C are separated) symmetry, and be wound with the center symmetry (i.e. rotation symmetry) in source region 300.The layout rotation symmetry of the layout of the second active area 300B and the 3rd active area 300C.Gate electrode 321 and the width overlapping part of the second and the 3rd active area 300B and 300C can than gate electrode 321 with first and the width little (shown in the dotted line among Fig. 3 A) of the overlapping part of having ideals, morality, culture, and discipline source region 300A and 300D.
Shown in Fig. 3 B, in the first active area 300A, the first source/drain electrode 333a and second source/drain electrode 333b is overlapped with gate electrode 321 about gate electrode 321 symmetries simultaneously.In the first active area 300A, active layer 325 comprises the first source/drain region 325a that is positioned at first source/drain electrode 333a below, the second source/drain region 325b that is positioned at second source/drain electrode 333b below, and the first channel region 325ch_1 between first and second sources/drain region 325a and 325b.
Shown in Fig. 3 C, in the second active area 300B, the 3rd source/drain electrode 333c and gate electrode 321 are overlapped, and the 4th source/drain electrode 333d and gate electrode 321 distance of separation d 3In the second active area 300B, active layer 325 comprises the 3rd source/drain region 325c that is positioned at the 3rd source/drain electrode 333c below, the 4th source/drain region 325d that is positioned at the 4th source/drain electrode 333d below, and the second channel region 325ch_2 between third and fourth source/drain region 325c and 325d.The second channel region 325ch_2 comprise deviate region between gate electrode 321 and the 4th source/drain electrode 333d (with the second channel region 325ch_2 among Fig. 3 C by distance d 3The part correspondence that marks off, also and among Fig. 3 A between gate electrode 321 and the 4th source/drain electrode 333d by distance d 3The zone that marks off is corresponding).
Shown in Fig. 3 D, in the 3rd active area 300C, the 5th source/drain electrode 333e and gate electrode 321 distance of separation d 3, and the 6th source/drain electrode 333f and gate electrode 321 are overlapped.In the 3rd active area 300C, active layer 325 comprises the 5th source/drain region 325e that is positioned at below, the 5th source/drain electrode 333e, the 6th source/drain region 325f that is positioned at the 6th source/drain electrode 333f below, and the 5th and the 6th source/ drain region 325e and 325f between triple channel district 325ch_3.Triple channel district 325ch_3 comprise deviate region between the 5th source/drain electrode 333e and gate electrode 321 (with triple channel district 325ch_3 among Fig. 3 D by distance d 3The part correspondence that marks off, also and among Fig. 3 A between gate electrode 321 and the 5th source/drain electrode 333e by distance d 3The zone that marks off is corresponding).
Layout and five source/drain electrode 333e and six source/drain electrode 333f the layout rotation symmetry among three active area 300Cs of the 3rd source/drain electrode 333c and the 4th source/drain electrode 333d in the second active area 300B.
As shown in Figure 3A, in the 300D of having ideals, morality, culture, and discipline source region, the 7th source/drain electrode 333g and the 8th source/drain electrode 333h is overlapped with gate electrode 321 about gate electrode 321 symmetries simultaneously.Layout and first source/drain electrode 333a and second source/drain electrode 333b the layout among first active area 300As of the 7th source/drain electrode 333g and the 8th source/drain electrode 333h in the 300D of having ideals, morality, culture, and discipline source region is basic identical.Therefore, similar with the first active area 300A shown in Fig. 3 B, in the 300D of having ideals, morality, culture, and discipline source region, active layer 325 comprises the 7th source/drain region that is positioned at below, the 7th source/drain electrode 333g, the 8th source/drain region that is positioned at the 8th source/drain electrode 333h below, and the 7th and the 8th source/drain region between the 4th channel region.
The 3rd source/drain electrode 333c among first source among the first active area 300A/drain electrode 333a, the second active area 300B, the 5th source/drain electrode 333e among the 3rd active area 300C and the 7th source/drain electrode 333g among the 300D of having ideals, morality, culture, and discipline source region are electrically connected to each other.Therefore, identical voltage be applied to first, the 3rd from identical source, the 5th and the 7th source/ drain electrode 333a, 333c, 333e and 333g.Similarly, the second source/drain electrode 333b among the first active area 300A, the 4th source/drain electrode 333d among the second active area 300B, the 6th source/drain electrode 333f among the 3rd active area 300C and the 8th source/drain electrode 333h among the 300D of having ideals, morality, culture, and discipline source region are electrically connected to each other.Therefore, identical voltage be applied to second, the 4th from identical source, the 6th and the 8th source/ drain electrode 333b, 333d, 333f and 333h.
In this case, in the first active area 300A and having ideals, morality, culture, and discipline source region 300D, first and second sources/drain region 325a, 325b and the 7th and the two ends of the 8th source/drain region and gate electrode 321 overlapping, thereby significantly improve " leading to " current characteristics.In the second active area 300B, the 4th source/drain electrode 333d and gate electrode 321 distance of separation d 3, therefore the second channel region 325ch_2 have and Fig. 3 A and Fig. 3 C between gate electrode 321 and the 4th source/drain electrode 333d by distance d 3The corresponding deviate region in zone that marks off.In the 3rd active area 300C, the 5th source/drain electrode 333e and gate electrode 321 distance of separation d 3, therefore triple channel district 325ch_3 have and Fig. 3 A and Fig. 3 D between the 5th source/drain electrode 333e and the gate electrode 321 by distance d 3The corresponding deviate region in zone that marks off.Because each among the second active area 300B and the 3rd active area 300C has deviate region, therefore, can prevent that high electric field is applied to the second channel region 325ch_2 and triple channel district 325ch_3.Correspondingly, when considering active area 300, can prevent the performance degradation of TFT, thereby improve " breaking " current characteristics.
As mentioned above, the first active area 300A and having ideals, morality, culture, and discipline source region 300D are basic identical aspect layout, and symmetry axis symmetry vertically (and along the horizontal symmetrical axial symmetry, rotation symmetry simultaneously), and the layout of the layout of the second active area 300B and the 3rd active area 300C rotation symmetry.Therefore, when the direction of identical voltage changed, sense of current changed, but the total amount of the electric current of the active area 300 of flowing through is basic identical.Layout according to first to fourth active area 300A to 300D, when applying identical voltage, the total amount of flowing through according to the electric current of the active area among the TFT of current embodiment 300 can be identical, and with the orientation independent that applies voltage, thereby improved " breaking " current characteristics and " leading to " current characteristics.
In another embodiment, first to fourth active area 300A to 300D can be insulated from each other, makes the influence of electric current of each other active area of can not flowed through among the first to fourth active area 300A to 300D.And, as mentioned above, in another embodiment, in active area 300, first source/drain electrode 333a, the 3rd source/drain electrode 333c, the 5th source/drain electrode 333e and the 7th source/drain electrode 333g can be connected to each other, and second source/drain electrode 333b, the 4th source/drain electrode 333d, the 6th source/drain electrode 333f and the 8th source/drain electrode 333h can be connected to each other, and first to fourth active area 300A to 300D is insulated from each other simultaneously.
Fig. 4 A is the layout that the active area 400 of the TFT that has off-set construction according to another embodiment of the present invention is shown.Fig. 4 B is the sectional view along the line I-I intercepting of Fig. 4 A.Fig. 4 C is the sectional view along the line II-II intercepting of Fig. 4 A.According to vertical stacking structure and the above vertical stacking similar of the TFT of current embodiment, therefore will no longer be described here with reference to the described TFT of Figure 1A to Fig. 1 C.
Shown in Fig. 4 A, active area 400 is divided into the rotational symmetric each other first active area 400A and the second active area 400B.TFT according to current embodiment has double-grid structure, in this double-grid structure, and two gate electrodes, promptly first grid electrode 421a is included in the active area 400 by parallel with the second gate electrode 421b.First grid electrode 421a and the width overlapping part of the second active area 400B can be littler than the width with the overlapping part of the first active area 400A of first grid electrode 421a, and the second gate electrode 421b and the width overlapping part of the first active area 400A can be than the second gate electrode 421b and width little (shown in the dotted line among Fig. 4 A) the overlapping part of the second active area 400b.
Shown in Fig. 4 B, in the first active area 400A, first source/drain electrode 433a and first grid electrode 421a are overlapped, and the second source/drain electrode 433b and the second gate electrode 421b distance of separation d 4Therefore, active layer 425 comprises the first source/drain region 425a that is positioned at first source/drain electrode 433a below, the second source/drain region 425b that is positioned at second source/drain electrode 433b below, and the first channel region 425ch_1 between first and second sources/drain region 425a and 425b.The first channel region 425ch_1 comprise deviate region between first grid electrode 421a and the second gate electrode 421b (and along regional corresponding between first grid electrode 421a and the second gate electrode 421b of the line I-I among Fig. 4 A) and the deviate region between the second gate electrode 421b and second source/drain electrode 433b (with the first channel region 425ch_1 among Fig. 4 B by distance d 4The part correspondence that marks off, also and among Fig. 4 A between the second gate electrode 421b and the second source/drain electrode 433d by distance d 4The zone that marks off is corresponding).
Shown in Fig. 4 C, in the second active area 400B, the 3rd source/drain electrode 433c and first grid electrode 421a distance of separation d 4, and the 4th source/drain electrode 433d and the second gate electrode 421b are overlapped.Therefore, active layer 425 comprises the 3rd source/drain region 425c that is positioned at the 3rd source/drain electrode 433c below, the 4th source/drain region 425d that is positioned at the 4th source/drain electrode 433d below, and the second channel region 425ch_2 between third and fourth source/drain region 425c and 425d.The second channel region 425ch_2 comprise deviate region between the 3rd source/drain electrode 433c and first grid electrode 421a (with the second channel region 425ch_2 among Fig. 4 C by distance d 4The part correspondence that marks off, also and among Fig. 4 A between the 3rd source/drain electrode 433c and the first grid electrode 421a by distance d 4The zone that marks off is corresponding), and the deviate region between first grid electrode 421a and the second gate electrode 421b (and along regional corresponding between first grid electrode 421a and the second gate electrode 421b of the line II-II among Fig. 4 A).
Layout and three source/drain electrode 433c and four source/drain electrode 433d the layout rotation symmetry among second active area 400Bs of the first source/drain electrode 433a and second source/drain electrode 433b in the first active area 400A.When considering the first grid electrode 421a and the second gate electrode 421b, also present identical rotation symmetry, the first grid electrode 421a and the second gate electrode 421b occupy similar size in the deviate region of the first active area 400A and the second active area 400B and overlay region.In active area 400, the first grid electrode 421a and the second gate electrode 421b rotate symmetry each other.
The 3rd source/drain electrode 433c among first source among the first active area 400A/drain electrode 433a and the second active area 400B is electrically connected to each other.Therefore, identical voltage is applied to first and the 3rd source/ drain electrode 433a and 433c from identical source.Similarly, second source/drain electrode 433b among the first active area 400A and the 4th source/drain electrode 433d among the second active area 400B are electrically connected to each other.Therefore, identical voltage is applied to second and the 4th source/ drain electrode 433b and 433d from identical source.
In the first active area 400A, if high voltage is applied to second source/drain electrode 433b, then electric current from first source/drain region 425a flows to the first channel region 425ch_1, flows to second source/drain region 425b then.In this case, the first and second gate electrode 421a and 421b reduce the amount of " breaking " electric current, and the deviate region among the first channel region 425ch_1 prevents that high electric field is applied to the first channel region 425ch_1.Therefore, can prevent the performance degradation of TFT, thereby improve " breaking " current characteristics.In addition, first source/drain region 425a and first grid electrode 421a are overlapping, thereby improve " leading to " current characteristics.
Change (for example, high voltage is applied to the first source/drain electrode 433a among the first active area 400A) if apply high-tension direction, then electric current from second source/drain region 425b flows to the first channel region 425ch_1, flows to first source/drain region 425a then.Different when in this case, deviate region is applied to second source/drain electrode 433b with respect to the relative position and the high voltage that have applied high-tension first source/drain region 425a.Different when therefore, the amount that is formed on the intensity of the electric field among the first channel region 425ch_1 and " leading to " electric current and " breaking " electric current also is applied to second source/drain electrode 433b with high voltage.
That is to say, if only consider the first active area 400A, then when the voltage that is applied to first source/drain electrode 433a exchanged with the voltage that is applied to second source/drain electrode 433b, deviate region was with respect to the relative position difference that has applied high-tension source/drain electrode among the first channel region 425ch_1.As a result, the intensity of electric field that is applied to the first channel region 425ch_1 is different when being applied to second source/drain electrode 433b at identical voltage when high voltage is applied to first source/drain electrode 433a.Therefore, when identical voltage is applied to first and second sources/ drain electrode 433a and 433b respectively, the amount difference of the electric current of the first channel region 425ch_1 that flows through.That is to say that the amount of electric current changes according to the direction that applies identical voltage.In addition, because therefore same phenomenon when only considering the second active area 400B, also can take place in the layout of the first and second active area 400A and 400B rotation symmetry.
On the other hand, when considering to comprise the active area 400 of the first active area 400A and the second active area 400B, the layout of the layout of the second active area 400B and first active area 400A rotation symmetry.Therefore, if high voltage is applied to the second source/drain electrode 433b among the first active area 400A, the amount of the electric current of the first active area 400A that then flows through equal to flow through when (or equaling substantially) same high voltage is applied to the 3rd source among the second active area 400B/drain electrode 433c amount of electric current of the second active area 400B.Similarly, when if high voltage is applied to first source among the first active area 400A/drain electrode 433a, the amount of the electric current of the first active area 400A that then flows through equal to flow through when (or equaling substantially) same high voltage is applied to the 4th source among the second active area 400B/drain electrode 433d amount of electric current of the second active area 400B.
Therefore, when high voltage is applied to second source/drain electrode 433b among the first active area 400A and the 4th source among the second active area 400B/drain electrode 433d, basic identical when the total amount of the electric current of the flow through first and second active area 400A and 400B and same high voltage are applied to first source/drain electrode 433a among the first active area 400A and the 3rd source among the second active area 400B/drain electrode 433c.Therefore, if the direction of identical voltage changes, then sense of current changes, but the maintenance of the total amount of the electric current of the active area 400 of flowing through is basic identical.
In other embodiments, the first and second active area 400A and 400B can be insulated from each other, make the influence of electric current of each other active area of can not flowed through among the first and second active area 400A and the 400B.In another embodiment, in active area 400, first source/drain electrode 433a can be connected to the 3rd source/drain electrode 433c, and second source/drain electrode 433b can be connected to the 4th source/drain electrode 433d, and the first and second active area 400A and 400B are insulated from each other simultaneously.
Fig. 5 A is the layout that the active area 500 of the TFT that has off-set construction according to another embodiment of the present invention is shown.Fig. 5 B is the sectional view along the line I-I intercepting of Fig. 5 A.Fig. 5 C is the sectional view along the line II-II intercepting of Fig. 5 A.According to vertical stacking structure and the above vertical stacking similar of the TFT of current embodiment, therefore will no longer be described here with reference to the described TFT of Figure 1A to Fig. 1 C.Except at two gate electrodes, promptly be formed with outside the offset electrodes between the first grid electrode 521a and the second gate electrode 521b, similar according to the TFT of the TFT of current embodiment and Fig. 4 A to Fig. 4 C.In certain embodiments, identical with the offset electrodes shown in Fig. 5 A, offset electrodes comprises two offset electrodes.
Shown in Fig. 5 A, active area 500 is divided into the rotational symmetric each other first active area 500A and the second active area 500B.TFT according to current embodiment has double-grid structure, and in this double-grid structure, first grid electrode 521a is included in the active area 500 by parallel with the second gate electrode 521b.First grid electrode 521a and the width overlapping part of the second active area 500B can be littler than the width with the overlapping part of the first active area 500A of first grid electrode 521a, and the second gate electrode 521b and the width overlapping part of the first active area 500A can be than the second gate electrode 521b and width little (shown in the dotted line among Fig. 5 A) the overlapping part of the second active area 500B.
Shown in Fig. 5 B, in the first active area 500A, first source/drain electrode 533a and first grid electrode 521a are overlapped, and the second source/drain electrode 533b and the second gate electrode 521b distance of separation d 5Therefore, active layer 525 comprises the first source/drain region 525a that is positioned at first source/drain electrode 533a below, the second source/drain region 525b that is positioned at second source/drain electrode 533b below, and the first channel region 525ch_1 between first and second sources/drain region 525a and 525b.The first channel region 525ch_1 comprises that deviate region between first grid electrode 521a and the second gate electrode 521b is (and along regional corresponding between first grid electrode 521a and the second gate electrode 521b of the line I-I among Fig. 5 A, comprise corresponding zone with the first offset electrodes 533o_1), and the deviate region between the second gate electrode 521b and second source/drain electrode 533b (with the first channel region 525ch_1 among Fig. 5 B by distance d 5The part correspondence that marks off, also and among Fig. 5 A between the second gate electrode 521b and the second source/drain electrode 533d by distance d 5The zone that marks off is corresponding).
The first offset electrodes 533o_1 between the first grid electrode 521a and the second gate electrode 521b with active layer 525 insulation.The first offset electrodes 533o_1 can be electrically connected to first and second gate electrode 521a and the 521b.The first skew insulating barrier 531o_1 is formed between the first channel region 525ch_1 and the first offset electrodes 533o_1 so that the first offset electrodes 533o_1 and active layer 525 are insulated.
Shown in Fig. 5 C, in the second active area 500B, the 3rd source/drain electrode 533c and first grid electrode 521a distance of separation d 5, and the 4th source/drain electrode 533d and the second gate electrode 521b are overlapped.In the second active area 500B, active layer 525 comprises the 3rd source/drain region 525c that is positioned at the 3rd source/drain electrode 533c below, the 4th source/drain region 525d that is positioned at the 4th source/drain electrode 533d below, and the second channel region 525ch_2 between third and fourth source/drain region 525c and 525d.The second channel region 525ch_2 comprise deviate region between the 3rd source/drain electrode 533c and first grid electrode 521a (with the second channel region 525ch_2 among Fig. 5 C by distance d 5The part correspondence that marks off, also and among Fig. 5 A between the 3rd source/drain electrode 533c and the first grid electrode 521a by distance d 5The zone that marks off is corresponding), and the deviate region between first grid electrode 521a and the second gate electrode 521b (and, comprising corresponding zone) with the second offset electrodes 533o_2 along regional corresponding between first grid electrode 521a and the second gate electrode 521b of the line II-II among Fig. 5 A.
The second offset electrodes 533o_2 between the first grid electrode 521a and the second gate electrode 521b with active layer 525 insulation.The second offset electrodes 533o_2 can be electrically connected to first and second gate electrode 521a and the 521b.The second skew insulating barrier 531o_2 is formed between the second channel region 525ch_2 and the second offset electrodes 533o_2 so that the second offset electrodes 533o_2 and active layer 525 are insulated.
Layout and three source/drain electrode 533c and four source/drain electrode 533d the layout rotation symmetry among second active area 500Bs of the first source/drain electrode 533a and second source/drain electrode 533b in the first active area 500A.When considering the first grid electrode 521a and the second gate electrode 521b, also present identical rotation symmetry, the first grid electrode 521a and the second gate electrode 521b occupy similar size in the deviate region of the first active area 500A and the second active area 500B and overlay region.In active area 500, the first grid electrode 521a and the second gate electrode 521b rotate symmetry each other.
The 3rd source/drain electrode 533c among first source among the first active area 500A/drain electrode 533a and the second active area 500B is electrically connected to each other.Therefore, identical voltage is applied to first and the 3rd source/ drain electrode 533a and 533c from identical sources.Similarly, second source/drain electrode 533b among the first active area 500A and the 4th source/drain electrode 533d among the second active area 500B are electrically connected to each other.Therefore, identical voltage is applied to second and the 4th source/ drain electrode 533b and 533d from identical sources.
In the first active area 500A, if high voltage is applied to second source/drain electrode 533b, then electric current from first source/drain region 525a flows to the first channel region 525ch_1, flows to second source/drain region 525b then.In this case, the first and second gate electrode 521a and 521b reduce the amount of " breaking " electric current, and the deviate region among the first channel region 525ch_1 prevents that high electric field is applied to the first channel region 525ch_1.In addition, the first offset electrodes 533o_1 can be so that electric current can be flowed through smoothly the mode of deviate region control the resistance value of the deviate region between the first grid electrode 521a and the second gate electrode 521b.Therefore, can prevent the performance degradation of TFT, thereby improve " breaking " current characteristics.Further, first source/drain electrode 525a and first grid electrode 521a are overlapping, thereby improve " leading to " current characteristics.
Change (for example, high voltage is applied to the first source/drain electrode 533a among the first active area 500A) if apply high-tension direction, then electric current from second source/drain region 525b flows to the first channel region 525ch_1, flows to first source/drain region 525a then.Different when in this case, deviate region is applied to second source/drain electrode 533b with respect to the relative position and the high voltage that have applied high-tension first source/drain region 525a.Different when therefore, the amount that is formed on the intensity of the electric field among the first channel region 525ch_1 and " leading to " electric current and " breaking " electric current also is applied to second source/drain electrode 533b with high voltage.
That is to say, if only consider the first active area 500A, then when the voltage that is applied to first source/drain electrode 533a exchanged with the voltage that is applied to second source/drain electrode 533b, the deviate region of the first channel region 525ch_1 was with respect to the relative position difference that has applied high-tension source/drain electrode.As a result, when high voltage is applied to first source/drain electrode 533a, different when intensity and the identical voltage that is applied to the electric field of the first channel region 525ch_1 is applied to second source/drain electrode 533b.Therefore, when identical voltage is applied to first and second sources/ drain electrode 533a and 533b respectively, the amount difference of the electric current of the first channel region 525ch_1 that flows through.That is to say that the amount of electric current changes according to the direction that applies identical voltage.In addition, because therefore same phenomenon when only considering the second active area 500B, also can take place in the rotation of the layout among the first and second active area 500A and 500B symmetry.
On the other hand, when considering to comprise the active area 500 of the first active area 500A and the second active area 500B, the layout of the layout of the second active area 500B and first active area 500A rotation symmetry.Therefore, if high voltage is applied to the second source/drain electrode 533b among the first active area 500A, the amount of the electric current of the first active area 500A that then flows through equal to flow through when (or being substantially equal to) same high voltage is applied to the 3rd source among the second active area 500B/drain electrode 533c amount of electric current of the second active area 500B.Similarly, when if high voltage is applied to first source among the first active area 500A/drain electrode 533a, the amount of the electric current of the first active area 500A that then flows through equal to flow through when (or being substantially equal to) same high voltage is applied to the 4th source among the second active area 500B/drain electrode 533d amount of electric current of the second active area 500B.
Therefore, when high voltage is applied to second source/drain electrode 533b among the first active area 500A and the 4th source among the second active area 500B/drain electrode 533d, basic identical when the total amount of the electric current of the flow through first and second active area 500A and 500B and same high voltage are applied to first source/drain electrode 533a among the first active area 500A and the 3rd source among the second active area 500B/drain electrode 533c.That is to say that if the direction of identical voltage changes, then sense of current changes, but the maintenance of the total amount of the electric current of the active area 500 of flowing through is basic identical.
In other embodiments, the first and second active area 500A and 500B can insulate each other, make the influence of electric current of each another active area of can not flowed through among the first and second active area 500A and the 500B.In another embodiment, in active area 500, first source/drain electrode 533a can be connected to the 3rd source/drain electrode 533c, second source/drain electrode 533b can be connected to the 4th source/drain electrode 533d, and the first offset electrodes 533o_1 can be connected to the second offset electrodes 533o_2, and the first and second active area 500A and 500B are insulated from each other simultaneously.
Fig. 6 A is the layout that the active area 600 of the TFT that has off-set construction according to another embodiment of the present invention is shown.Fig. 6 B is the sectional view along the line I-I intercepting of Fig. 6 A.According to vertical stacking structure and the above vertical stacking similar of the TFT of current embodiment, therefore will no longer be described here with reference to the described TFT of Figure 1A to Fig. 1 C.TFT according to current embodiment has double-grid structure, in this double-grid structure, and two gate electrodes, promptly first grid electrode 621a is included in the active area 600 by parallel with the second gate electrode 621b.
Shown in Fig. 6 B, in active area 600, first source/drain electrode 633a and first grid electrode 621a are overlapped, and second source/drain electrode 633b and the second gate electrode 621b are overlapped.First source/drain electrode the 633a and the second gate electrode 621b distance of separation d 6, therefore, can think that first source/drain electrode 633a is offset from the second gate electrode 621b.Similarly, second source/drain electrode 633b and first grid electrode 621a distance of separation d 6, therefore, can think that second source/drain electrode 633b is offset from first grid electrode 621a.
Active layer 625 comprises the first source/drain region 625a that is positioned at first source/drain electrode 633a below, the second source/drain region 625b that is positioned at second source/drain electrode 633b below, and the channel region 625ch between first and second sources/drain region 625a and 625b.Channel region 625ch comprise deviate region between first grid electrode 621a and the second gate electrode 621b (and along regional corresponding between first grid electrode 621a and the second gate electrode 621b of the line I-I among Fig. 6 A, comprise with by distance d 6The zone of the common factor correspondence in two zones that mark off).
In active area 600, the layout of the layout of first source/drain electrode 633a and second source/drain electrode 633b is along vertical symmetry axis (for example, the line of and centre first grid electrode 621a and second gate electrode 621b between vertical with line I-I among Fig. 6 A) symmetry.In addition, the layout of first grid electrode 621a and the layout of the second gate electrode 621b are also along identical vertical symmetry axis symmetry.Source/drain electrode and gate electrode also present along the identical symmetry of horizontal symmetry axis (for example, the line I-I among Fig. 6 A).Further, the electrode of these groups also rotates symmetry.
In active area 600, if high voltage is applied to second source/drain electrode 633b, then electric current from first source/drain region 625a flows to channel region 625ch, flows to second source/drain region 625b then.In this case, the first and second gate electrode 621a and 621b reduce the amount of " breaking " electric current, and the deviate region of channel region 625ch prevents that high electric field is applied to channel region 625ch.Therefore, can prevent the performance degradation of TFT, thereby improve " breaking " current characteristics.In addition, first source/drain electrode 625a and first grid electrode 621a are overlapping, thereby improve " leading to " current characteristics.Similarly, the second source/drain region 625b and the second gate electrode 621b are overlapping, therefore improve " leading to " current characteristics.
Change (for example, high voltage is applied to the first source/drain electrode 633a in first active area 600) if apply high-tension direction, then electric current from second source/drain region 625b flows to channel region 625ch, flows to first source/drain region 625a then.Identical when in this case, deviate region is applied to second source/drain electrode 633b with respect to the relative position and the high voltage that have applied high-tension source/drain region 625a.Therefore, compare when being applied to second source/drain electrode 633b with high voltage, the electric current of the active area 600 of flowing through difference aspect direction, but substantially the same aspect amount.That is to say that when the amplitude of voltage was identical for each direction, the amount of electric current was substantially the same, and with the orientation independent that applies voltage.
Fig. 7 A is the layout that the active area 700 of the TFT that has off-set construction according to another embodiment of the present invention is shown.Fig. 7 B is the sectional view along the line I-I intercepting of Fig. 7 A.According to vertical stacking structure and the above vertical stacking similar of the TFT of current embodiment, therefore will no longer be described here with reference to the described TFT of Figure 1A to Fig. 1 C.TFT according to current embodiment has double-grid structure, in this double-grid structure, and two gate electrodes, promptly first grid electrode 721a is included in the active area 700 by parallel with the second gate electrode 721b.
Shown in Fig. 7 B, in active area 700, first source/drain electrode 733a and first grid electrode 721a are overlapped, and second source/drain electrode 733b and the second gate electrode 721b are overlapped.First source/drain electrode the 733a and the second gate electrode 721b distance of separation d 7, therefore, can think that first source/drain electrode 733a is offset from the second gate electrode 721b.Similarly, second source/drain electrode 733b and first grid electrode 721a distance of separation d 7, therefore, can think that second source/drain electrode 733b is offset from first grid electrode 721a.
Active layer 725 comprises the first source/drain region 725a that is positioned at first source/drain electrode 733a below, the second source/drain region 725b that is positioned at second source/drain electrode 733b below, and the channel region 725ch between first and second sources/drain region 725a and 725b.Channel region 725ch comprises deviate region between first grid electrode 721a and the second gate electrode 721b (and along regional corresponding between first grid electrode 721a and the second gate electrode 721b of the line I-I among Fig. 7 A, comprising the zone corresponding with offset electrodes 733o).
Offset electrodes 733o between the first grid electrode 721a and the second gate electrode 721b with active layer 725 insulation.Offset electrodes 733o can be electrically connected to first and second gate electrode 721a and the 721b.Skew insulating barrier 731o is formed between channel region 725ch and the offset electrodes 733o so that offset electrodes 733o and active layer 725 are insulated.
In active area 700, the layout of the layout of first source/drain electrode 733a and second source/drain electrode 733b is along vertical symmetry axis (for example, vertical with line I-I among Fig. 7 A and with the line of offset electrodes 733o to branch) symmetry.In addition, the layout of first grid electrode 721a and the layout of the second gate electrode 721b are also along identical vertical symmetry axis symmetry.Also present between the electrode of these groups along horizontal symmetry axis () identical symmetry for example, the line I-I of Fig. 7 A, and between the electrode of these groups, also have the rotation symmetry.
In active area 700, if high voltage is applied to second source/drain electrode 733b, then electric current from first source/drain region 725a flows to channel region 725ch, flows to second source/drain region 725b then.In this case, the first and second gate electrode 721a and 721b reduce the amount of " breaking " electric current, and the deviate region among the channel region 725ch prevents that high electric field is applied to channel region 725ch.Correspondingly, can prevent the performance degradation of TFT, thereby improve " breaking " current characteristics.In addition, offset electrodes 733o can be so that electric current can be flowed through smoothly the mode of deviate region control the resistance value of the deviate region between the first grid electrode 721a and the second gate electrode 721b.Further, first source/drain region 725a and first grid electrode 721a are overlapping, and second source/drain region 725b and the second gate electrode 721b are overlapping, thereby improve " leading to " current characteristics.
Change (for example, high voltage is applied to the first source/drain electrode 733a in the active area 700) if apply high-tension direction, then electric current from second source/drain region 725b flows to channel region 725ch, flows to first source/drain region 725a then.Identical when in this case, deviate region is applied to second source/drain electrode 733b with respect to the relative position and the high voltage that have applied high-tension source/drain region 725a.Therefore, compare when being applied to second source/drain electrode 733b with high voltage, the electric current of the active area 700 of flowing through is difference aspect its direction, but substantially the same aspect its amount.That is to say that when the amplitude of voltage was identical for each direction, the amount of electric current was substantially the same, and with the orientation independent that applies voltage.
Fig. 8 is the layout that the active area 800 of the TFT that has off-set construction according to another embodiment of the present invention is shown.Active area 800 is divided into the rotational symmetric each other first active area 800A and the second active area 800B.
Referring to Fig. 8, except first source/drain electrode 833a is the combination of the first source/drain electrode 133a and the 3rd source/drain electrode 133c of the active area 100 shown in Figure 1A, and second source/drain electrode 833b is outside the combination of the second source/drain electrode 133b of active area 100 and the 4th source/drain electrode 133d, and active area 800 has the structure identical with the active area 100 of Figure 1A.Therefore, the TFT of Fig. 8 is identical with the sectional view of Figure 1B along the sectional view of the line I-I intercepting of Fig. 8, and the TFT of Fig. 8 is identical with the sectional view of Fig. 1 C along the sectional view of the line II-II intercepting of Fig. 8.
In the first active area 800A, first source/drain electrode 833a and gate electrode 821 are overlapped, and second source/drain electrode 833b and gate electrode 821 distance of separation d 8In the second active area 800B, first source/drain electrode 833a and gate electrode 821 distance of separation d 8, and second source/drain electrode 833b and gate electrode 821 are overlapped.
As above active area 100 to Figure 1A to Fig. 1 C is described, in the TFT of Fig. 8, because the deviate region between one of gate electrode 821 and source/drain electrode, wherein each of source/drain electrode and gate electrode 821 distance of separation d 8, therefore can prevent that high electric field is applied to channel region.Therefore, can prevent the performance degradation of TFT, thereby improve " breaking " current characteristics.In addition, the first source/drain electrode 833a and second source/drain electrode 833b is overlapped with gate electrode 821, thereby has improved " leading to " current characteristics.Because first source/drain electrode 833a, second source/drain electrode 833b and gate electrode 821 are wound with the center rotation symmetry in source region 800, therefore when the amplitude of voltage is identical for each direction, the amount of electric current of channel region of flowing through is substantially the same, and is applied to the orientation independent of first source/drain electrode 833a and second source/drain electrode 833b with voltage.
Although the first source/drain electrode 833a and second source/drain electrode 833b is connected to each other in the first active area 800A and the second active area 800B, can be by active layer 825 insulation be limited current paths.
Fig. 9 is the layout that the active area 900 of the TFT that has off-set construction according to another embodiment of the present invention is shown.Active area 900 is divided into the first active area 900A and the second active area 900B that is mutually symmetrical along horizontal symmetry axis (for example, the line that the first active area 900A and the second active area 900B are separated).
Active area 900 is combinations of the active area 800 of two Fig. 8, and the layout of one of them active area 800 is mirror images (reflection) of the layout of another active area 800.Specifically, active area 900 has such structure: the active area 800 of two Fig. 8 with a distance (for example, predetermined distance) is separated from each other and is mutually symmetrical along horizontal symmetry axis (for example, the line that the first active area 900A and the second active area 900B are separated).In addition, the basal surface of first and second sources of active area 800/ drain electrode 833a and 833b and top surface are extended and are bonded together to form the first source/drain electrode 933a and second source/drain electrode 933b.Therefore, the sectional view that the line I-I along Fig. 9 of the TFT of Fig. 9 intercepts is identical with the sectional view of Figure 1B, and the sectional view that the line II-II along Fig. 9 of the TFT of Fig. 9 intercepts is identical with the sectional view of Fig. 1 C.
In the first active area 900A, first source/drain electrode 933a and gate electrode 921 are overlapped, and the part of first source/drain electrode 933a is offset from gate electrode 921.In addition, second source/drain electrode 933b and gate electrode 921 are overlapped, and the part of second source/drain electrode 933b is offset from gate electrode 921.
As above active area 100 to Figure 1A to Fig. 1 C is described, in the TFT of Fig. 9, can be by using and gate electrode 921 distance of separation d 9Deviate region prevent that high electric field is applied to channel region.Therefore, can prevent the performance degradation of TFT, thereby improve " breaking " current characteristics.In addition, the first source/drain electrode 933a and second source/drain electrode 933b is overlapped with gate electrode 921, thereby has improved " leading to " current characteristics.Because the first active area 900A and the second active area 900B are mutually symmetrical along horizontal symmetry axis, therefore when the amplitude of voltage is identical for each direction, the amount of electric current of channel region of flowing through is substantially the same, and is applied to first source/drain electrode 933a with voltage or second source/drain electrode 933b is irrelevant.
Although the first source/drain electrode 933a and second source/drain electrode 933b is connected in the first active area 900A and the second active area 900B, can be by active layer 925 insulation be limited current paths.
Below describe the various embodiment that have the TFT of off-set construction according to of the present invention, but the invention is not restricted to above embodiment.The feature of exemplary embodiment can comprise deviate region and the overlay region among the active area that is present in the unit, and the electrode that presents the symmetry of some form relative to each other, thereby improves " breaking " current characteristics and " leading to " current characteristics.
Figure 10 illustrates according to the channel current I among the TFT of the embodiment of the invention Ds(vertical axes) is to grid voltage V gThe curve chart of the simulation result that the characteristic of (trunnion axis) and the channel current of comparative example compare the characteristic of grid voltage.In the curve chart of Figure 10, " traditional TFT ◇ " expression does not have traditional TFT of off-set construction, " skew TFT zero " expression has traditional TFT of off-set construction, and " mixing TFT △ " expression is according to for example TFT with off-set construction shown in Figure 1A to Fig. 1 C of the present invention.Here, use the ATLAS device emulation.
Referring to Figure 10, this TFT of three types comparison shows that: " skew TFT zero " illustrates " breaking " electric current of minimum (for example, with negative-gate voltage V gCorresponding) and " leading to " electric current of minimum (for example, with positive gate voltage V gCorresponding).In having traditional TFT of off-set construction " skew TFT zero ",, but also cause the amount of " leading to " electric current less owing to the high resistance of deviate region owing to deviate region causes the amount of " breaking " electric current less.Cause " traditional TFT ◇ " that " leading to " electric current of maximum is shown owing to leakage current but " breaking " electric current of maximum also is shown.The amount that " mix TFT △ " illustrates " lead to " electric current is the same big with the amount that utilization " traditional TFT ◇ " is drawn, but the amount that the amount of " breaking " electric current and utilization " are offset TFT zero " draws is the same little.In the TFT mixing TFT △ that has according to off-set construction of the present invention, can reach a conclusion: the lap of source/drain electrode and gate electrode makes the amount of " leading to " electric current bigger, and the deviate region between source/drain electrode and the gate electrode makes the amount of " breaking " electric current less.
That is to say, from the curve chart of Figure 10, can notice, when use according to the embodiment of the invention have the TFT of deviate region and nondeviate region the time, can reduce the amount of " break " electric current, simultaneously the amount of increase " leading to " electric current.And, as mentioned above, if source/drain electrode and gate electrode (or a plurality of gate electrode) (for example are arranged to symmetry, reflective symmetry, rotation symmetry), then when the amplitude of voltage is identical for each direction, the amount of electric current of channel region of flowing through is basic identical, and with the orientation independent that applies voltage to grid.
Although specifically illustrated and described the present invention with reference to exemplary embodiment, but those of ordinary skills are to be understood that, under the situation that does not deviate from the spirit and scope of the present invention that limit as following claim and equivalent thereof, can carry out various changes to form and details here.

Claims (44)

1. thin-film transistor, comprising: be divided into the active area of first active area and second active area, described active area comprises:
Gate electrode;
Active layer comprises first active layer corresponding with described first active area and second active layer corresponding with described second active area, described first active layer and described second active layer and described gate electrode;
Gate insulation layer is between described gate electrode and described active layer; And
Source/drain electrode layer comprises first source/drain electrode and the second source/drain electrode and the 3rd source/drain electrode that is electrically connected to described second active layer and the 4th source/drain electrode that are electrically connected to described first active layer, wherein:
Two source/drain electrodes and the described gate electrode selected from described first to fourth source/drain electrode are overlapped,
Two source/drain electrodes of in described first to fourth source/drain electrode other are offset from described gate electrode, and
Described first to fourth source/drain electrode and described gate electrode are arranged symmetrically.
2. thin-film transistor according to claim 1, wherein:
Described first and the 3rd source/drain electrode be electrically connected to each other, make identical voltage be applied to described first and the 3rd source/drain electrode, and
Described second and the 4th source/drain electrode be electrically connected to each other, make identical voltage be applied to described second and the 4th source/drain electrode.
3. thin-film transistor according to claim 2, wherein:
Described first source/drain electrode and described the 3rd source/drain electrode are connected to each other; And
Described second source/drain electrode and described the 4th source/drain electrode are connected to each other.
4. a thin-film transistor comprises two thin-film transistors as claimed in claim 3, and wherein respective sources/the drain electrode of these two thin-film transistors is connected to be used as single thin-film transistor with the mode of gate electrode with symmetric arrangement.
5. thin-film transistor according to claim 1, wherein said active layer comprise the material of selecting by in amorphous silicon, polysilicon, microcrystal silicon, oxide semiconductor, organic semiconductor and the group that constitutes thereof.
6. thin-film transistor according to claim 1, wherein said active area further comprise the ohmic contact layer between described active layer and described source/drain electrode layer.
7. thin-film transistor according to claim 1, wherein:
Described first active layer comprises first source corresponding with described first source/drain electrode/drain region, the second source/drain region corresponding with described second source/drain electrode, and first channel region between described first source/drain region and described second source/drain region, and
Described second active layer comprises three source corresponding with described the 3rd source/drain electrode/drain region, the four source/drain region corresponding with described the 4th source/drain electrode, and second channel region between described the 3rd source/drain region and described the 4th source/drain region.
8. thin-film transistor according to claim 7, wherein:
Described first channel region comprise not with described gate electrode, described first source/drain electrode and described second source/drain electrode in any first overlapping deviate region, and
Described second channel region comprise not with described gate electrode, described the 3rd source/drain electrode and described the 4th source/drain electrode in any second overlapping deviate region.
9. thin-film transistor according to claim 1, the source in source/drain electrode layer in wherein said second active area and described first active area/drain electrode layer rotation symmetry.
10. thin-film transistor according to claim 9, wherein:
One and described gate electrode in described first source/drain electrode and the described second source/drain electrode, and
In described first source/drain electrode and the described second source/drain electrode another is offset from described gate electrode.
11. thin-film transistor according to claim 1, wherein said first active area and described second active area are insulated from each other.
12. thin-film transistor according to claim 1, wherein said gate electrode comprise the first grid electrode parallel to each other and second gate electrode.
13. thin-film transistor according to claim 12, wherein:
Described first and the 3rd source/drain electrode be electrically connected to each other, make identical voltage be applied to described first and the 3rd source/drain electrode, and
Described second and the 4th source/drain electrode be electrically connected to each other, make identical voltage be applied to described second and the 4th source/drain electrode.
14. thin-film transistor according to claim 12, the source in source/drain electrode layer in wherein said second active area and described first active area/drain electrode layer rotation symmetry.
15. thin-film transistor according to claim 14, wherein:
In described first to fourth source/drain electrode one overlap with described first grid electrode; And
In described first to fourth source/drain electrode another and described second gate electrode are overlapped.
16. thin-film transistor according to claim 12, wherein said first grid electrode with the overlapping width of described second active layer than described first grid electrode little with the overlapping width of described first active area.
17. thin-film transistor according to claim 12, wherein said active area further comprise and described first grid electrode and described second gate electrode between the offset electrodes of region overlapping, described offset electrodes and the insulation of described active layer.
18. thin-film transistor according to claim 17, wherein said offset electrodes comprises:
And first offset electrodes of the region overlapping between described first and second sources/drain electrode, described first offset electrodes and the insulation of described first active layer, and
And second offset electrodes of the region overlapping between described third and fourth source/drain electrode, described second offset electrodes and the insulation of described second active layer.
19. thin-film transistor according to claim 17, wherein:
Described first and the 3rd source/drain electrode be electrically connected to each other, make identical voltage be applied to described first and the 3rd source/drain electrode, and
Described second and the 4th source/drain electrode be electrically connected to each other, make identical voltage be applied to described second and the 4th source/drain electrode.
20. thin-film transistor according to claim 17, wherein said offset electrodes are electrically connected to described first grid electrode and described second gate electrode.
21. thin-film transistor according to claim 12, wherein said first active area and described second active area are insulated from each other.
22. a thin-film transistor comprises the active area that is divided into first active area, second active area and the 3rd active area, described active area comprises:
Gate electrode;
Active layer, comprise first active layer corresponding, second active layer corresponding with described second active area with described first active area, with three active layer corresponding with described the 3rd active area, described first active layer, described second active layer and described the 3rd active layer and described gate electrode;
Gate insulation layer is between described gate electrode and described active layer; And
Source/drain electrode layer, comprise first source/drain electrode and the second source/drain electrode that is electrically connected to described first active layer, the 3rd source/drain electrode that is electrically connected to described second active layer and the 4th source/drain electrode, and the 5th source/drain electrode and the 6th source/drain electrode that are electrically connected to described the 3rd active layer, wherein:
Two source/drain electrodes and the described gate electrode selected from described first to fourth source/drain electrode are overlapped,
Two source/drain electrodes of in described first to fourth source/drain electrode other are offset from described gate electrode, and
Described first to the 6th source/drain electrode and described gate electrode be arranged symmetrically.
23. thin-film transistor according to claim 22, wherein:
Described first, the 3rd and the 5th source/drain electrode be electrically connected to each other, make identical voltage be applied to described first, the 3rd and the 5th source/drain electrode, and
Described second, the 4th and the 6th source/drain electrode be electrically connected to each other, make identical voltage be applied to described second, the 4th and the 6th source/drain electrode.
24. thin-film transistor according to claim 22, the source/drain electrode layer symmetry in source/drain electrode layer in wherein said the 3rd active area and described first active area.
25. thin-film transistor according to claim 22, wherein:
Described first source/drain electrode and described second source/drain electrode and described gate electrode are overlapped, and
Described the 3rd source/drain electrode and described the 4th source/drain electrode are offset from described gate electrode.
26. thin-film transistor according to claim 22, wherein:
Described first active layer comprises first source corresponding with described first source/drain electrode/drain region, the second source/drain region corresponding with described second source/drain electrode, and first channel region between described first source/drain region and described second source/drain region,
Described second active layer comprises three source corresponding with described the 3rd source/drain electrode/drain region, the four source/drain region corresponding with described the 4th source/drain electrode, and second channel region between described the 3rd source/drain region and described the 4th source/drain region, and
Described the 3rd active layer comprises five source corresponding with described the 5th source/drain electrode/drain region, the six source/drain region corresponding with described the 6th source/drain electrode, and the triple channel district between described the 5th source/drain region and described the 6th source/drain region.
27. thin-film transistor according to claim 26, wherein said second channel region comprise not with described gate electrode, described the 3rd source/drain electrode and described the 4th source/drain electrode in any overlapping deviate region.
28. thin-film transistor according to claim 27, source/drain electrode layer in the source/drain electrode layer in wherein said first active area, described second active area and the source/drain electrode layer in described the 3rd active area are along the symmetry axis symmetry.
29. thin-film transistor according to claim 22, wherein said gate electrode with the overlapping width of described second active layer than described gate electrode little with the overlapping width of the described first and the 3rd active area.
30. thin-film transistor according to claim 22, wherein said first to the 3rd active area is insulated from each other.
31. a thin-film transistor comprises the active area that is divided into first active area, second active area, the 3rd active area and having ideals, morality, culture, and discipline source region, described active area comprises:
Gate electrode;
Active layer, comprise first active layer corresponding with described first active area, with corresponding second active layer of described second active area, with corresponding the 3rd active layer of described the 3rd active area and four active layer corresponding, described first active layer, described second active layer, described the 3rd active layer and described the 4th active layer and described gate electrode with described having ideals, morality, culture, and discipline source region;
Gate insulation layer is between described gate electrode and described active layer; And
Source/drain electrode layer, comprise first source/drain electrode and the second source/drain electrode that is electrically connected to described first active layer, the 3rd source/drain electrode that is electrically connected to described second active layer and the 4th source/drain electrode, the 5th source/drain electrode that is electrically connected to described the 3rd active layer and the 6th source/drain electrode, and the 7th source/drain electrode and the 8th source/drain electrode that are electrically connected to described the 4th active layer, wherein:
Overlap from the described the 3rd two source/drain electrodes and the described gate electrode of selecting to the 6th source/drain electrode,
The described the 3rd other two source/drain electrodes to the 6th source/drain electrode are offset from described gate electrode, and
Described first to the 8th source/drain electrode and described gate electrode be arranged symmetrically.
32. thin-film transistor according to claim 31, wherein:
Described first, the 3rd, the 5th and the 7th source/drain electrode be electrically connected to each other, make identical voltage be applied to described first, the 3rd, the 5th and the 7th source/drain electrode, and
Described second, the 4th, the 6th and the 8th source/drain electrode be electrically connected to each other, make identical voltage be applied to described second, the 4th, the 6th and the 8th source/drain electrode.
33. thin-film transistor according to claim 31, wherein:
Described first active layer comprises first source corresponding with described first source/drain electrode/drain region, the second source/drain region corresponding with described second source/drain electrode, and first channel region between described first source/drain region and described second source/drain region,
Described second active layer comprises three source corresponding with described the 3rd source/drain electrode/drain region, the four source/drain region corresponding with described the 4th source/drain electrode, and second channel region between described the 3rd source/drain region and described the 4th source/drain region,
Described the 3rd active layer comprises five source corresponding with described the 5th source/drain electrode/drain region, the six source/drain region corresponding with described the 6th source/drain electrode, and the triple channel district between described the 5th source/drain region and described the 6th source/drain region, and
Described the 4th active layer comprises seven source corresponding with described the 7th source/drain electrode/drain region, the eight source/drain region corresponding with described the 8th source/drain electrode, and the 4th channel region between described the 7th source/drain region and described the 8th source/drain region.
34. thin-film transistor according to claim 33, wherein:
Described second channel region comprise not with described gate electrode, described the 3rd source/drain electrode and described the 4th source/drain electrode in any first overlapping deviate region, and
Described triple channel district comprise not with described gate electrode, described the 5th source/drain electrode and described the 6th source/drain electrode in any second overlapping deviate region.
35. thin-film transistor according to claim 34, wherein:
Source in source/drain electrode layer in described the 3rd active area and described second active area/drain electrode layer rotation symmetry, and
Source/drain electrode layer symmetry in source/drain electrode layer in the described having ideals, morality, culture, and discipline source region and described first active area.
36. thin-film transistor according to claim 35, wherein said first source/drain electrode and described second source/drain electrode and described gate electrode are overlapped.
37. thin-film transistor according to claim 35, wherein:
One and described gate electrode in described the 3rd source/drain electrode and described the 4th source/drain electrode, and
In described the 3rd source/drain electrode and described the 4th source/drain electrode another is offset from described gate electrode.
38. thin-film transistor according to claim 31, wherein said gate electrode with the overlapping width of the described second and the 3rd active area than described gate electrode with described first and the overlapping width in having ideals, morality, culture, and discipline source region little.
39. thin-film transistor according to claim 31, wherein said first to fourth active area is insulated from each other.
40. a thin-film transistor includes the source region, described active area comprises:
Gate electrode comprises the first grid electrode parallel to each other and second gate electrode;
Active layer is with described first grid electrode and described second gate electrode;
Gate insulation layer is between described gate electrode and described active layer; And
Source/drain electrode layer comprises the first source/drain electrode and the second source/drain electrode that are electrically connected to described active layer, wherein:
Described first source/drain electrode and described first grid electrode are overlapped,
Described second source/drain electrode and described second gate electrode are overlapped, and
Described first and second sources/drain electrode and described gate electrode are arranged symmetrically.
41. according to the described thin-film transistor of claim 40, wherein said active area further comprise and described first grid electrode and described second gate electrode between the offset electrodes of region overlapping, described offset electrodes and the insulation of described active layer.
42. according to the described thin-film transistor of claim 41, wherein said offset electrodes is electrically connected to described first grid electrode and described second gate electrode.
43. according to the described thin-film transistor of claim 40, wherein said active layer comprises first source corresponding with described first source/drain electrode/drain region, the second source/drain region corresponding with described second source/drain electrode, and the channel region between described first source/drain region and described second source/drain region.
44. according to the described thin-film transistor of claim 43, wherein said channel region comprise not with described first grid electrode, described second gate electrode, described first source/drain electrode and described second source/drain electrode in any overlapping deviate region.
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