KR100494038B1 - High voltage thin film transistor having a offset in verticle direction - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage amorphous thin film transistor having a vertical offset to withstand high voltage. A source / drain electrode formed on the doped amorphous silicon layer and the entire structure to improve contact characteristics, and the offset of the amorphous silicon layer formed perpendicularly between the edge region of the active layer channel and the source and / or drain electrode. It provides a high voltage amorphous thin film transistor having.

Through this configuration, the problem of the strict process constraints of the high voltage amorphous thin film transistor having the horizontal offset is solved, the offset is easily controlled in the process, the characteristics of the high voltage thin film transistor are stabilized, and the process cost is low. To secure it.

Description

HIGH VOLTAGE THIN FILM TRANSISTOR HAVING A OFFSET IN VERTICLE DIRECTION}

The present invention relates to a high voltage amorphous thin film transistor, and more particularly to a high voltage amorphous thin film transistor having a vertical offset to withstand high voltage.

A high voltage amorphous thin film transistor is an element applied to a display requiring a high voltage such as an active matrix field emission display (AMFED), and a high voltage of 50 to 100V is generally applied.

Hereinafter, an AMFED high voltage amorphous thin film transistor having a horizontal offset according to the related art will be described with reference to FIG. 1.

The amorphous film transistor includes a substrate 101 for forming a device, a gate electrode 102, a gate insulating film 103, an active layer 104, an n + amorphous silicon 105, and a source / drain electrode 106. . In this case, after the gate electrode 102 is formed, the gate insulating film 103, the active layer 104 and the n + amorphous silicon 105 are deposited in a continuous process, and the active layer 104 and the n + amorphous silicon 105 are patterned. After that, the source / drain electrodes 106 are formed. Thereafter, a protective film 107 is formed on this entire structure. In addition, the field emission material 108 is formed.

At this time, as shown in FIG. 1, there is no overlapping region in the portion corresponding to the drain electrode among the gate electrode 102 and the source / drain electrode 106, and there is an overlapping region in the portion corresponding to the source electrode. If there is no overlapping area, space charge limited current occurs in this area. That is, in this region, when the low voltage is applied, the resistance becomes small and a large amount of current flows. When the high voltage is applied, the resistance becomes small and the current hardly flows. Therefore, using such a characteristic is particularly useful when applying a high voltage to the drain electrode.

However, in the AMFED high voltage amorphous thin film transistor having a horizontal offset according to the prior art as shown in FIG. 1, the portion between the gate and drain electrodes, which is a region where the space limited current phenomenon occurs, is determined by the alignment of the photolithography process. It is a structure that can only be used. That is, even if the same voltage is applied, when the length of the region is changed, the magnitude of the applied electric field is also changed. To reduce these differences, the process must be tightly controlled.

Accordingly, the AMFED high voltage amorphous thin film transistor having a horizontal offset for the prior art has a problem of strict process constraints.

In order to solve the above problems, an object of the present invention is to easily control the offset in the high voltage thin film transistor in the process, to stabilize the characteristics of the high voltage thin film transistor, to ensure a low process cost.

As a means for solving the above problems, an aspect of the present invention is to improve the contact characteristics of the gate electrode, the gate insulating film formed on the gate electrode, the active layer formed on a predetermined portion on the gate insulating film, the source and drain electrodes on the active layer A high voltage amorphous having a doped amorphous silicon layer and a source / drain electrode formed on the entire structure, the offset of the amorphous silicon layer formed perpendicularly between the edge region of the active layer channel and the source and / or drain electrode. Provides a thin film transistor.

Further, another aspect of the present invention is to form a gate electrode on a substrate, to form a gate insulating film on the gate electrode, to form and pattern a semiconductor layer on the gate insulating film to form an active layer on a predetermined portion, on the active layer Forming an amorphous silicon layer and a source / drain electrode formed over the entire structure, in order to improve contact characteristics with the source / drain electrodes, in a vertical direction between the edge region of the active layer channel and the source and / or drain electrodes. A method of manufacturing a high voltage amorphous thin film transistor having an offset of an amorphous silicon layer formed thereon is provided.

Preferably, the thickness of the offset may have a thickness of 1000 to 3000 mm 3.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)

Referring to FIG. 2, a high voltage thin film transistor includes a gate electrode 202, a gate insulating film 203, an active layer 204, an n + amorphous silicon layer 205, an etch stopper 206, and a space limited current on a substrate 201. An undoped amorphous silicon layer 207, an n + amorphous silicon layer 208, a source / drain electrode 209 for generating a phenomenon, a protective film 210 composed of a nitride film or a polymer for protecting the device, and a field emission material ( 211).

The substrate 201 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, or the like, and the gate electrode 202 may be formed of a metal film by LPCVD, PECVD, sputtering, or the like, and has a thickness of, for example, 1000 to 2000 μs. Is formed.

The gate insulating film 203 is formed using a silicon oxide film or a silicon nitride film, and is formed to have a thickness of, for example, 500 to 2000 GPa.

The active layer 204 and the n + amorphous silicon layer 205 can be sequentially deposited in a continuous process using a PECVD method, and the etch stopper 206 is formed of, for example, a silicon nitride film to etch to form the active layer 204. It functions as a protective film.

The undoped amorphous silicon layer 207 is formed to 1 μm or less, and preferably forms an offset in the vertical direction at a thickness of 3000 to 5000 mm 3. In FIG. 2, an amorphous silicon layer 207 is formed on both the source electrode and the drain electrode, but such an offset may be formed on the source electrode and / or the drain electrode.

The amorphous silicon layer 207 can adjust the space charge current phenomenon according to the deposition thickness thereof. Therefore, compared to the photolithography alignment process, this phenomenon can be controlled by the deposition thickness, so that much more precise adjustment is possible and a highly reproducible process can be secured. This is because misalignment of the photolithography process can occur up to several micrometers. On the other hand, the amorphous silicon layer 207 has a structure that completely covers the n + amorphous silicon layer 205. That is, in order to perform the function of offset, the amorphous silicon layer 207 may be spatially separated from each other so that the n + amorphous silicon layer 205 and the n + amorphous silicon layer 208 are not connected to each other. Only one of the source electrode and the drain electrode may be spatially separated from the other electrode, and the other electrode may have a structure capable of contacting it (see the fourth embodiment).

An n + amorphous silicon layer 208 and a source / drain electrode 209 are formed on the undoped amorphous silicon layer 207. In addition, the protective film 210 is formed in this whole structure, for example in thickness of 2000-8000 micrometers.

The field emission material 211 preferably uses a material having a small work function and a sharp geometry, and thus may form a high electric field, and may use carbon nanotubes or the like.

Hereinafter, the operation of the high voltage amorphous silicon thin film transistor according to the first embodiment will be described.

When the gate voltage is applied above the threshold voltage, the electronic layer is formed on the active layer 204 by inversion phenomenon. At this time, when the drain voltage is applied to about 50 to 100V, an electric field is formed between the n + amorphous silicon layer 208 and the n + amorphous silicon layer 205. In this case, a condition in which a space charge current may flow in the amorphous silicon layer 207 that is not doped by the formed electric field may be satisfied. In this situation, current flows through the drain electrode and the n + amorphous silicon layer 208, passes through the undoped amorphous silicon layer 207, and flows through the n + amorphous silicon layer 205 to the inversion layer. Current passing through the inversion layer flows toward the source electrode in the opposite direction.

Next, a manufacturing process of the high voltage thin film transistor according to the first embodiment will be described in detail with reference to FIG. 1.

First, after the gate electrode 202 is formed on the transparent substrate 201, the silicon oxide film 203, the active layer 204, and the n + amorphous silicon layer 205 are sequentially deposited in this order. Thereafter, the n + amorphous silicon layer 205 is patterned, and an etch stopper 206 is formed to serve as an etch stopper film in the post-stage process. An n + amorphous silicon layer 205 is deposited to reduce contact resistance with the active layer 204.

Next, an amorphous silicon layer 207 is formed. As described above, the amorphous silicon layer 207 functions as an offset. This thickness may vary depending on the voltage applied (eg, 20-100V). Thereafter, an n + amorphous silicon layer 208 and a source / drain electrode 209 are formed, and the etch stopper 206 is used as an etch stop layer for the channel to remove the upper portion of the active layer, and a protective film on the entire structure thereon. 210). Finally, the field emission material 211 is formed.

(Second embodiment)

Referring to FIG. 3, a high voltage thin film transistor includes a gate electrode 302, a gate insulating film 303, an active layer 304, an n + amorphous silicon layer 305, a source / drain electrode 306, a device on a substrate 301. It comprises a protective film 307 and a field emission material 308 made of a nitride film or a polymer for protecting the.

Referring to the difference from the first embodiment, the first embodiment shows that the amorphous silicon layer (207 in FIG. 2) serves as an offset, whereas the second embodiment shows that the active layer 304 has a channel role and offset. Will play a role together. In addition, in the second embodiment, unlike the first embodiment, the structure does not employ an etch stopper. Therefore, the detailed description of the second embodiment will be described based on differences from the first embodiment for the convenience of description.

In this case, there is no distinction between the region where the space charge limit current is formed and the region where the charge layer is formed by the gate voltage. Therefore, as the gate voltage is applied, a high voltage is applied to the drain region between the formed channel region and the n + doped region, thereby generating a space charge current.

The manufacturing of the high voltage thin film transistor according to the second embodiment has an advantage in that the number of processes can be greatly reduced and simplified. However, since the length of the channel is determined by the etching of the channel backside, it is necessary to precisely control this etching process.

Next, a manufacturing process of the high voltage thin film transistor according to the second embodiment will be described in detail with reference to FIG. 3.

First, after the gate electrode 302 is formed on the transparent substrate 301, the silicon dioxide film 303, the active layer 304, and the n + amorphous silicon layer 305 are successively deposited. Thereafter, the n + amorphous silicon layer 305 and the active layer 304 are patterned to form a source / drain electrode 306. Using the source / drain electrodes 306 as a mask, the n + amorphous silicon layer 305 and the active layer 304 in the upper portion of the channel formation region are back etched. A protective film 307 is formed over the entire structure. do. Finally, the field emission material 308 is formed.

 (Third embodiment)

Referring to FIG. 4, a high voltage thin film transistor includes a gate electrode 402, a gate insulating film 403, an active layer 404, an n + amorphous silicon layer 405, an etch stopper 406, and a space limited current on a substrate 401. An undoped amorphous silicon layer 407 for generating a phenomenon, a source / drain electrode 408, a protective film 409 made of a nitride film or a polymer for protecting the device, and a field emission material 410.

In this structure, there is no n + amorphous silicon layer (reference numeral 208 in Fig. 2) between the source / drain electrode 408 and the amorphous silicon layer 407 serving as an offset as compared with the first embodiment. That is, the n + amorphous silicon layer (reference numeral 208 of FIG. 2) is introduced to reduce contact resistance, and has an effect of preventing leakage current due to the flow of holes. However, since this function can be performed to some extent in the n + amorphous silicon layer 405, the third embodiment can take the structure of eliminating this layer. That is, if the source / drain electrode 408 allows the injection of electrons, the n + amorphous silicon layer (reference numeral 208 of FIG. 2), which is an n + doping layer, may be omitted.

(Example 4)

 Referring to FIG. 5, a high voltage thin film transistor includes a gate electrode 502, a gate insulating film 503, an active layer 504, an n + amorphous silicon layer 505, an etch stopper 506, and a space limited current on a substrate 501. An undoped amorphous silicon layer 507, an n + amorphous silicon layer 508, a source / drain electrode 509, a protective film 510 composed of a nitride film or a polymer for protecting the device, and a field emission material 511).

Compared with the first embodiment, the amorphous silicon layer 507 has a structure covering only the n + amorphous silicon layer 505 located below either of the source or drain electrodes. That is, in the first embodiment, both of the amorphous silicon layer 507 are formed so that the n + amorphous silicon layer (205 in FIG. 2) and the n + amorphous silicon layer (208 in FIG. 2) are not connected to each other in order to perform the function of offset. Take a structure that can be separated spatially. However, in the fourth exemplary embodiment, only a lower portion of one of the source electrode and the drain electrode is spatially separated from each other, and the other electrode has a structure capable of contacting it.

This is because in the actual implementation of the present invention, it may not be necessary to form an offset in both the source electrode and the drain electrode, and in this case, the fourth embodiment can be appropriately applied. In fact, in the case where the offset is taken only on one side compared to the first embodiment where both are offset, the fourth embodiment will show a higher value in terms of the total current.

Through the above-described configuration, the offset of the high voltage thin film transistor can be easily controlled in the process, thereby stabilizing the characteristics of the high voltage thin film transistor, and securing an inexpensive process cost.

1 is a diagram illustrating a high voltage amorphous thin film transistor having a horizontal offset according to the prior art.

2 to 5 are diagrams illustrating a high voltage thin film transistor having a vertical offset according to exemplary embodiments of the present invention.

* Brief description of the main parts of the drawing

101, 201, 301, 401, 501: substrate

102, 202, 302, 402, 502: gate electrode

103, 203, 303, 403, 503: gate insulating film

104, 204, 304, 404, 504: active layer

105, 205, 305, 405, 505: n + amorphous silicon layer

Claims (10)

delete A gate electrode; A gate insulating film formed on the gate electrode; An amorphous silicon active layer formed on a predetermined portion on the gate insulating film; A doped amorphous silicon layer on the active layer to improve contact characteristics with a source / drain electrode; And A source / drain electrode formed on the entire structure, Having an offset of an amorphous silicon layer formed in a vertical direction between an edge region of the active layer channel and the source and / or drain electrode, And the offset and the active layer are the same layer, and the offset is performed such that the thickness of the channel edge region of the active layer is thicker than the thickness of the channel region of the active layer. A gate electrode; A gate insulating film formed on the gate electrode; An active layer of amorphous silicon formed at a predetermined portion on the gate insulating film; A first doped amorphous silicon layer on the active layer to improve contact characteristics with a source / drain electrode; And A source / drain electrode formed on the entire structure, Having an offset of an amorphous silicon layer formed in a vertical direction between an edge region of the active layer channel and the source and / or drain electrode, Further comprising an offset of a second doped amorphous silicon layer and an amorphous silicon layer between an edge region of the active layer channel and the source and / or drain electrode, And the offset is configured to completely cover the doped amorphous silicon layer under at least one of the drain electrode and the source electrode. The high voltage thin film transistor of claim 3, further comprising an etch stopper, which is an etch stop layer, on the channel of the active layer. The high voltage thin film transistor according to any one of claims 2 to 4, wherein the offset has a thickness of 1000 to 3000 kV. delete Forming a gate electrode on the substrate; Forming a gate insulating film on the gate electrode; Forming and patterning an amorphous silicon layer on the gate insulating layer to form an active layer on a predetermined portion; Forming a doped amorphous silicon layer on the active layer to improve contact characteristics with a source / drain electrode; And A source / drain electrode formed on the entire structure, Having an offset of an amorphous silicon layer formed in a vertical direction between an edge region of the active layer channel and the source and / or drain electrode, And the offset and the active layer are the same layer, and the offset is formed such that the thickness of the channel edge region of the active layer is thicker than the thickness of the channel region of the active layer. Forming a gate electrode on the substrate; Forming a gate insulating film on the gate electrode; Forming and patterning an amorphous silicon layer on the gate insulating layer to form an active layer on a predetermined portion; Forming a first doped amorphous silicon layer on the active layer to improve contact characteristics with a source / drain electrode; And A source / drain electrode formed on the entire structure, Having an offset of an amorphous silicon layer formed in a vertical direction between an edge region of the active layer channel and the source and / or drain electrode, Forming an offset of a second doped amorphous silicon layer and an amorphous silicon layer between an edge region of the active layer channel and the source and / or drain electrode, wherein the offset is one of the drain electrode and the source electrode. A method of manufacturing a high voltage thin film transistor, characterized in that to form a structure completely covering the doped amorphous silicon layer at least one lower portion. The method of claim 8, further comprising forming an etch stopper, which is an etch stop layer, on the channel of the active layer. The method of manufacturing a high voltage thin film transistor according to any one of claims 7 to 9, wherein the offset has a thickness of 1000 to 3000 mW.