CN102270636A - Thin film transistor array substrate and manufacturing method thereof - Google Patents
Thin film transistor array substrate and manufacturing method thereof Download PDFInfo
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- CN102270636A CN102270636A CN2010101918173A CN201010191817A CN102270636A CN 102270636 A CN102270636 A CN 102270636A CN 2010101918173 A CN2010101918173 A CN 2010101918173A CN 201010191817 A CN201010191817 A CN 201010191817A CN 102270636 A CN102270636 A CN 102270636A
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Abstract
The invention relates to a thin film transistor array substrate, which comprises a substrate, a grid layer, a grid insulating layer, a source/ drain electrode layer, a patterning protection layer, an oxide semiconductor layer, a resin layer and a pixel electrode. The grid layer is arranged on the substrate; the grid insulating layer is arranged on the grid layer and the substrate. The source/ drain electrode layer is arranged on the grid insulating layer; the patterning protection layer is arranged on the source/ drain electrode layer and partial patterning protection layer is exposed; the oxide semiconductor layer is arranged on the patterning protection layer and is connected electrically with the source/ drain electrode layer; the resin layer is arranged on the oxide semiconductor layer and covers the oxide semiconductor layer; and the pixel electrode is arranged on the resin layer and is connected with source/ drain electrode layer. In addition, the invention also provides a method for manufacturing the thin film transistor array substrate. And the thin film transistor array substrate enables generation of a leakage current to be avoided.
Description
Technical field
The present invention relates to a kind of transistor (TFT) array substrate, and be particularly related to the manufacture method of a kind of thin-film transistor array base-plate and thin-film transistor array base-plate.
Background technology
The application of thin-film transistor array base-plate in display unit is day by day extensive, for example it can be applicable to liquid crystal indicator (Liquid Crystal Display, LCD), electrophoretic display apparatus (Electro-Phoretic Display, EPD) with organic LED display device (OrganicLight Emitting Diode Display, OLED).
Be example with using in LCD, a kind of existing thin-film transistor array base-plate comprises substrate, be formed at suprabasil metal gate layers, be formed at gate insulator on the metal gate layers, be formed at source on the gate insulator, be formed at amorphous phase indium gallium zinc oxide (a-IGZO) layer on the source, be formed at the protective layer on the a-IGZO layer and be formed at pixel electrode on the protective layer.
Yet in above-mentioned thin-film transistor array base-plate, protective layer is directly to be formed on the a-IGZO layer, because the material of protective layer is generally silicon dioxide, it has the problem that is easy to generate leakage current, therefore can influence the use of thin-film transistor array base-plate.
Therefore, how avoiding the generation of leakage current, is one of subject under discussion that personnel were paid attention to of association area with the serviceability that promotes thin-film transistor array base-plate in fact.
Summary of the invention
In view of this, the invention provides a kind of thin-film transistor array base-plate, it can avoid the generation of leakage current.
The present invention also provides a kind of manufacture method of thin-film transistor array base-plate, and the thin-film transistor array base-plate of its preparation can be avoided the generation of leakage current.
The present invention proposes a kind of thin-film transistor array base-plate, and it comprises substrate, grid layer, gate insulator, source, patterning protective layer, oxide semiconductor layer, resin bed and pixel electrode; Grid layer is arranged in the substrate; Gate insulator is arranged in grid layer and the substrate; Source is arranged on the gate insulator; The patterning protective layer is arranged on the source and exposes the part source; Oxide semiconductor layer is arranged on the patterning protective layer, and is electrically connected on source; Resin bed is arranged on the oxide semiconductor layer and the capping oxide semiconductor layer, and exposes this source of part; Pixel electrode is arranged on the resin bed and is connected to source.
The present invention also proposes a kind of manufacture method of thin-film transistor array base-plate, and it at first forms grid layer in substrate; Then, form gate insulator in grid layer and substrate; Then, form source on gate insulator; Then, form the patterning protective layer on source, and expose the part source; Then, form oxide semiconductor layer on the patterning protective layer, and be electrically connected on source; Then, form resin bed on oxide semiconductor layer and the capping oxide semiconductor layer, and expose this source of part; Then, form pixel electrode on resin bed and be connected to source.
The patterning protective layer of thin-film transistor array base-plate of the present invention is arranged on the source; and oxide semiconductor layer is arranged on the patterning protective layer; this can reduce even be avoided the generation of leakage current, thereby can improve the serviceability of thin-film transistor array base-plate.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Figure 1A is the profile of the thin-film transistor array base-plate of the embodiment of the invention.
Figure 1B is the profile of the thin-film transistor array base-plate of another embodiment of the present invention.
Fig. 2 A-2F is the technology generalized section of the thin-film transistor array base-plate shown in Figure 1A.
100,200: thin-film transistor array base-plate 10: substrate
11: grid layer 12: gate insulator
13: source 14,24: patterning protective layer
15: oxide semiconductor layer 16,26: resin bed
17,27: pixel electrode 18,28: thin-film transistor
19: wire jumper portion 20: pad parts
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to embodiment, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Figure 1A illustrates the profile into the thin-film transistor array base-plate of the embodiment of the invention.See also Figure 1A; thin-film transistor array base-plate 100 comprises thin-film transistor 18, and thin-film transistor 18 comprises substrate 10, grid layer 11, gate insulator 12, source 13, patterning protective layer 14, oxide semiconductor layer 15, resin bed 16 and pixel electrode 17.Wherein, grid layer 11 is arranged in the substrate 10; gate insulator 12 is arranged on substrate 10 and the grid layer 11; source 13 is arranged on the gate insulator 12; patterning protective layer 14 is arranged on the source 13 and exposes part source 13; oxide semiconductor layer 15 is arranged on the patterning protective layer 14 and is electrically connected on source 13; resin bed 16 is arranged on the oxide semiconductor layer 15 and capping oxide semiconductor layer 15; also expose part source 13, pixel electrode 17 is arranged on the resin bed 16 and is connected to source 13.Wherein, the material of oxide semiconductor layer 15 can be the amorphous oxides one of at least that comprises indium (In), gallium (Ga) and zinc (Zn), for example is amorphous phase indium gallium zinc oxide (a-IGZO).
In the present embodiment, thin-film transistor array base-plate 100 can be used for electrophoretic display apparatus (Electro-Phoretic Display, EPD), but the present invention is not as limit; By suitable structure modify, thin-film transistor array base-plate of the present invention also is used for other display unit.For example, see also Figure 1B, thin-film transistor array base-plate 200 is applied in liquid crystal indicator (Liquid CrystalDisplay; LCD) in; wherein in the thin-film transistor 28, it is directly to be arranged on the patterning protective layer 24 that partial pixel electrode 27 is arranged, and has saved part resin bed 26 therebetween.
In addition, in the present embodiment, thin-film transistor array base-plate 100 also comprises wire jumper portion 19 and pad parts 20, wire jumper portion 19 is connected between other parts of pad parts 20 and thin-film transistor array base-plate 100, and pad parts 20 is used for being electrically connected with outer member, for example is electrically connected with the external circuit board or control circuit.
Above-mentioned thin-film transistor array base-plate 100; by the structural arrangement between design source 13, patterning protective layer 14 and the oxide semiconductor layer 15; even also patterning protective layer 14 is arranged on the source 13; and oxide semiconductor layer 15 is arranged on the patterning protective layer 14; thereby can reduce even avoid the generation of leakage current, and then improve the serviceability of thin-film transistor array base-plate 100.Moreover, because wire jumper portion 19 and pad parts 20 save resin bed, therefore also can avoid the problem of chips incorporate (IC Bonding) difficulty and circuit corrosion.
Be described further below with reference to the manufacture method of accompanying drawing above-mentioned thin-film transistor array base-plate 100.
See also Fig. 2 A, the manufacture method of thin-film transistor array base-plate 100 is prior to forming grid layer 11 in the substrate 10, then form gate insulator 12 on substrate 10 and grid layer 11.Wherein, the formation method of grid layer 11 for example can deposit the layer of metal material earlier in substrate 10, adopts a Patternized technique to form grid layer 11 again.And the formation method of gate insulator 12 for example can comprise that (Chemical Vapor Deposition CVD), but is not limited thereto chemical vapour deposition technique.Specifically, in the present embodiment, the material of grid layer 11 can be metal, for example comprises one of aluminium, aluminium neodymium alloy, molybdenum, chromium, molybdenum evanohm and copper or its composition.The material of gate insulator 12 can comprise one of silicon nitride, silica, aluminium oxide and yittrium oxide or its composition.
See also Fig. 2 B, behind the formation gate insulator 12, then on gate insulator 12, form source 13.The formation method of source 13 for example can deposit the layer of metal material earlier, adopts a Patternized technique to form again.The material of source 13 can be metal, for example comprises one of aluminium, aluminium neodymium alloy, molybdenum, chromium, molybdenum evanohm and copper or its composition.
See also Fig. 2 C, after the formation source 13, then on source 13, form patterning protective layer 14.Patterning protective layer 14 exposes part source 13.The formation method of patterning protective layer 14 for example can comprise chemical vapour deposition technique, but is not limited thereto.Wherein, patterning protective layer 14 can comprise one of silicon nitride, silica, phenolic resins and polyimides or its composition.In addition, patterning protective layer 14 also can be the composite insulation layer of organic material and inorganic material.
See also Fig. 2 D, behind the formation patterning protective layer 14, then on patterning protective layer 14, form oxide semiconductor layer 15, and make the oxide semiconductor layer 15 of formation be electrically connected on source 13.The material of oxide semiconductor layer 15 can be the amorphous oxides one of at least that comprises indium (In), gallium (Ga) and zinc (Zn), for example is amorphous phase indium gallium zinc oxide (a-IGZO).In addition, the process conditions of formation oxide semiconductor layer 15 can comprise aerating oxygen and argon gas.
See also Fig. 2 E, behind the formation oxide semiconductor layer 15, then on oxide semiconductor layer 15, form resin bed 16.Resin bed 16 capping oxide semiconductor layers 15, and expose part source 13.Wherein, resin bed 16 can be positive and negative type photoresistance.
At last, see also Fig. 2 F, on resin bed 16, form pixel electrode 17, and make pixel electrode 17 be connected to source 13, thereby form thin-film transistor array base-plate 100.Wherein, the material of pixel electrode 17 can comprise one of indium tin oxide, indium-zinc oxide, molybdenum, chromium and molybdenum evanohm or its composition.
In sum; the patterning protective layer of thin-film transistor array base-plate of the present invention is arranged on the source; and oxide semiconductor layer is arranged on the patterning protective layer, and this can reduce even be avoided the generation of leakage current, thereby improves the serviceability of thin-film transistor array base-plate.Moreover the patterning protective layer is arranged on the source and oxide semiconductor layer is arranged at the patterning protective layer, also can avoid the problem of chips incorporate and circuit corrosion, thereby can further improve the serviceability of thin-film transistor array base-plate.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (10)
1. thin-film transistor array base-plate is characterized in that comprising:
A substrate;
One deck grid layer is arranged in this substrate;
One deck gate insulator is arranged in this grid layer and this substrate;
One deck source is arranged on this gate insulator;
One deck patterning protective layer, be arranged on this source and expose the part this source;
One deck oxide semiconductor layer is arranged on this patterning protective layer, and is electrically connected on this source;
One deck resin bed, be arranged on this oxide semiconductor layer and cover this oxide semiconductor layer and expose the part this source; And
A pixel electrode is arranged on this resin bed and is connected to this source.
2. thin-film transistor array base-plate as claimed in claim 1 is characterized in that: the material of this oxide semiconductor layer comprises the amorphous oxides one of at least of indium, gallium and zinc.
3. thin-film transistor array base-plate as claimed in claim 1 is characterized in that: the material of this oxide semiconductor layer comprises amorphous phase indium gallium zinc oxide.
4. thin-film transistor array base-plate as claimed in claim 1 is characterized in that: this resin bed is positive and negative type photoresistance.
5. thin-film transistor array base-plate as claimed in claim 1 is characterized in that: this pixel electrode of part directly is arranged on this patterning protective layer.
6. the manufacture method of a thin-film transistor array base-plate, it comprises:
Form one deck grid layer in a substrate;
Form one deck gate insulator in this grid layer and this substrate;
Form one deck source on this gate insulator;
Form one deck patterning protective layer on this source, and expose this source of part;
Form one deck oxide semiconductor layer on this patterning protective layer, and be electrically connected on this source;
Form one deck resin bed on this oxide semiconductor layer and cover this oxide semiconductor layer and expose this source of part; And
Form a pixel electrode on this resin bed and be connected to this source.
7. the manufacture method of thin-film transistor array base-plate as claimed in claim 6 is characterized in that: the material of this oxide semiconductor layer comprises the amorphous oxides one of at least of indium, gallium and zinc.
8. the manufacture method of thin-film transistor array base-plate as claimed in claim 6, it is characterized in that: the material of this oxide semiconductor layer comprises amorphous phase indium gallium zinc oxide.
9. the manufacture method of electric crystal array film substrate as claimed in claim 6, it is characterized in that: this resin bed is positive and negative type photoresistance.
10. the manufacture method of electric crystal array film substrate as claimed in claim 6, it is characterized in that: the process conditions that form this oxide semiconductor layer comprise aerating oxygen and argon gas.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010191817.3A CN102270636B (en) | 2010-06-04 | 2010-06-04 | Thin-film transistor array base-plate and manufacture method thereof |
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| CN201010191817.3A CN102270636B (en) | 2010-06-04 | 2010-06-04 | Thin-film transistor array base-plate and manufacture method thereof |
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| CN102270636A true CN102270636A (en) | 2011-12-07 |
| CN102270636B CN102270636B (en) | 2015-12-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014059713A1 (en) * | 2012-10-19 | 2014-04-24 | 深圳市华星光电技术有限公司 | Thin film transistor array manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6448463A (en) * | 1987-08-19 | 1989-02-22 | Matsushita Electric Ind Co Ltd | Method of driving amorphous silicon thin film transistor |
| US5898187A (en) * | 1995-09-12 | 1999-04-27 | Lg Electronics Inc. | Thin film transistor |
| CN101145561A (en) * | 2006-09-11 | 2008-03-19 | 北京京东方光电科技有限公司 | TFT matrix structure and making method thereof |
| US20090261332A1 (en) * | 2008-04-17 | 2009-10-22 | Samsung Electronics Co., Ltd. | Thin film transistor array panel, fabricating method thereof and flat panel display having the same |
-
2010
- 2010-06-04 CN CN201010191817.3A patent/CN102270636B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6448463A (en) * | 1987-08-19 | 1989-02-22 | Matsushita Electric Ind Co Ltd | Method of driving amorphous silicon thin film transistor |
| US5898187A (en) * | 1995-09-12 | 1999-04-27 | Lg Electronics Inc. | Thin film transistor |
| CN101145561A (en) * | 2006-09-11 | 2008-03-19 | 北京京东方光电科技有限公司 | TFT matrix structure and making method thereof |
| US20090261332A1 (en) * | 2008-04-17 | 2009-10-22 | Samsung Electronics Co., Ltd. | Thin film transistor array panel, fabricating method thereof and flat panel display having the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014059713A1 (en) * | 2012-10-19 | 2014-04-24 | 深圳市华星光电技术有限公司 | Thin film transistor array manufacturing method |
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| CN102270636B (en) | 2015-12-16 |
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