CN102263082A - Packaging substrate structure and manufacturing method - Google Patents
Packaging substrate structure and manufacturing method Download PDFInfo
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- CN102263082A CN102263082A CN2010101893284A CN201010189328A CN102263082A CN 102263082 A CN102263082 A CN 102263082A CN 2010101893284 A CN2010101893284 A CN 2010101893284A CN 201010189328 A CN201010189328 A CN 201010189328A CN 102263082 A CN102263082 A CN 102263082A
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- insulating barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention provides a packaging substrate structure and a manufacturing method. The packaging substrate structure comprises a substrate with a circuit layout, a laminar circuit structure arranged on the substrate, a first insulating layer, an interface layer, a plurality of first solder balls and a second insulating layer, wherein the laminar circuit structure has a plurality of ball placement pads; the first insulating layer is coated on the laminar circuit structure, and is substantially as high as the ball placement pads; the interface layer is arranged on the ball placement pads; the plurality of first solder balls are arranged on the interface layer on the ball placement pads; a cladding layer is covered on the first solder balls; the insulating layer is arranged about the first solder balls, and has a risen part which is risen along the lateral cambered surfaces of the first solder balls; and the risen part of the second insulating layer is lower than the first solder balls. The packaging substrate structure and the manufacturing method mainly have the advantages that: after a first previous insulating layer coating step, uniform to-be-printed surfaces with the same height can be provided; and the sizes of the ball placement pads can be accurately controlled by a patterning etching step.
Description
Technical field
The present invention relates to a kind of package substrate construction, particularly a kind of package substrate construction and manufacture method thereof with to be printed of homogeneous and contour tin ball.
Background technology
The development trend of electronic product little by little evolve for light, thin, short, little, at a high speed, high frequency and multi-functional field.In order to satisfy practical application request, semiconductor packaging has been the stacked structure of three-dimensional (3D) from ball grid array (ball grid array is called for short BGA) encapsulation and crystal covered carrier-board (flip chip is called for short FC) evolution gradually.Perhaps, in the encapsulation of support plate face, with FC technology or bonding wire (wire bond is called for short WB) technology various packaging body assemblings are engaged, to form a multi-functional structure.
In prior art, the implantation of solder ball array be by print solder paste on the board structure of finishing anti-layer (for example green lacquer) coating, then carry out reflow (reflow) step again.And the print solder paste step is to set up a printing stencil (steel plate) with patterning open loop on the surface with substrate to be printed, then utilize the tin cream on the scraper printing stencil to clamp-on in the patterning open loop, make to be positioned at open loop that tin cream is all inserted in upper and lower space, green lacquer surface.After taking off steel plate and carrying out the reflow step, the lip-deep tin cream fusion of green lacquer is an orbicule.When semiconductor chip board structure structure when dress therewith, the tin ball that the tin ball of this orbicule is corresponding with die terminals (or copper post) contacts, and after finishing the reflow step, is combined into electricity conductive construction.
In advanced person's semiconductor chip manufacturing technology, the design of chip has presented high density I/O contact, makes wire structures more intensive.Therefore, for base plate for packaging, welding conductive structure (projection) quantity of a side that contacts with chip also needs significantly to increase thereupon, causes the spacing between the conductive projection also nearer by healing.Yet, because of being subject to the spacing of steel plate open loop, add the out-of-flatness influence of green lacquer coat on the upper substrate, can cause the following tin amount instability of print solder paste step.As if the tin amount is too much down, then easily cause tin bridge phenomenon; If the tin amount is very few down, then cause the tin sphere volume too small, because of the coplanarity deficiency of conductive projection, make and can't electrically connect smoothly with chip.
Summary of the invention
Embodiments of the invention provide a kind of package substrate construction, comprise that one has the substrate of configuration; One build-up circuit structure is arranged on this substrate, and wherein this build-up circuit structure has a plurality of ball pads of planting; One first insulating barrier is coated on this build-up circuit structure, and roughly to plant the ball pad contour with those; One boundary layer is arranged at those and plants on the ball pad; A plurality of first tin balls are arranged on those boundary layers of planting the ball pad, cover a coating layer on those first tin balls; And one second insulating barrier be arranged at those first tin balls around, and have one and rise part and rise along the side cambered surface of those first tin balls; Wherein the rise of this second insulating barrier partly is lower than the height of those first tin balls.
Embodiments of the invention provide a kind of package substrate construction in addition, comprise that one has the substrate of configuration; One build-up circuit structure is arranged on this substrate, and wherein this build-up circuit structure has a plurality of ball pads of planting; One first insulating barrier is coated on this build-up circuit structure, and roughly to plant the ball pad contour with those; One boundary layer is arranged at those and plants on the ball pad; A plurality of first tin balls are arranged on those boundary layers of planting the ball pad, cover a coating layer on those first tin balls; One second insulating barrier be arranged at those first tin balls around, and have one and rise part and rise along the side cambered surface of those first tin balls; A plurality of second tin balls are arranged on the cambered surface zone, top of those first tin balls; And semiconductor chip subtend is arranged at this substrate, this semiconductor chip has the conduction contact of a plurality of columns, correspondence is also goed deep into those second tin balls, wherein fill glue between this semiconductor chip and this substrate, and wherein the rise of this second insulating barrier partly is lower than the height of those first tin balls.
Embodiments of the invention provide a kind of manufacture method of package substrate construction again, comprising: a substrate with configuration is provided; Form a build-up circuit structure on this substrate, wherein this build-up circuit structure has a plurality of ball pads of planting; Be coated with one first insulating barrier on this build-up circuit structure, roughly to plant the ball pad contour with those comprehensively; This first insulating barrier of patterning is to expose the surface that those plant the ball pad; Depositing a boundary layer plants on the ball pad in those; Implant a plurality of first tin balls and plant on the boundary layer of ball pad, on those first tin balls, cover a coating layer in those; And be coated with one second insulating barrier around those first tin balls, and have the side cambered surface rise of a rise part along those first tin balls, wherein the rise of this second insulating barrier partly is lower than the height of those first tin balls.
Major advantage of the present invention is through after the first previous insulating barrier application step, and homogeneous and contour to be printed can be provided.By the pattern etched step, can accurately control the size of planting the ball pad.Can directly influence bump pitch and size owing to plant the size of ball pad, therefore accurately the accuracy that the ball pad can promote printing or plant the tin sphere volume of ball is planted in control, reach the target (be lower than below the 150 μ m, or between 100 μ m to 140 μ m) of minuteness space.Compared to prior art, the first tin ball on the package substrate construction of the present invention contacts the coplanarity (coplanarity) that has than high-quality with the conduction of die terminals.Moreover, by providing one second tin ball on the first tin ball top cambered surface of exposing, thereby can provide enough welding volumes, to adapt to following tin ball height height/closely spaced product demand.What is more, because the rise bilge construction of second insulating barrier after the open loop is an indent circular arc, and the curve of this arc attaches for being docile and obedient the first tin ball, therefore can increase by the first tin ball and plant the adhesion of ball pad, obtains preferable reliability result.
For the present invention can be become apparent, embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
Description of drawings
Fig. 1-Fig. 8 shows the manufacture method according to the package substrate construction of one embodiment of the invention, in the generalized section in each processing step stage.
Fig. 9-Figure 10 shows the manufacture method of package substrate construction according to another embodiment of the present invention, in the generalized section in each processing step stage.
And the description of reference numerals in the above-mentioned accompanying drawing is as follows:
110～substrate;
120a, 120b～build-up circuit structure;
122～plant the ball pad;
130～the first insulating barriers;
135～boundary layer;
140～the first tin balls;
142,144～coat of metal;
145～the second tin balls;
150～the second insulating barriers;
Second insulating barrier after 150 '～open loop;
153～rise part;
210～semiconductor chip;
220～filling glue;
The contact of 230～column conduction.
Embodiment
Below describe and be accompanied by the example of description of drawings in detail with each embodiment, as reference frame of the present invention.In accompanying drawing or specification description, similar or identical part is all used identical figure number.And in the accompanying drawings, the shape of embodiment or thickness can enlarge, and to simplify or convenient the sign.Moreover the part of each element will be it should be noted that to describe explanation respectively in the accompanying drawing, the element that does not illustrate among the figure or describe, form known to those skilled in the art, in addition, only for disclosing the ad hoc fashion that the present invention uses, it is not in order to limit the present invention to certain embodiments.
In view of this, embodiments of the invention provide a kind of package substrate construction, and the zone between the circuit on the substrate is inserted with anti-weldering insulation material, form one contour to be printed, then carry out follow-up paste solder printing and reflow step.Because of only needing to form the projection of weld pad top, so only be the size and the height homogeneous of may command projection by the open loop on the steel plate.Moreover, can adjust the insulating barrier of thickness by being coated with one deck in addition, control the zone of exposing of projection.By constituting a new projection cube structure in conjunction with being coated with layer of cloth,, and the spacing between the projection cube structure is controlled at target below the 150 μ m with bump size and the height that reaches homogeneous.
Fig. 1-Fig. 8 shows the manufacture method according to the package substrate construction of one embodiment of the invention, in the generalized section in each processing step stage.See also Fig. 1, a substrate 110 with configuration at first is provided.Substrate 110 can be the single or multiple lift composite base plate.The material of substrate can comprise plastic cement, pottery, macromolecule or other composite materials that is fit to.Substrate 110 has formed or has been provided with the line construction of various kenels, for example metal connecting line, conductive plugs, conductive through hole (conductive through hole).Then, form build-up circuit structure 120a, 120b in the upper and lower surface of this substrate, wherein this build-up circuit structure has a plurality of ball pads 122 of planting.Will be appreciated that, the build-up circuit structure 120a of upper and lower layer, interlayer dielectric layer and the metal layer that 120b comprises multilayer, and by the electric connection of the conductive through hole in the substrate 110.In following embodiment, only focus on the description of the projection cube structure on the build-up circuit structure 120a on upper strata.
See also Fig. 2, be coated with one first insulating barrier 130 on this build-up circuit structure, roughly to plant ball pad 122 contour with those, again through open loop technologies such as plasma cleaning, laser drill or exposure imagings, makes those plant ball pad 122 and expose afterwards.In an embodiment, this first insulating barrier 130 can select to use general anti-layer (green lacquer) coating, but the thickness of coating is lower.In other embodiment, this first insulating barrier can be selected other dielectric materials for use, for example epoxy resin (epoxy resin), two Maleimide-triazine resin (bismaleimide triazine, BT), pi (polyimide), ABF film (ajinomotobuild-up film), polyphenylene oxide (poly phenylene oxide, PPE), polypropylene (polypropylene, PP), polytetrafluoroethylene (polytetrafluorethylene, PTFE) or methyl methacrylate (Polymethylmethacrylate, PMMA).The formation step of this first insulating barrier 130 comprises and is coated with one first insulating barrier comprehensively on this build-up circuit structure, makes above-mentionedly to plant the ball pad and this first insulating barrier has surface in the roughly same height.Then this first insulating barrier is carried out open loop step such as plasma cleaning, laser drill or exposure imaging, expose the surface that those plant the ball pad.For example, coating anti-welding layer (green lacquer) carries out image transfer (or laser drill, plasma cleaning) and plants open loop on the ball pad to finish those, only covers anti-layer in the circuit top, then optionally carries out follow-up surface treatment step.
Then, see also Fig. 3, form a boundary layer 135 and plant on the ball pad 122 in those.This boundary layer 135 can comprise coat of metal or bottom catalyzing metal layer, for example chemical nickel porpezite.In an embodiment, this boundary layer 135 can comprise: nickel, gold, tin, lead, aluminium, silver, chromium, tungsten, palladium, silicon, above-mentioned alloy or the combination in any of above-mentioned material.
See also Fig. 4, implant a plurality of first tin balls 140 and plant on the boundary layer 135 of ball pad in those.For example, can directly insert the first tin ball and plant on the ball pad, perhaps paste solder printing be planted on the ball pad in to be printed those,, form the binding tin ball structure of being desired through after the reflow process by the steel plate typography in those.Based on previous first insulating barrier, 130 application step of process, make those these first insulating barriers 130 of planting the peripheral region of ball pad 122 and vicinity have the surface of equal height in fact, therefore when carrying out the steel plate printing, can not be subjected to the influence of substrate, can reach tin amount homogeneous down, avoid the coplanarity defect of insufficient of tin bridge phenomenon and conductive projection.Then, optionally on the established first tin ball, plate an attached coating layer, as shown in Figure 5.This coating layer can be the above coat of metal 142,144 of one deck, and wherein ground floor is the bottom catalyzing metal layer.Will be appreciated that the material of coat of metal 142,144 can comprise: nickel, gold, tin, lead, aluminium, silver, chromium, tungsten, palladium, silicon, above-mentioned alloy or the combination in any of above-mentioned material.
See also Fig. 6, be coated with one second insulating barrier 150 (for example anti-weldering insulating barrier) on board structure.It should be noted that the compatibility of this first insulating barrier 130 on this second insulating barrier 150 and this peripheral region is better than the compatibility of the coating layer 144 on this second insulating barrier 150 and those first tin balls 140.Therefore, second insulating barrier 150 can be obviously greater than the thickness that covers on those first tin balls 140 at the thickness on this peripheral region.Then, carry out image transfer, plasma cleaning or laser drill to finish the open loop (or claiming secondary green lacquer open loop) on the first tin ball, make second insulating barrier 150 ' after the open loop have the side cambered surface rise of a rise part 153 along those first tin balls, and make the cambered surface zone, top that second insulating barrier 150 ' after this open loop exposes those first tin balls, as shown in Figure 7, the rise part 153 of second insulating barrier 150 ' after this open loop is lower than the height of those first tin balls.
See also Fig. 8, then, semiconductor chip 210 subtends are arranged at this board structure, and bestow pressure and the two is combined with temperature.This semiconductor chip 210 has the conduction contact 230 of a plurality of columns, and correspondence is also goed deep into those first tin balls 140, wherein fills glue 220 between this semiconductor chip and this substrate.
Fig. 9-Figure 10 shows the manufacture method of package substrate construction according to another embodiment of the present invention, in the generalized section in each processing step stage.See also Fig. 9, utilize above-mentioned package substrate construction shown in Figure 7, on the cambered surface zone, top of those first tin balls 140 that second insulating barrier 150 ' after this open loop is exposed, form a plurality of second tin balls 145.Those second tin balls 145 can utilize the mode of directly inserting to form, and plant the ball step by increasing secondary, to strengthen the effect of Chip Packaging.Then, see also Figure 10, semiconductor chip 210 subtends are arranged at this board structure, and bestow pressure and the two is combined with temperature.This semiconductor chip 210 has the conduction contact 230 of a plurality of columns, and correspondence is also goed deep into those second tin balls 145, wherein fills glue 220 between this semiconductor chip and this substrate.
Embodiment disclosed according to the present invention, its major advantage is through after previous first insulating barrier, 130 application step, and homogeneous and contour to be printed can be provided.By the pattern etched step, can accurately control the size of planting the ball pad.Can directly influence bump pitch and size owing to plant the size of ball pad, therefore accurately the accuracy that the ball pad can promote printing or plant the tin sphere volume of ball is planted in control, reach the target (be lower than below the 150 μ m, or between 100 μ m to 140 μ m) of minuteness space.Compared to prior art, the first tin ball 140 on the package substrate construction of the present invention contacts the coplanarity (coplanarity) that has than high-quality with the conduction of die terminals.Moreover, by providing one second tin ball 145 on the first tin ball, the 140 top cambered surfaces of exposing, thereby can provide enough welding volumes, to adapt to following tin ball height height/closely spaced product demand.What is more, because rise portion 153 structures of second insulating barrier 150 ' after the open loop are an indent circular arc, and the curve of this arc attaches for being docile and obedient the first tin ball 140, therefore can increase by the first tin ball and the adhesion of planting the ball pad, obtains preferable reliability result.
Though the present invention with preferred embodiment openly as above; yet it is not in order to limit scope of the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the scope that claim defined of enclosing.
Claims (17)
1. package substrate construction comprises:
One substrate has configuration on this substrate;
One build-up circuit structure is arranged on this substrate, and wherein this build-up circuit structure has a plurality of ball pads of planting;
One first insulating barrier is coated on this build-up circuit structure, and contour with described a plurality of ball pads of planting;
One boundary layer is arranged at described a plurality of planting on the ball pad;
A plurality of first tin balls are arranged on described a plurality of boundary layer of planting the ball pad, cover a coating layer on described a plurality of first tin balls; And
One second insulating barrier be arranged at described a plurality of first tin balls around, and have one and rise part and rise along the side cambered surface of described a plurality of first tin balls;
Wherein the rise of this second insulating barrier partly is lower than the height of described a plurality of first tin balls.
2. package substrate construction according to claim 1, comprise that also semiconductor chip subtend is arranged at this substrate, this semiconductor chip has the conduction contact of a plurality of columns, and correspondence is also goed deep into described a plurality of first tin ball, wherein fills glue between this semiconductor chip and this substrate.
3. package substrate construction according to claim 1, wherein this first insulating barrier is a dielectric material, comprises epoxy resin, two Maleimide-triazine resin, pi, ABF film, polyphenylene oxide, polypropylene, polytetrafluoroethylene or methyl methacrylate.
4. package substrate construction according to claim 1, wherein this boundary layer is a coat of metal, comprising: nickel, gold, tin, lead, aluminium, silver, chromium, tungsten, palladium, silicon, above-mentioned alloy or the combination in any of above-mentioned material.
5. package substrate construction according to claim 1, wherein this coating layer comprises one first coat of metal and one second coat of metal.
6. package substrate construction according to claim 1, wherein this second insulating barrier is an anti-weldering insulating barrier, comprises epoxy resin, two Maleimide-triazine resin, pi, ABF film, polyphenylene oxide, polypropylene, polytetrafluoroethylene or methyl methacrylate.
7. package substrate construction according to claim 1, wherein the compatibility of this second insulating barrier and this first insulating barrier is better than the compatibility of this coating layer on this second insulating barrier and the described a plurality of first tin ball.
8. package substrate construction according to claim 1, wherein this second insulating barrier exposes the cambered surface zone, top of described a plurality of first tin balls.
9. package substrate construction according to claim 1 also comprises:
A plurality of second tin balls are arranged on the cambered surface zone, top of described a plurality of first tin balls; And
Semiconductor chip subtend is arranged at this substrate, and this semiconductor chip has the conduction contact of a plurality of columns, and correspondence is also goed deep into described a plurality of second tin ball, wherein fills glue between this semiconductor chip and this substrate.
10. the manufacture method of a package substrate construction comprises:
One substrate with configuration is provided;
Form a build-up circuit structure on this substrate, wherein this build-up circuit structure has a plurality of ball pads of planting;
Be coated with one first insulating barrier on this build-up circuit structure comprehensively, and contour with described a plurality of ball pads of planting;
This first insulating barrier of patterning is to expose described a plurality of surface of planting the ball pad;
Deposit a boundary layer in described a plurality of planting on the ball pad;
Implant a plurality of first tin balls on described a plurality of boundary layers of planting the ball pad, on described a plurality of first tin balls, cover a coating layer; And
Be coated with one second insulating barrier around described a plurality of first tin balls, and have the side cambered surface rise of a rise part along described a plurality of first tin balls, wherein the rise of this second insulating barrier partly is lower than the height of described a plurality of first tin balls.
11. the manufacture method of package substrate construction according to claim 10, comprise that also subtend engages semiconductor chip and this substrate, this semiconductor chip has the conduction contact of a plurality of columns, correspondence is also goed deep into described a plurality of first tin ball, wherein fills glue between this semiconductor chip and this substrate.
12. the manufacture method of package substrate construction according to claim 10, wherein implant a plurality of first tin balls and comprise printing one tin cream on described a plurality of these boundary layers of planting the ball pad, and impose a reflow step and make tin cream form the tin ball in the step on described a plurality of these boundary layers of planting the ball pad.
13. the manufacture method of package substrate construction according to claim 10, wherein be coated with the step of one second insulating barrier around described a plurality of first tin balls and comprise this second insulating barrier of coating on this substrate, and impose steps such as image transfer, plasma cleaning or laser drill to expose the cambered surface zone, top of described a plurality of first tin balls.
14. the manufacture method of package substrate construction according to claim 13, wherein the compatibility of this second insulating barrier and this first insulating barrier is better than the compatibility of this coating layer on this second insulating barrier and the described a plurality of first tin ball.
15. the manufacture method of package substrate construction according to claim 13 also comprises:
Form a plurality of second tin balls on the cambered surface zone, top of described a plurality of first tin balls; And
Subtend is in conjunction with semiconductor chip and this substrate, and this semiconductor chip has the conduction contact of a plurality of columns, and correspondence is also goed deep into described a plurality of second tin ball, wherein fills glue between this semiconductor chip and this substrate.
16. the manufacture method of package substrate construction according to claim 10, wherein this first insulating barrier is a dielectric material, comprises epoxy resin, two Maleimide-triazine resin, pi, ABF film, polyphenylene oxide, polypropylene, polytetrafluoroethylene or methyl methacrylate.
17. the manufacture method of package substrate construction according to claim 10, wherein this second insulating barrier is an anti-weldering insulating barrier, comprises epoxy resin, two Maleimide-triazine resin, pi, ABF film, polyphenylene oxide, polypropylene, polytetrafluoroethylene or methyl methacrylate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010101893284A CN102263082A (en) | 2010-05-24 | 2010-05-24 | Packaging substrate structure and manufacturing method |
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| CN2010101893284A CN102263082A (en) | 2010-05-24 | 2010-05-24 | Packaging substrate structure and manufacturing method |
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| CN102263082A true CN102263082A (en) | 2011-11-30 |
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| CN2010101893284A Pending CN102263082A (en) | 2010-05-24 | 2010-05-24 | Packaging substrate structure and manufacturing method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108233178A (en) * | 2016-12-12 | 2018-06-29 | 联亚光电工业股份有限公司 | Semicondcutor laser unit |
| CN109712898A (en) * | 2018-12-10 | 2019-05-03 | 通富微电子股份有限公司 | A kind of packaging method and packaging |
| CN109279180B (en) * | 2017-07-21 | 2020-06-16 | 深圳市中科先见医疗科技有限公司 | Medical implant component with an encapsulation layer and method for encapsulating a medical implant component |
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| CN1738017A (en) * | 2004-08-17 | 2006-02-22 | 三星电子株式会社 | The electrode structure of semiconductor device and manufacture method thereof |
| CN101335214A (en) * | 2003-12-02 | 2008-12-31 | 全懋精密科技股份有限公司 | Semiconductor packing substrate for forming presoldering tin material and its preparation method |
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| CN1536631A (en) * | 2003-04-09 | 2004-10-13 | 全懋精密科技股份有限公司 | Electrically-connecting pad electroplated metal layer structrure of semiconductor package base plate and its making metod |
| CN101335214A (en) * | 2003-12-02 | 2008-12-31 | 全懋精密科技股份有限公司 | Semiconductor packing substrate for forming presoldering tin material and its preparation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108233178A (en) * | 2016-12-12 | 2018-06-29 | 联亚光电工业股份有限公司 | Semicondcutor laser unit |
| CN109279180B (en) * | 2017-07-21 | 2020-06-16 | 深圳市中科先见医疗科技有限公司 | Medical implant component with an encapsulation layer and method for encapsulating a medical implant component |
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Application publication date: 20111130 |