CN101335214A - Semiconductor packing substrate for forming presoldering tin material and its preparation method - Google Patents
Semiconductor packing substrate for forming presoldering tin material and its preparation method Download PDFInfo
- Publication number
- CN101335214A CN101335214A CN 200810134649 CN200810134649A CN101335214A CN 101335214 A CN101335214 A CN 101335214A CN 200810134649 CN200810134649 CN 200810134649 CN 200810134649 A CN200810134649 A CN 200810134649A CN 101335214 A CN101335214 A CN 101335214A
- Authority
- CN
- China
- Prior art keywords
- electric connection
- connection pad
- tin material
- packaging
- base plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
The invention relates to a semiconductor packaging base-plate used for forming pre-soldering tin material and a manufacturing method thereof. The invention mainly provides the packaging base-plate with at least one surface forming a plurality of electrically connected pads, and then a protective organic insulating layer is formed on the surface of the packaging base-plate, and thinned to expose the upper surfaces of the electrically connected pads of the protective organic insulating layer. Later, a conductive film and a resistance layer on the surfaces of the protective organic insulating layer and the electrically connected pads are formed in sequence; also, a plurality of openings are formed on the resistance layer to expose the conductive film on the electrically connected pads; and then an electroplating process is carried out to the packaging base-plate; the stenciling mode can also be directly utilized to deposit the pre-soldering tin material on the electrically connected pads. The invention can promote the bonding strength of the pre-soldering tin, and can avoid the problem of contrapositioning caused by the downsizing of electrically connected pads and the problem that the pre-soldering tin material is difficult to be deposited on the electrically connected pads.
Description
The present invention is that Chinese patent application number is 200310117149.X, and the applying date is the dividing an application of patent application on December 2nd, 2003.
Technical field
The invention relates to a kind of semiconductor packing substrate for forming presoldering tin material and method for making thereof, particularly can manifest on the conductor package substrate of electric connection pad, utilize plating or mould printing mode to form board structure of pre-solder bump and preparation method thereof about a kind of.
Background technology
Since IBM Corporation introduces chip package (Flip chip package) technology in early days in nineteen sixty, compare with routing (Wire bond) technology, the characteristics of Flip Chip are that the electric connection between semiconductor chip and substrate is by solder bump, rather than general gold thread.The advantage of this Flip Chip is to improve the size of packaging density and reduction package assembling.Simultaneously, this Flip Chip need not use long metal wire, so can improve the performance of electrical aspect.In view of this, industry is used high temperature scolding tin on ceramic substrate, and (Control-collapsechipconnection C4), has for many years the chip interconnection technique of promptly so-called control disintegration.In recent years, because high density, at a high speed and the increase of semiconductor subassembly demand cheaply, simultaneously in response to the diminishing trend of the volume of electronic product, to cover brilliant assembly and (for example be arranged at cheaply organic circuit board, printed circuit board (PCB) or substrate), and be filled in chip below with epoxy resin primer (Under fill resin), to reduce between silicon and the organic circuit plate structure, presented volatile growth because of the thermal stress that thermal dilation difference was produced.
In existing Flip Chip, dispose electrical electrode pad (Electrode pads) on the surface of semiconductor integrated circuit (IC) chip, organic circuit board also has corresponding electric connection pad, between this chip and circuit board solder bump or other conductive adhesive material can be set suitably.This chip is to be arranged on this circuit board in the ventricumbent mode of electrical contact, and its characteristics are that this solder bump or conductive adhesive material provide electrical I/O (I/O) and the mechanical connection between this chip and circuit board.
See also Figure 1A and Figure 1B, this is a kind of existing brilliant assembly that covers, as shown in FIG., several metal couplings 11 are formed on the electrode pad 12 of chip 13, and several are formed on the electric connection pad 15 of organic circuit board 16 by the made pre-solder bump 14 of scolder.Be enough to make under the reflow temperature condition of these pre-solder bump 14 fusions, by pre-solder bump 14 reflows to corresponding metal coupling 11 can be formed scolding tin knot 17.With regard to solder bump scolding tin knot (Solder bump joint), insert primer material 18 in the crack between can be further between this chip and this circuit board, with thermal expansion difference that suppresses 16 of this chip 13 and this circuit boards and the stress that reduces this scolding tin knot.
See also Fig. 2, this is a kind of existing organic circuit board 2 that is used for flip chip, this circuit board has electric connection pad 21, and the insulating barrier 22 of this organic circuit board 2 can be made by the organic material of organic material, combined filament or the organic material of mixed particle etc. (for example, epoxy resin, polyimides (Polyimide), span come acyl to come composite material of amine/triazine radical (Bismaleimide triazine-based) resin, cyanate (Cyanate ester) or its glass fibre (Glass fiber) etc.).This electric connection pad 21 is formed by metal material (for example, copper) typically.General metal barrier layer 23 is to comprise being formed on the nickel adhesion coating on this electric connection pad 21 and being formed on golden protective layer on the nickel adhesion coating.This barrier layer also can be by gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, palladium/gold or nickel/palladium/gold etc., by electroplating (Electroplating), non-chemically electroplating (Electroless plating) or physical vapour deposition (PVD) methods such as (Physical vapor deposition) and form.Apply organic insulating protective layer 24 afterwards on the surface of this circuit board 2, for example green lacquer etc. is formed on the circuit layer on this circuit board surface and insulation characterisitic is provided with protection.
As shown in Figure 2, this electric connection pad 21 is to expose in the insulating protective layer 24, and is formed with pre-solder bump 25 on this electric connection pad 21 and covers brilliant scolding tin knot for follow-up formation; And industry mainly is to deposit scolding tin to form pre-solder bump on this electric connection pad 21 by the mould printing technology at present, and wherein the more common template sheet material of this mould printing technology is steel plate.Yet, in practical operation, because communication now, the significantly growth of network and computer etc. various portable (Portable) product, can dwindle the IC area and have high density and the spherical grid array type of many pinizations characteristic (BGA), crystal covering type (Flip chip), chip size packages (CSP, Chip size package) with multi-chip module (MCM, Multi chip module) etc. packaging part day by day becomes the main flow on the encapsulation market, and normal and microprocessor, chipset, high-effect chip collocation such as drawing chip and ASIC is with performance calculation function more at a high speed.These structures certainly will be dwindled line width and electric connection pad size; when electric connection pad gap 26 continues reduction; because the existence of insulating protective layer 24 between this electric connection pad; electric connection pad 21 areas of part will be sheltered from; make expose outside this insulating protective layer 24 electric connection pad 21 sizes more shape dwindle; cause the contraposition of the pre-solder bump of follow-up formation to have problems; simultaneously also because of the shared space of this insulating protective layer 24 and the effect of altitude of its formation; template bore size in the mould printing technology certainly will be reduced thereupon; not only, the template die sinking improves because of being difficult for causing the manufacturing cost of this template; more be difficult to make pre-soldering tin material to pass, cause the bottleneck on the process technique because of the perforate pitch-row of this template is trickle.Moreover; because this insulating protective layer 24 shelters from electric connection pad 21 areas of part; and the space that it is shared and the effect of altitude of its formation; to cause the pre-soldering tin material use amount increase and the relative thickness of base plate for packaging to increase, cause the increase of processing procedure expense and compactization of unfavorable semiconductor device.In addition; form pre-scolding tin with plating mode in the open area of insulating protective layer 24 in addition; also the contact area that is formed on the electric connection pad because of pre-soldering tin material is restricted, and formed pre-scolding tin adhesion intensity is not good enough, fails reliability test by pre-scolding tin.
Therefore, in view of the above problems, how to avoid forming that aligning accuracy deficiency, the adhesion intensity of pre-soldering tin material is not good crosses problems such as low with mould printing technology process rate, effectively on an integrated circuit (IC) substrate package, form the structure of pre-scolding tin, become the problem of desiring most ardently solution at present in fact.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art; main purpose of the present invention is providing a kind of semiconductor packing substrate for forming presoldering tin material and method for making thereof; it is to be formed with on the conductor package substrate of a plurality of electric connection pads on a surface; cover an organic insulation protective layer; and carry out thinning with the complete upper surface that appears this electric connection pad, this electric connection pad is had than large tracts of land for forming pre-soldering tin material.
A further object of the present invention provides a kind of semiconductor packing substrate for forming presoldering tin material and method for making thereof, by increasing the contact area of electric connection pad with the pre-soldering tin material of deposition, helps promoting pre-scolding tin adhesion intensity.
Another object of the present invention provides a kind of semiconductor packing substrate for forming presoldering tin material and method for making thereof; can avoid existence because of insulating protective layer between electric connection pad; the electric connection pad size that exposes outside this insulating protective layer is dwindled; cause the generation of the contraposition problem of follow-up formation projection, be difficult for being deposited on the first-class problem of this electric connection pad with pre-soldering tin material.
For reaching above-mentioned and other purpose, a kind of semiconductor packing substrate for forming presoldering tin material method for making of the present invention, its key step comprises: provide at least one surface to be formed with the base plate for packaging of a plurality of electric connection pads; On this base plate for packaging surface, form organic insulating protective layer; And the thickness that grinds this organic insulation protective layer of thinning, make upper surface and each electric connection pad flush of this organic insulation protective layer, to manifest the upper surface of this electric connection pad.
Follow-uply can on the surface of this organic insulation protective layer and electric connection pad, form conducting film and resistance layer in regular turn, and make this resistance layer be formed with a plurality of perforates, to manifest the conducting film on this electric connection pad surface, then this base plate for packaging is carried out electroplating process, form pre-soldering tin material with the conducting film electroplating surface on this electric connection pad; Also or directly utilize mould printing (Stencilprinting) mode, the pre-soldering tin material of deposition on this electric connection pad, and can be by back welding process on this electric connection pad, to form pre-solder bump.
By above-mentioned processing procedure, also a kind of semiconductor packing substrate for forming presoldering tin material of the present invention, it mainly comprises: the semiconductor base plate for packaging, its at least one surface is formed with a plurality of electric connection pads; And an organic insulation protective layer, be formed in this base plate for packaging surface, and the upper surface flush of the upper surface of this organic protection insulating barrier and electric connection pad and fluid-tight engagement, with the complete upper surface that exposes this electric connection pad.Wherein the upper surface of this electric connection pad is to be formed with pre-soldering tin material for later use plating or mode of printing.
Existing method is to utilize to be formed with insulating protective layer on the surface of integrated circuit (IC) substrate package; just cover the part electric connection pad; make it produce adverse influence; the present invention makes the organic insulation protective layer manifest the electric connection pad upper surface; electric connection pad is had than large tracts of land for forming pre-soldering tin material; avoid causing taking integrated circuit and electric connection pad space and forming influence highly because of the formation of this insulating protective layer; the pre-soldering tin material use amount increase and the relative thickness of circuit package substrate are increased; cause the raising of processing procedure expense and compactization of unfavorable semiconductor device; can help promoting pre-scolding tin adhesion intensity by increasing the contact area of electric connection pad with the pre-soldering tin material of deposition.
Description of drawings
Figure 1A and Figure 1B show a kind of existing processing procedure generalized section of covering brilliant assembly;
Fig. 2 shows existing circuit board generalized section with insulating protective layer and pre-solder bump;
Fig. 3 A to Fig. 3 I shows semiconductor packing substrate for forming presoldering tin material method for making generalized section of the present invention;
Fig. 4 A to Fig. 4 E shows the generalized section of another example of semiconductor packing substrate for forming presoldering tin material method for making of the present invention;
Fig. 5 A and Fig. 5 B are presented at the structural profile schematic diagram of bond semiconductor chip on the conductor package substrate;
Fig. 6 A and Fig. 6 B are presented at the structural profile schematic diagram that engages the semiconductor chip with metal coupling on the conductor package substrate;
Fig. 7 A and Fig. 7 B are presented to engage simultaneously on the conductor package substrate to form and cover the structural profile schematic diagram that brilliant scolding tin is tied and plate is tied the scolding tin of plate; And
Fig. 8 shows the semiconductor package part structural profile schematic diagram that forms crystal covered package.
Embodiment
Embodiment
Below be conjunction with figs., describe semiconductor packing substrate for forming presoldering tin material and method for making embodiment thereof among the present invention in detail.What must note a bit is herein, these accompanying drawings are the schematic diagram of simplification, it only illustrates basic structure of the present invention in a schematic way, therefore it only shows the formation relevant with the present invention, and shown formation be not number when implementing, shape with reality, and dimension scale draw, number, shape and dimension scale during its actual enforcement is a kind of optionally design, and its formation arrangement form may be more complicated.
Shown in Fig. 3 A to Fig. 3 I, describe the embodiment generalized section of semiconductor packing substrate for forming presoldering tin material method for making of the present invention in detail.
See also Fig. 3 A, semiconductor base plate for packaging 3 at first is provided, the surface of this base plate for packaging 3 has been formed with a plurality of electric connection pads 32.Certainly this substrate surface also can be formed with a plurality of conducting wires 31 simultaneously for being connected with this electric connection pad 32.The process technique that forms electric connection pad and conducting wire about base plate for packaging is various, they be industry known process technique, so its non-this case technical characterstic is no longer repeat specification.
See also Fig. 3 B, then utilize modes such as printing, spin coating or applying on this is formed with base plate for packaging 3 surfaces of electric connection pad 32, form an organic insulation protective layer 33, this organic insulation protective layer can be to refuse welding flux layer, for example green lacquer.
See also Fig. 3 C; carry out the thickness of this organic insulation protective layer 33 of thinning; so as to manifesting the upper surface of this electric connection pad 32; it can be by technology such as grindings; remove this organic insulation protective layer 33 of part,, make the periphery fluid-tight engagement of this organic protection insulating barrier 33 and electric connection pad 32 to expose the upper surface of this electric connection pad 32; and the complete upper surface that manifests this electric connection pad 32, so promptly constitute semiconductor packing substrate for forming presoldering tin material of the present invention.
See also Fig. 3 D, when if this substrate surface is formed with electric connection pad 32 simultaneously with conducting wire 31, also utilize modes such as printing, spin coating or applying on these base plate for packaging 3 surfaces, be coated with a dielectric film 34, this dielectric film 34 can be the oxidation-resistant film of organic or inorganic, and utilize patterning process such as exposure, development, and make this dielectric film 34 cover this conducting wire 31, make the upper surface of this electric connection pad 32 be emerging in the surface of this base plate for packaging 3.If this base plate for packaging 3 is not formed with conducting wire 31 at outermost surface, promptly there is not the necessity (shown in Fig. 3 D ') that forms dielectric film 34 coverings.Certainly, this conducting wire 31 also can form dielectric film 34 and be covered (as Fig. 3 D " shown in), and in the pre-scolding tin processing procedure of follow-up plating, directly covers with resistance layer and also can.
See also Fig. 3 E, also can on these base plate for packaging 3 surfaces, form conducting film 35; This conducting film 35 is electroplated the required current conduction path of pre-scolding tin mainly as aftermentioned, it can be made of metal, alloy or deposit multilayer metal level, as is selected from any composition of copper, tin, nickel, chromium, titanium, copper-evanohm or group that tin-lead alloy constitutes.By physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating or chemical precipitation, for example sputter (Sputtering), evaporation (Evaporation), electric arc steam deposition (Arc vapor deposition), ion beam sputter (Ionbeams puttering), the molten diffusing deposition of laser (Laser ablation deposition) or electricity slurry promote the chemical vapour deposition (CVD) mode to be formed on this circuit board surface.Shown in Fig. 3 E, it is to overlay on the base plate for packaging that the surface has electric connection pad 32 and conducting wire 31 with conducting film 35, and this conducting wire 31 is in its surface coverage one deck dielectric film 34 to be arranged earlier.Shown in Fig. 3 E ', it is that promptly this substrate surface is not coated with dielectric film, but directly forms conducting film 35 on substrate surface when base plate for packaging 3 outermost surfaces when shape does not have the conducting wire.As for Fig. 3 E " shown in be conducting film 35 is directly overlayed on the base plate for packaging that the surface has electric connection pad 32 and conducting wire 31, and these 31 surfaces, conducting wire can be coated with one deck dielectric film 34.The following drawings, to have conducting wire and electric connection pad with this substrate surface, and being formed with a dielectric film (corresponding diagram 3E) on this conducting wire is illustrated for example, this substrate surface only has (the corresponding diagram 3E ') of electric connection pad relatively, and this substrate surface has conducting wire and electric connection pad, and be not formed with on this conducting wire a dielectric film (corresponding diagram 3E "), its fabrication steps is roughly the same, main difference only is to be formed with dielectric film 34 on the conducting wire of substrate surface.
See also Fig. 3 F, then patterning is formed with a resistance layer 36 on the conducting film 35 on these base plate for packaging 3 surfaces, makes this resistance layer 36 be formed with a plurality of perforates 360, to manifest the conducting film 35 on these electric connection pad 32 surfaces.This resistance layer 36 can be a photoresist layer such as dry film or liquid photoresistance (Photo resist) for example, it is to utilize modes such as printing, spin coating or applying, be formed on this base plate for packaging 3 surfaces, relend, also can form this perforate 360 by laser technology by modes such as exposure, development patterning in addition.
See also Fig. 3 G, then this base plate for packaging 3 is electroplated (Electroplating) processing procedure, tool conductive characteristic by this conducting film 35, when electroplating, can be used as current conduction path, on the electric connection pad 32 in this resistance layer perforate 360, plating is formed with pre-soldering tin material, reduce the generation of following point by plating mode: in the mould printing technology, when the dwindling of electric connection pad size and spacing, the perforate of this template must diminish thereupon, causes this template die sinking to be difficult for improving with manufacturing cost; Be difficult to make pre-soldering tin material to pass because of the perforate pitch-row of this template is trickle; The template wiped clean causes problems such as bottleneck on the process technique and inconvenience.This can fully be applied on the base plate for packaging with small circuit and electric connection pad spacing.Wherein, this pre-soldering tin material can be selected from the alloy that mixture constituted of lead, tin, silver, copper, bismuth, antimony, zinc, nickel, zirconium, magnesium, indium, tellurium and gallium cohort element.
See also Fig. 3 H, after the exposed surface of this electric connection pad 32 is finished the pre-soldering tin material of plating, remove this resistance layer 36 earlier, then, will have the conducting film 35 that is covered by this resistance layer 36 again now and remove.Wherein, the pre-soldering tin material of finishing of electroplating can be a conductive pole 37 forms on this electric connection pad 32, and is follow-up in order to be electrically conducted the electrode pad of crystal covering type semiconductor chip.
See also Fig. 3 I, also can be under the temperature conditions of the pre-soldering tin material fusion that is enough to make this electroplating deposition, carry out reflow (Reflow-Soldering) processing procedure, make this pre-soldering tin material through reflow, form pre-solder bump 38 on this electric connection pad 32, follow-up engaging with the metal coupling of semiconductor chip forms the scolding tin knot.
Fig. 4 A to Fig. 4 E describes another example of semiconductor packing substrate for forming presoldering tin material method for making of the present invention in detail, and it is to utilize the mould printing mode, deposits soldering tin material being revealed on the electric connection pad of substrate surface.
See also Fig. 4 A, semiconductor base plate for packaging 3 at first is provided, the surface of this base plate for packaging 3 has been formed with a plurality of electric connection pads 32.Certainly this substrate surface also can be formed with a plurality of conducting wires 31 simultaneously for being connected with this electric connection pad 32.
See also Fig. 4 B, then utilize modes such as printing, spin coating or applying on this is formed with base plate for packaging 3 surfaces of electric connection pad 32, be formed with an organic insulation protective layer 33, this organic insulation protective layer can be to refuse welding flux layer, for example green lacquer.
See also Fig. 4 C; carry out the thickness of this organic insulation protective layer 33 of thinning; so as to manifesting the upper surface of this electric connection pad 32, make the periphery fluid-tight engagement of this organic protection insulating barrier 33 and electric connection pad 32, and the complete upper surface that manifests this electric connection pad 32.
See also Fig. 4 D, when if this substrate surface is formed with electric connection pad 32 simultaneously with conducting wire 31, also one dielectric film 34 is arranged in these base plate for packaging 3 surface-coated, this dielectric film 34 can be the oxidation-resistant film of organic or inorganic, and utilize patterning process such as exposure, development, make this dielectric film 34 cover this conducting wire 31, make the upper surface of this electric connection pad 32 be emerging in the surface of this base plate for packaging 3.If this base plate for packaging 3 is not formed with conducting wire 31 at outermost surface, promptly there is not the necessity (shown in Fig. 3 D ') that forms dielectric film 34 coverings.Certainly, this conducting wire 31 also can form dielectric film 34 and be covered (as Fig. 3 D " shown in).In the present embodiment accompanying drawing, be to be formed with conducting wire and electric connection pad, and be formed with on this conducting wire that a dielectric film is illustrated with substrate surface.
See also Fig. 4 E, afterwards, can be by the mould printing technology, on the electric connection pad 32 on these substrate 3 surfaces, deposit soldering tin material, and under the reflow temperature condition of the soldering tin material fusion that is enough to make this deposition, carry out the processing procedure of reflow (Reflow-soldering), make this soldering tin material, on this electric connection pad 32, form solder bump 35 through reflow.Because the thickness of this dielectric film 34 only is about 2 to 5 microns, not only do not cover around this electric connection pad, the thickness of this dielectric film 34 simultaneously, can not influence follow-up surface yet and utilize mould printing at this substrate 3, the exploitativeness of deposition soldering tin material on this electric connection pad 32 is to reduce the generation of contraposition problem.Certainly,, do not have these problems yet, can effectively provide the mould printing technology to have on the electric connection pad 32 long-pending, form pre-solder bump 35 than large contact surface at this if this substrate surface is not formed with this dielectric film.The more common template sheet material of above-mentioned mould printing technology is steel plate.
Following conjunction with figs. is illustrated Application Example of the present invention, wherein, base plate for packaging 3 by the pre-scolding tin structure of the formed tool of method for making of the present invention, in an Application Example, formed conductive pole 37 on the electric connection pad 32 of this base plate for packaging 3 is to use the semiconductor chip that is bonded on a tool electrode pad.Shown in Fig. 5 A and Fig. 5 B, one semiconductor chip 41 with several electrode pad 42 is provided, correspond to the position of the conductive pole 37 of this base plate for packaging 3 respectively with the electrode pad 42 of this semiconductor chip 41, this semiconductor chip 41 is provided with and is electrically conducted on this base plate for packaging 3.
According to the present invention, another embodiment of this base plate for packaging 3 can use to be bonded on the semiconductor chip with metal coupling.As shown in Figure 6A, semiconductor chip 51 has the action face that a plurality of electrode pad 52 are formed on this semiconductor chip 51, have several metal couplings 53 on this electrode pad 52, and this semiconductor chip 51 is in the mode of corresponding respectively pre-solder bump 38 positions at this base plate for packaging 3 of this metal coupling 53, is arranged on this base plate for packaging 3.Then, shown in Fig. 6 B, make these pre-solder bump 38 reflows to this metal coupling 53, cover brilliant scolding tin knot 54 between this semiconductor chip 51 and this base plate for packaging 3, to form.Metal coupling 53 on this semiconductor chip 51 can be made of metal, alloy or deposition several metal, for example solder bump, golden projection, copper bump or with the copper post of scolding tin cap (Solder Caps) covering etc.; And this metal coupling can be an Any shape, for example follows closely the projection of column-like projection block, spherical protrusions, column-like projection block or other shape.
According to the present invention, an Application Example again of this base plate for packaging 3 also can be used on simultaneously to form covers brilliant scolding tin knot and the plate scolding tin knot to plate.Shown in Fig. 7 A, prepare a circuit board 6, this circuit board 6 can be organic or ceramic circuit board, and chip 62 is arranged on the suitable position of this circuit board 6; On this circuit board 6, several electric connection pads 61 are formed on the periphery of this chip 62, wherein, a plurality of metal couplings the 64, the 65th are respectively formed on the electrode pad 63 of this electric connection pad 61 of this circuit board 6 and this chip 62.Then, this circuit board 6 by making its metal coupling 64,65 towards the mode that is formed on the pre-solder bump 38 on this base plate for packaging 3, is connect and puts on this base plate for packaging 3.Shown in Fig. 7 B, make these metal coupling 64,65 difference reflows to corresponding pre-solder bump 38, cover brilliant scolding tin knot 66 between this chip 62 and this base plate for packaging 3, to form, and between this circuit board 6 and this base plate for packaging 3, form the scolding tin knot 67 of plate plate.
In further application of the invention embodiment, this base plate for packaging 3 also can be used as the conductor package substrate of making crystal covered package 70.Please refer to Fig. 8, this substrate respectively thereon, lower surface forms a plurality of electric connection pads, and, on the electric connection pad of this upper surface of base plate, form a plurality of pre-solder bumps 38, and plant on the electric connection pad of this base lower surface and be connected to several soldered balls 39 by said method.Semiconductor chip 71 is arranged on this base plate for packaging 3 to cover crystal type, this set-up mode that covers crystalline substance is the metal coupling 73 that makes on the electrode pad 72 that is formed on this chip 71, be soldered to this pre-solder bump 38 that is formed on this base plate for packaging 3, and be filled in the gap between this chip 71 and this base plate for packaging 3, to form this crystal covered package 70 with primer material 74.
Because in semiconductor packing substrate for forming presoldering tin material of the present invention and the method for making thereof; be that the organic insulation protective layer is manifested the electric connection pad upper surface; this electric connection pad is had than large tracts of land for forming pre-soldering tin material; avoid formation because of this insulating protective layer; the influence that causes taking integrated circuit and electric connection pad space and form height; the pre-soldering tin material use amount increase and the relative thickness of circuit package substrate are increased; cause the raising of processing procedure expense and compactization of unfavorable semiconductor device; and can be by increasing the contact area of electric connection pad with the pre-soldering tin material of deposition, and help promoting pre-scolding tin adhesion intensity.
Electric connection pad of the present invention, also can be applicable to convex pads, prewelding soldering pad or solder ball pad etc. in the general circuit plate, existing accompanying drawing is only represented with the part electric connection pad, in fact this electric connection pad and the number of scolding tin in advance, be required and designed and be distributed in the surface of base plate for packaging, and this processing procedure may be implemented on the single side or two sided of base plate for packaging according to actual processing procedure.And the foregoing description only is illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.
Claims (3)
1, a kind of semiconductor packing substrate for forming presoldering tin material method for making is characterized in that, this method for making comprises:
Provide at least one surface to be formed with the base plate for packaging of a plurality of electric connection pads;
On this base plate for packaging surface, form organic insulating protective layer; And
Grind the thickness of this organic insulation protective layer of thinning, make upper surface and each electric connection pad flush of this organic insulation protective layer, to manifest the upper surface of this electric connection pad.
2, semiconductor packing substrate for forming presoldering tin material method for making as claimed in claim 1 is characterized in that, this method for making deposits pre-soldering tin material on this electric connection pad.
3, semiconductor packing substrate for forming presoldering tin material method for making as claimed in claim 2 is characterized in that, this soldering tin material is to be deposited on this electric connection pad with mode of printing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810134649 CN100580894C (en) | 2003-12-02 | 2003-12-02 | Manufacturing method for forming semiconductor packing substrate with presoldering tin material |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810134649 CN100580894C (en) | 2003-12-02 | 2003-12-02 | Manufacturing method for forming semiconductor packing substrate with presoldering tin material |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200310117149XA Division CN100452329C (en) | 2003-12-02 | 2003-12-02 | Semiconductor packing substrate for forming presoldering tin material and its preparation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101335214A true CN101335214A (en) | 2008-12-31 |
| CN100580894C CN100580894C (en) | 2010-01-13 |
Family
ID=40197692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810134649 Expired - Fee Related CN100580894C (en) | 2003-12-02 | 2003-12-02 | Manufacturing method for forming semiconductor packing substrate with presoldering tin material |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100580894C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102227155A (en) * | 2011-03-15 | 2011-10-26 | 苏州超联光电有限公司 | Flexible printed wiring board and touch screen possessing flexible printed wiring board |
| CN102263082A (en) * | 2010-05-24 | 2011-11-30 | 南亚电路板股份有限公司 | Packaging substrate structure and manufacturing method |
| CN109817604A (en) * | 2017-11-22 | 2019-05-28 | 三星电子株式会社 | Semiconductor devices |
| CN111613714A (en) * | 2020-05-25 | 2020-09-01 | 深圳市华星光电半导体显示技术有限公司 | Micro light-emitting diode and manufacturing method thereof |
| CN115332117A (en) * | 2022-08-12 | 2022-11-11 | 苏州通富超威半导体有限公司 | Ball grid array packaging method and device |
-
2003
- 2003-12-02 CN CN 200810134649 patent/CN100580894C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263082A (en) * | 2010-05-24 | 2011-11-30 | 南亚电路板股份有限公司 | Packaging substrate structure and manufacturing method |
| CN102227155A (en) * | 2011-03-15 | 2011-10-26 | 苏州超联光电有限公司 | Flexible printed wiring board and touch screen possessing flexible printed wiring board |
| CN109817604A (en) * | 2017-11-22 | 2019-05-28 | 三星电子株式会社 | Semiconductor devices |
| CN109817604B (en) * | 2017-11-22 | 2023-09-19 | 三星电子株式会社 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
| CN111613714A (en) * | 2020-05-25 | 2020-09-01 | 深圳市华星光电半导体显示技术有限公司 | Micro light-emitting diode and manufacturing method thereof |
| CN115332117A (en) * | 2022-08-12 | 2022-11-11 | 苏州通富超威半导体有限公司 | Ball grid array packaging method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100580894C (en) | 2010-01-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4660643B2 (en) | Semiconductor package substrate for forming pre-solder structure, semiconductor package substrate on which pre-solder structure is formed, and manufacturing method thereof | |
| JP3262497B2 (en) | Chip mounted circuit card structure | |
| JP3320979B2 (en) | How to mount a device directly on a device carrier | |
| US20060201997A1 (en) | Fine pad pitch organic circuit board with plating solder and method for fabricating the same | |
| CN100495694C (en) | Semiconductor device | |
| US6753208B1 (en) | Wafer scale method of packaging integrated circuit die | |
| CN100576476C (en) | Chip buried in semiconductor encapsulation base plate structure and method for making thereof | |
| TWI260079B (en) | Micro-electronic package structure and method for fabricating the same | |
| CN103325760B (en) | Conductive bump formed on semiconductor substrate and method for fabricating the same | |
| KR20100050457A (en) | Multilayer wiring element having pin interface | |
| CN100505196C (en) | Chip electric connection structure and its manufacturing method | |
| US20070158838A1 (en) | Circuit board, method for manufacturing the same, semiconductor device, and method for manufacturing the same | |
| US7340829B2 (en) | Method for fabricating electrical connection structure of circuit board | |
| CN100534263C (en) | Circuit board conductive lug structure and making method | |
| CN102693955A (en) | Package carrier and method for manufacturing the same | |
| CN101383335B (en) | Semiconductor package substrate and fabrication method thereof | |
| CN102823337A (en) | Circuit board with anchored underfill | |
| CN1980538A (en) | Method for forming circuit-board electric connection end | |
| US6555469B1 (en) | Chip scale packages | |
| CN100580894C (en) | Manufacturing method for forming semiconductor packing substrate with presoldering tin material | |
| CN101360388B (en) | Electricity connection terminal construction of circuit board and preparation thereof | |
| CN100452329C (en) | Semiconductor packing substrate for forming presoldering tin material and its preparation method | |
| US11948899B2 (en) | Semiconductor substrate structure and manufacturing method thereof | |
| CN102202463A (en) | Side edge packaged type PCB (printed circuit board) | |
| CN100369242C (en) | Pre-soldering arrangement for semiconductor packaging substrate and method for making same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100113 Termination date: 20171202 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |