CN208706581U - Flush type chip - Google Patents
Flush type chip Download PDFInfo
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- CN208706581U CN208706581U CN201821362051.9U CN201821362051U CN208706581U CN 208706581 U CN208706581 U CN 208706581U CN 201821362051 U CN201821362051 U CN 201821362051U CN 208706581 U CN208706581 U CN 208706581U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
The application provides a kind of flush type chip.The flush type chip includes: metallic substrates；Metal layer, setting on the metallic substrate, form groove in metal layer；Chip, on the metallic substrate, and in the grooves, chip includes the first chip surface far from metallic substrates for setting, is provided with connection terminal on the first chip surface；Dielectric layer is arranged on the first chip surface of chip；Leading-out terminal is electrically connected with the connection terminal of chip, connection terminal is fanned out to.The application is by the way that chip to be arranged in the groove of metallic substrates and metal layer, so that multiple faces of chip are surrounded by metal material, such as chip includes six faces, then its five faces, it is surrounded by metal material including the surface contacted with metallic substrates and four sides adjacent with metal layer, since the thermal diffusivity of metal is good, can effectively be radiated to the chip of embedment, the heat-sinking capability for improving chip, the radiating requirements suitable for various chips.
Description
Technical field
This application involves chip encapsulation technology field, in particular to a kind of flush type chip.
Background technique
With the development of electronic product high-frequency high-speed demand, traditional wire-bonding package and flip-chip packaged mutual contact mode are difficult to completely
The demand of sufficient high-frequency high-speed signal transmission, therefore more and more chips are fanned out to technique reality using embedment in substrate or wafer scale
Existing bare chip encapsulation, reduces encapsulation interconnection size and realizes chip high-frequency high-speed and transmit the demand to signal integrity.But it is existing
The flush type encapsulation scheme of technology is difficult to realize the demand of high heat radiation chip.
Utility model content
The application can be improved the heat dissipation effect of chip mainly solving the technical problems that provide a kind of flush type chip,
To realize the radiating requirements of various chips.
In order to solve the above technical problems, the technical solution that the application uses is: providing a kind of flush type chip, be embedded to
Formula chip includes: metallic substrates；Metal layer, setting on the metallic substrate, form groove in metal layer；Chip is arranged in metal
In substrate, and in the grooves, chip includes the first chip surface far from metallic substrates, is provided on the first chip surface
Connection terminal；Dielectric layer is arranged on the first chip surface of chip；Leading-out terminal is electrically connected with the connection terminal of chip, with
Connection terminal is fanned out to.
The application is located in the groove of metal layer by the way that chip to be arranged on the metallic substrate, so that chip is multiple
Face is surrounded by metal material, such as chip includes six faces, then its five faces, the surface including being contacted with metallic substrates and with
Four adjacent sides of metal layer are surrounded by metal material, can be to the chip of embedment since the thermal diffusivity of metal is good
It is effectively radiated, improves the heat-sinking capability of chip, the radiating requirements suitable for various chips.
Detailed description of the invention
Fig. 1 is a kind of flow diagram of the manufacturing method of flush type chip provided by the embodiments of the present application；
Fig. 2-Figure 16 is the flow diagram of the manufacturing method of another flush type chip provided by the embodiments of the present application；
Figure 17 is a kind of overlooking structure diagram of flush type chip provided by the embodiments of the present application；
Figure 18 is the schematic diagram of the section structure of direction cutting of the Figure 17 along dotted line B1-B2；
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that embodiments described below is merely a part but not all of the embodiments of the present application.
Based on the embodiment in the application, obtained by those of ordinary skill in the art without making creative efforts all
Other embodiments shall fall in the protection scope of this application.
In order to keep technical solution provided by the embodiments of the present application clearer, following embodiment combination attached drawing is to the application skill
Art scheme is described in detail.
Referring to Fig. 1, Fig. 1 is a kind of process signal of the manufacturing method of flush type chip provided by the embodiments of the present application
Figure.As shown in Figure 1, the manufacturing method of the present embodiment the following steps are included:
Step S1: a metallic substrates are provided.
Step S2: metal layer is set on the metallic substrate, wherein multiple grooves are formed in metal layer.
Step S3: chip being placed on the metallic substrate, and in the grooves, and chip includes first far from metallic substrates
Chip surface is provided with connection terminal on the first chip surface.
Step S4: dielectric layer is set on the first chip surface of chip.
Step S5: the connection terminal of chip is fanned out to.
Therefore, the present embodiment is by the way that chip to be arranged on the metallic substrate, and is located in the groove of metal layer, so that chip
Multiple faces surrounded by metal material, such as chip includes six faces, then its five faces, including the surface contacted with metallic substrates
And four sides adjacent with metal layer are surrounded by metal material, it, can be to embedment since the thermal diffusivity of metal is good
Chip effectively radiated, improve the heat-sinking capability of chip, the radiating requirements suitable for various chips.
Referring to Fig. 2, Fig. 2 is the process signal of the manufacturing method of another flush type chip provided by the embodiments of the present application
Figure, Fig. 3 to Figure 16 is the process flow diagram of corresponding manufacturing method shown in Fig. 2.As shown in Fig. 2, the manufacture of the present embodiment
Method the following steps are included:
Step S10: a metallic substrates 100 are provided.
As shown in figure 3, the size of metallic substrates 100 can be according to PCB (Printed Circuit Board, printed circuit
Plate) selection of process equipment ability.The area size of metallic substrates 100 can be 500 millimeters × 600 millimeters, metallic substrates 100
Thickness can be 30 microns -500 microns.The material of metallic substrates 100 can be thermal coefficient height, cheap copper, can also
To be the cheap metals such as aluminium, nickel.
Metallic substrates 100 include the first substrate surface 111 and the second substrate surface 112.First substrate surface 111 and second
Substrate surface 112 is oppositely arranged.
Step S20: first photosensitive film layer 210 is set on the first substrate surface 111 of metallic substrates 100, in the second base
Second photosensitive film layer 220 is set on bottom surface 112, as shown in Figure 4.
First photosensitive film layer 210 and the second photosensitive film layer can be specifically arranged in this step by way of being bonded or coating
220。
The material of first photosensitive film layer 210 and the second photosensitive film layer 220 can be the same or different.The present embodiment is with two
For the material of person is identical.The material of first photosensitive film layer 210 and the second photosensitive film layer 220 can be photosensitive type organic material, and
The type of film layer can be dry film or wet film.
First photosensitive film layer 210 is used for the reference standard made as subsequent metal layer, therefore its thickness should be with metal layer
Thickness it is suitable, and metal layer is used to surround the chip being embedded to, therefore the thickness of metal layer can be suitable with the thickness of chip.With this
It derives, the thickness of first photosensitive film layer 210 of the present embodiment can choose 50 microns -300 microns as needed, than to be embedded to
About 15-20 microns or more of the thickness of chip.
Second photosensitive layer 220 mainly for the protection of metallic substrates 100 the second substrate surface 112 in metal deposition processes
It is not coated with metal, it is contemplated that the control of material cost, thickness are smaller than the thickness of the first photosensitive layer 210, can choose
20-30 microns.
It should be understood that the second thicker photosensitive film layer also can be set when considering the strength factor of the second photosensitive film layer 220
220, such as set identical as the thickness of the first photosensitive film layer 210 for the second photosensitive film layer 220.The identical photosensitive film layer of thickness
It may make equipment disposably to produce, thus save modeling cost and the time of photosensitive film layer.
Step S30: being exposed the first photosensitive film layer 210, develop, to form spaced patterning films 211,
Patterning films 211 are corresponding with groove and gap.
Wherein, groove is for chip placement, and gap is the cutting for chip, referring specifically to described hereinafter.
As shown in figure 5, this step is specially to use in PCB processing procedure exposure development equipment to the first photosensitive film layer 210, second
Photosensitive film layer 220 is exposed development, wherein the first photosensitive film layer 210 is that part is photosensitive, forms patterning films 211.Second
Photosensitive film layer 220 is comprehensively photosensitive, therefore can be fully retained on the second substrate surface 112 of metallic substrates 100.
Step S40: carrying out metal plating between two patterning films 211, to form metal layer 110.
As shown in fig. 6, this step metal layer 110 can be electroplated between two patterning films 211 by way of plating.
When plating can control plating metal layer height be slightly below or equal to patterning films 211 height.
If the height of the metal layer 110 of plating is different, brushing process can be increased after the completion of plating, to metal layer 110
Surface carry out brushing processing.Ensure that the metal height difference that 110 whole surface of metal layer is electroplated is less than or equal to 5 microns.
The material for the metal layer 110 being electroplated in this step may include the metals such as copper, nickel.
It should be understood that in other embodiments, metal layer 110 can also be arranged by modes such as sputterings.The present embodiment is not right
The set-up mode of metal layer 110 is restricted.
Step S50: film layer 211 and the removal of the second photosensitive film layer 220 be will be patterned into.
As shown in fig. 7, strong basicity chemical medicinal liquid, which can be used, in this step will be patterned into film layer 211 and the second photosensitive film layer
220 removals.To form groove 301 and gap 302 in metallic substrates 100.
As shown in Figure 7 it is found that groove 301 and gap 302 are spaced by metal layer 110 and are arranged.
In the present embodiment, groove 301 will be used for chip placement, width can be equal to or greater than chip width, thickness
The thickness of chip can be greater than or equal to.The present embodiment by take the width and thickness of groove 301 be respectively greater than chip width and
It is described in detail for thickness.
Cutting of the gap 302 for chip buried rear one single chip packaging body.
The width of groove 301 can be greater than or equal to the width in gap 302.The single core that the present embodiment is formed in view of cutting
The structure of piece packaging body will select the width in gap 302 to be less than the width of groove 301, and the width in gap 302 is set with cutting
The comparable size of standby width.So that in one single chip packaging body after cutting without or exist and few be located at gap 302
In filler, the dielectric layer being filled in gap 302 as described later.It is possible thereby to the metal layer 110 that chip will be encapsulated
It is exposed, improve heat dissipation effect.
Step S60: adhesive glue 340 is set in the position that metallic substrates 100 are located at groove 301, chip 300 is placed on metal
In the groove 301 of substrate 100, and bonded by adhesive glue 340 and metallic substrates 100.
As shown in figure 8, chip 300 includes the first chip surface 310 and the second chip surface 320.First chip surface 310
It is oppositely arranged with the second chip surface 320.Also, connection terminal 330 is provided on the first chip surface 310.
This step is specially to bond the second chip surface 320 of chip 300 with adhesive glue 340, passes through adhesive glue
340 bond with metallic substrates 100.
Adhesive glue 340 can be conductive or non-conductive resin or metal powder composite materials.It can further use and add
The mode of heat cure solidifies adhesive glue 340, and metallic substrates 100 and chip 300 are relatively fixed.
In the present embodiment, the height of chip 300 can be equal to or less than metal layer 110 thickness so that complete it is chip buried
After formula encapsulation, all sides of chip 300 are surrounded by metal layer 110, are effectively radiated.
In other embodiments, it is contemplated that in the case where the material cost of metal, the height of chip 300 can also be greater than metal
The thickness of layer 110, that is to say, that after completing chip embedded type encapsulation, a part of all sides of chip 300 is by metal layer 110
It surrounds.
Step S70: being arranged dielectric layer 400 on the first chip surface 310 of chip 300, and dielectric layer 400 is further filled
Groove and gap, and cover metal layer 110.
As shown in figure 9, dielectric layer 400 can be the resin material of semi-solid preparation, such as epoxy resin or bismaleimide-three
Piperazine resin and inorganic filler etc. form flaky material, and material thickness is can choose as needed between 20 microns of -100um.Medium
Layer 400 can also be with the flaky material of photosensitive type, by can thoroughly solidify after heating.Certainly, dielectric layer 400 or non-sense
The flaky material of light type.
As shown in Figure 10, dielectric layer 400 is solidified.Specifically, dielectric layer 400 is pressed at high temperature under high pressure
Metal layer 110,300 surface of chip are simultaneously fully cured, and thus cover the first chip surface 310 and metal layer of chip 300
110.Dielectric layer 400 goes back liquefiable at high temperature under high pressure and flows into the gap between chip 300 and groove 301 and gap 302
Between.Gap that dielectric layer 400 flows between chip 300 and groove 301 and realize in the embedment metal layer 110 of chip 300.
Step S80: conductive through hole 410 is set in the position that dielectric layer 400 is correspondingly connected with terminal 330, conductive through hole 410 will
Connection terminal 330 is exposed.
As shown in figure 11, the top aperture in cured dielectric layer 400 in the connection terminal 330 of corresponding chip 300, shape
At Microvia (i.e. conductive through hole) 410, pore size can be arranged according to the size of connection terminal 330, such as may be configured as about
30 microns -100 microns.
According to described previously, if the material of dielectric layer 400 is non-photo-sensing profile material, this step can be using laser drill etc.
Technique realizes aperture.If dielectric layer 400 is photosensitive type material, aperture can be realized using the techniques such as solidification after exposure development.
Step S90: the first leading-out terminal 411 is set in conductive through hole 410, and is extended to outside dielectric layer 400, will be connected
Connecting terminal 330 is fanned out to.
As shown in figure 12, one layer of metal conducting layer can be arranged on 400 surface of dielectric layer in this step, and metal conducting layer is further
Fill conductive through hole 410.Then patterning is carried out to metal conducting layer and forms the first leading-out terminal 411.
Specifically, can metallize first on 400 surface of dielectric layer and 410 inner wall of conductive through hole, and then can be used
The techniques such as plating fill and lead up conductive through hole 410, and flush with the metal on 400 surface of dielectric layer, to form above-mentioned metallic conduction
Layer.
Further, the first leading-out terminal 412 can be further formed when patterning to metal conducting layer.First draws
Terminal 412 can be the leading-out terminal of chip 300 out, or the leading-out terminal of other chips.
Step S101: solder mask 500 is set on dielectric layer 400, and is formed in the position of corresponding first leading-out terminal 411
Welding resistance opening 420, with exposed first leading-out terminal 411.
As shown in figure 13, one layer of solder mask 500 can be set on dielectric layer 400 first.Then figure is carried out to solder mask 500
Caseization processing, to form welding resistance opening 420.Welding resistance opening 420 is further disposed at the position of the first leading-out terminal 412, will
First leading-out terminal 412 is exposed.
Step S102: being further arranged the second leading-out terminal 600 on the first leading-out terminal 411, so that connection terminal 330
It is fanned out to by the first leading-out terminal 411 and the second leading-out terminal 600.
It please refers to shown in Figure 14 and Figure 15, wherein Figure 14 is that the plan structure of the flush type chip of corresponding step S102 is shown
It is intended to, Figure 15 is the schematic diagram of the section structure of the embedded structure shown in Figure 14 along dotted line A1-A2 section view.
As shown in Figure 14 and Figure 15, this step can be used Reflow Soldering and graft ball technique in (the i.e. first extraction of welding resistance opening 420
The position of terminal 411 and 412) surface placement tin ball, form the second leading-out terminal 600.To form chip buried metal layer
110, chip connection terminal 330 passes through the structure that the first leading-out terminal 411 and the second leading-out terminal 600 are fanned out to.
Step S103: cutting process is carried out in the corresponding position in gap 302, divides the chip 300 being located in groove 301
From.
As shown in figure 16, cutting process is carried out to the corresponding position in gap 302 by cutting equipment 700.Due in Fig. 5-7
When forming groove 301, gap 302 is formd between groove 301, and dielectric layer 400, medium are filled in gap 302
Its hardness is lower compared to the metal material of metal layer 110 for the material of layer 400, to facilitate the cutting of chip 300.
It, can be when step S101 forms solder mask 500 in the corresponding gap of solder mask 500 in order to facilitate the cutting of this step
Target pattern is arranged in 302 position, to facilitate the positioning of the cutting equipment 700 of this step.
Therefore, the present embodiment is by the way that chip 300 to be arranged between metallic substrates 100 and the groove 301 of metal layer 110,
So that multiple faces of chip 300 are surrounded by metal material.It, can be to the chip 300 of embedment since the thermal diffusivity of metal is good
It is effectively radiated, improves the heat-sinking capability of chip 300, the radiating requirements suitable for various chips 300.
In addition, being provided with gap 302 during manufacturing chip 300, facilitate the cutting of chip package monomer.
Finally, realizing the extraction of chip 300 by the manufacturing process technology that plating, Reflow Soldering graft the printed circuit boards such as ball
Terminal 330 is fanned out to, to meet the needs of wafer-level package is to device pin area, while real using printed wiring board technique
The encapsulation that is fanned out to of existing chip has lower cost.
Wherein, in another embodiment, according to previously described manufacturing method, two can also be only arranged in metallic substrates 100
A metal layer 110.Chip 300 is only one, is arranged between two metal layer 110, has saved subsequent cutting step.
In another embodiment, according to previously described manufacturing method, chip 300 also be can be set in all grooves
301 and gap 302 in, i.e., different groove 301 and gap 302 is arranged in various sizes of chip 300.Under this scenario, core
The cutting that piece encapsulates monomer may be selected to carry out part cutting to metal layer 110.
In another embodiment, the first photosensitive film layer can also be only arranged in step S20 described previously, and it is photosensitive to save second
Film layer.Metallic substrates 100 can be placed in the equipment such as plummer at this time, the surface of the second substrate surface 112 and plummer
Fitting, blocks the second substrate surface 112 by equipment such as plummers.
The embodiment of the present application also provides a kind of flush type chip, which can be according to previously described manufacturer
Method is formed.
It is the structure that a kind of flush type chip provided by the embodiments of the present application is overlooked referring specifically to Figure 17 and Figure 18, Figure 17
Schematic diagram, Figure 18 are the schematic diagram of the section structure of direction cutting of the Figure 17 along dotted line B1-B2.As shown in Figure 17 and Figure 18, originally
The flush type chip 10 of embodiment includes metallic substrates 100, metal layer 110, chip 300, dielectric layer 400 and leading-out terminal
700。
Wherein, the material of metallic substrates 100 can be thermal coefficient height, cheap copper, and it is honest and clean to be also possible to aluminium, nickel etc.
Valence metal.
Metallic substrates 100 include the first substrate surface 111 and the second substrate surface 112.First substrate surface 111 and second
Substrate surface 112 is oppositely arranged.
Metal layer 110 is arranged in metallic substrates 100, and groove 301 is formed in metal layer 110, is used for chip placement 300.
The width of groove 301 can be greater than or equal to the width of chip 300.
Metal layer 110 is used to surround the chip 300 of embedment, therefore the thickness of metal layer 110 can be with the thickness phase of chip 300
When.The thickness of the metal layer 110 of the present embodiment can choose 50 microns -300 microns as needed, thicker than chip to be embedded to
About 15-20 microns or more of degree.
In other embodiments, it is contemplated that in the case where the material cost of metal, the height of chip 300 can also be greater than metal
The thickness of layer 110, that is to say, that after completing chip embedded type encapsulation, a part of all sides of chip 300 is by metal layer 110
It surrounds.
The material of metal layer 110 may include the metals such as copper, nickel.
Chip 300 is arranged in metallic substrates 100, and is located in groove 301.
Chip 300 includes the first chip surface 310 and the second chip surface 320 being oppositely arranged.Wherein, the first chip list
Face 310 is arranged far from metallic substrates 100, is provided with connection terminal 330 on the first chip surface 310.
Second chip surface 320 is arranged close to metallic substrates 100.It is arranged in the position that metallic substrates 100 are located at groove 301
Adhesive glue 340, the second chip surface 320 are adhesively fixed by adhesive glue 340 with metallic substrates 100.
Adhesive glue 340 can be conductive or non-conductive resin or metal powder composite materials.It can further use and add
The mode of heat cure solidifies adhesive glue 340, and metallic substrates 100 and chip 300 are relatively fixed.
Dielectric layer 400 is arranged on the first chip surface 310 of chip 300.Dielectric layer 400 further fills groove 301,
And cover metal layer 110.
Dielectric layer 400 can be the resin material of semi-solid preparation, such as epoxy resin or bismaleimide-triazine resin and nothing
Machine filler etc. forms flaky material, and material thickness is can choose as needed between 20 microns of -100um.Dielectric layer 400 can also be with
The flaky material of photosensitive type, by can thoroughly solidify after heating.Certainly, the sheet of dielectric layer 400 or non-photo-sensing type
Material.
Dielectric layer 400 is pressed into metal layer 110,300 surface of chip at high temperature under high pressure and is fully cured, is thus covered
The first chip surface 310 and metal layer 110 of chip 300.Dielectric layer 400 goes back liquefiable at high temperature under high pressure and flows into chip
Gap between 300 and groove 301.Gap that dielectric layer 400 flows between chip 300 and groove 301 and realize chip 300
It is embedded in metal layer 110.
Leading-out terminal 700 is electrically connected with the connection terminal 330 of chip 300, and connection terminal 300 is fanned out to.
Leading-out terminal 700 includes the first leading-out terminal 411 and 412 and the second leading-out terminal 600.
Conductive through hole 410 is further provided on dielectric layer 400, conductive through hole 410 is exposed by connection terminal 330.It is conductive
The pore size of through-hole 410 can be arranged according to the size of connection terminal 330, such as may be configured as about 30 microns -100 microns.
According to described previously, if the material of dielectric layer 400 is non-photo-sensing profile material, the realization of the techniques such as laser drill can be used
Aperture.If dielectric layer 400 is photosensitive type material, it can be used and the techniques such as solidify after exposure development and realize aperture.
First leading-out terminal 411 is arranged in conductive through hole 410, and extends to outside dielectric layer 400, by connection terminal
330 are fanned out to.
Further, the first leading-out terminal 412 is further set on dielectric layer 400, and the first leading-out terminal 412 can be core
The leading-out terminal of piece 300, or the leading-out terminal of other chips.
Further, flush type chip 10 further includes solder mask 500.Solder mask 500 is arranged on dielectric layer 400, and
The position of corresponding first leading-out terminal 411 and 412 forms welding resistance opening 420, with exposed first leading-out terminal 411 and 412.
Second leading-out terminal 600 is arranged on the first leading-out terminal 411 and 412.Specifically Reflow Soldering, which can be used, grafts ball work
Skill places tin ball on 420 (i.e. the position of the first leading-out terminal 411 and 412) surfaces of welding resistance opening, forms the second leading-out terminal
600.It is embedded to metal layer 110 to form chip 300, chip connection terminal 330 is drawn by the first leading-out terminal 411 and second
The structure that terminal 600 is fanned out to.
Therefore, the present embodiment is by the way that chip 300 to be arranged between metallic substrates 100 and the groove 301 of metal layer 110,
So that multiple faces of chip 300 are surrounded by metal material.It, can be to the chip 300 of embedment since the thermal diffusivity of metal is good
It is effectively radiated, improves the heat-sinking capability of chip 300, the radiating requirements suitable for various chips 300.
In addition, realizing the leading-out terminal 330 of chip 300 by the technology that plating, Reflow Soldering graft the printed circuit boards such as ball
Be fanned out to, to meet the needs of wafer-level package is to device pin area, while chip is realized using printed wiring board technique
Be fanned out to encapsulation have lower cost.
The foregoing is merely presently filed embodiments, are not intended to limit the scope of the patents of the application, all to utilize this
Equivalent structure or equivalent flow shift made by application specification and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of flush type chip, which is characterized in that the flush type chip includes:
Metallic substrates；
Metal layer is arranged in the metallic substrates, and groove is formed in the metal layer；
Chip is arranged in the metallic substrates, and is located in the groove, and the chip includes far from the metallic substrates
First chip surface is provided with connection terminal on first chip surface；
Dielectric layer is arranged on first chip surface of the chip；
Leading-out terminal is electrically connected with the connection terminal of the chip, the connection terminal is fanned out to.
2. flush type chip according to claim 1, which is characterized in that
The thickness of the metal layer is equal to or more than the thickness of the chip.
3. flush type chip according to claim 2, which is characterized in that the thickness range of the metal layer be 50 microns-
300 microns, the thickness of the metal layer is 15-20 microns bigger than the thickness of the chip.
4. flush type chip according to claim 1, which is characterized in that the width of the groove is greater than or equal to the core
The width of piece.
5. flush type chip according to claim 1, which is characterized in that the chip further comprises and first core
The second chip surface that piece surface is oppositely arranged；
Adhesive glue is set in the position that the metallic substrates are located at the groove, second chip surface passes through the adhesive glue
It is adhesively fixed with the metallic substrates.
6. flush type chip according to claim 1, which is characterized in that the dielectric layer further fills the groove,
And cover the metal layer.
7. flush type chip according to claim 1, which is characterized in that the leading-out terminal include the first leading-out terminal and
Second leading-out terminal；
Conductive through hole is further provided on the dielectric layer, the conductive through hole is exposed by the connection terminal, and described first
Leading-out terminal is arranged in the conductive through hole, and extends to outside the dielectric layer, and the connection terminal is fanned out to.
8. flush type chip according to claim 7, which is characterized in that the pore size of the conductive through hole is 30 micro-
- 100 microns of rice.
9. flush type chip according to claim 7, which is characterized in that the flush type chip further include:
Solder mask is arranged on the dielectric layer, and forms welding resistance opening in the position of corresponding first leading-out terminal, with exposed institute
State the first leading-out terminal；
Second leading-out terminal is arranged on first leading-out terminal, so that the connection terminal is drawn by described first
Terminal and second leading-out terminal are fanned out to.
10. flush type chip according to claim 1, which is characterized in that the thickness range of the metallic substrates is 30 micro-
- 500 microns of rice.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821362051.9U CN208706581U (en) | 2018-08-22 | 2018-08-22 | Flush type chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821362051.9U CN208706581U (en) | 2018-08-22 | 2018-08-22 | Flush type chip |
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| Publication Number | Publication Date |
|---|---|
| CN208706581U true CN208706581U (en) | 2019-04-05 |
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ID=65944018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821362051.9U Active CN208706581U (en) | 2018-08-22 | 2018-08-22 | Flush type chip |
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| Country | Link |
|---|---|
| CN (1) | CN208706581U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110858548A (en) * | 2018-08-22 | 2020-03-03 | 深南电路股份有限公司 | Embedded chip and manufacturing method thereof |
-
2018
- 2018-08-22 CN CN201821362051.9U patent/CN208706581U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110858548A (en) * | 2018-08-22 | 2020-03-03 | 深南电路股份有限公司 | Embedded chip and manufacturing method thereof |
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