CN102255501A - Charge pump circuit - Google Patents
Charge pump circuit Download PDFInfo
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- CN102255501A CN102255501A CN2011101825154A CN201110182515A CN102255501A CN 102255501 A CN102255501 A CN 102255501A CN 2011101825154 A CN2011101825154 A CN 2011101825154A CN 201110182515 A CN201110182515 A CN 201110182515A CN 102255501 A CN102255501 A CN 102255501A
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Abstract
The invention provides a charge pump circuit which comprises a current source, a first input terminal, a second input terminal, and an output terminal. The charge pump circuit also comprises an upper current mirror which is connected with the first input terminal and the current source, a lower current mirror which is connected with the second input terminal and the current source, an operational amplifier which is connected with the upper current mirror and the lower current mirror, and a low-pass filter which is connected with the operational amplifier and the output terminal. The upper current mirror is a P-type field effect transistor integrated circuit which is used for generating charging current, and the lower current mirror is an N-type field effect transistor integrated circuit which is used for generating discharging current. A positive input terminal of the operational amplifier is connected with the upper current mirror and the lower current mirror, an anti-phase input terminal of the operational amplifier is connected with the output terminal through the low-pass filter, and an output terminal of the operational amplifier is connected with the upper current mirror. According to the invention, stability of an output signal is guaranteed.
Description
Technical field
The present invention relates to a kind of control circuit, refer to a kind of charge pump circuit that can guarantee stable output signal especially.
Background technology
No matter be phase-locked loop or delay phase-locked loop, all need output signal of itself and the phase difference between the input signal are differentiated by phase frequency detector, with charge pump this phase difference is carried out integration then, control now in voltage with the form body of voltage variety the result of integration, control voltage controlled oscillator or voltage controlled delay line with control voltage then, till Phase synchronization between the two.
Fig. 1 is the system block diagram of phase-locked loop in the prior art, and it comprises that an input, a phase frequency detector that links to each other with this input, a charge pump circuit that links to each other with this phase frequency detector, a low pass filter that links to each other with this charge pump circuit, a voltage controlled oscillator that links to each other with this low pass filter, an output and that links to each other with this voltage controlled oscillator are connected in the frequency divider between this phase frequency detector and this voltage controlled oscillator.The output signal of existing charge pump circuit often concussion occurs owing to the positive feedback phenomenon, makes the output signal instability of charge pump circuit, and further influences the operate as normal of whole phase-locked loop.
Summary of the invention
In view of above content, be necessary to provide a kind of charge pump circuit that can guarantee stable output signal.
A kind of charge pump circuit, comprise a current source, one first input end, one second input, an and output, described charge pump circuit also comprises a last current mirror that links to each other with described first input end and described current source, the one following current mirror that links to each other with described second input and described current source, one operational amplifier and a low pass filter that links to each other with described operational amplifier and described output that links to each other with described upward current mirror and described current mirror down, described upward current mirror is a P type field effect transistor aggregate circuit, and be used to produce a charging current, described current mirror down is a N type field effect transistor aggregate circuit, and be used to produce a discharging current, one normal phase input end of described operational amplifier links to each other with described upward current mirror and described current mirror down, one inverting input of described operational amplifier links to each other with described output by described low pass filter, and an output of described operational amplifier links to each other with the described current mirror of going up.
Relative prior art, charge pump circuit of the present invention is by the different connected modes of operational amplifier, and between operational amplifier and output, be connected the feedback intensity that low pass filter reduces positive feedback, eliminated the concussion of the output signal that the positive feedback phenomenon causes, guaranteed the stability of charge pump circuit output signal, made that whole phase-locked loop can operate as normal.
Description of drawings
Fig. 1 is the system block diagram of existing phase-locked loop.
Fig. 2 is the block architecture diagram of charge pump circuit of the present invention.
Fig. 3 is the circuit diagram of charge pump circuit better embodiment of the present invention.
Embodiment
See also Fig. 2, charge pump circuit better embodiment of the present invention comprises that a current source, a first input end, one second input, an output, a last current mirror that links to each other with this first input end and this current source, a following current mirror that links to each other with this second input and this current source, an operational amplifier and that links to each other with current mirror, this time current mirror and this output on this are connected in the low pass filter between this operational amplifier and this output.
Please consult Fig. 2 and Fig. 3 simultaneously, charge pump circuit better embodiment of the present invention comprises a current source I, one first input end SLWDN, the one last current mirror that links to each other with this first input end SLWDN, one second input SPDUP, the one following current mirror that links to each other with this second input SPDUP, the one operational amplifier OPA that links to each other with current mirror and this time current mirror on this, one low pass filter that links to each other with current mirror and this operational amplifier OPA on this, one with should go up current mirror, the output CHOUT that this time current mirror and this low pass filter link to each other, an one power end AVD and a ground end AVS.Should go up current mirror and be used to produce one by the charging current I1 of this power end AVD to this output CHOUT, this time current mirror is used to produce one by the discharging current I2 of this output CHOUT to this ground end AVS.
Should go up current mirror is P type field effect transistor (PMOS) aggregate circuit, it comprises one first field effect transistor M1, one second field effect transistor M2, one the 3rd field effect transistor M3, one the 4th field effect transistor M4, one the 5th field effect transistor M5 and one the 6th field effect transistor M6, and this first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3, the 4th field effect transistor M4, the 5th field effect transistor M5 and the 6th field effect transistor M6 are P type field effect transistor; This time current mirror is N type field effect transistor (NMOS) aggregate circuit, it comprises one the 7th field effect transistor M7, one the 8th field effect transistor M8, one the 9th field effect transistor M9, the tenth a field effect transistor M10, the 11 a field effect transistor M11, the 12 a field effect transistor M12, the 13 a field effect transistor M13 and 1 the 14 field effect transistor M14, and the 7th field effect transistor M7, the 8th field effect transistor M8, the 9th field effect transistor M9, the tenth field effect transistor M10, the 11 field effect transistor M11, the 12 field effect transistor M12, the 13 field effect transistor M13 and the 14 field effect transistor M14 are N type field effect transistor.This low pass filter comprises a resistance R 1, one first capacitor C 1 and one second capacitor C 2.
The concrete annexation of charge pump circuit better embodiment of the present invention is as follows: current mirror links to each other by this current source I with this time current mirror on this, and this operational amplifier OPA is connected on this between the current mirror and this time current mirror.This low pass filter is connected between this operational amplifier OPA and this output CHOUT.This first input end SLWDN links to each other with the grid of the first field effect transistor M1 of current mirror on this, the drain electrode of this first field effect transistor M1 links to each other with the source class of this second field effect transistor M2, the drain electrode of the 3rd field effect transistor M3 links to each other with the source class of the 4th field effect transistor M4, and the drain electrode of the 5th field effect transistor M5 links to each other with the source class of the 6th field effect transistor M6.This second input SPDUP links to each other with the grid of the 8th field effect transistor M8 of this time current mirror, the drain electrode of the 8th field effect transistor M8 links to each other with the source class of the 7th field effect transistor M7, the grid of the grid of the 7th field effect transistor M7 and the 9th field effect transistor M9, the grid of the 11 field effect transistor M11, the grid of the 13 field effect transistor M13, the forward end of drain electrode and this current source I links to each other, the source class of the 9th field effect transistor M9 links to each other with the drain electrode of the tenth field effect transistor M10, the source class of the 11 field effect transistor M11 links to each other with the drain electrode of the 12 field effect transistor M12, and the source class of the 13 field effect transistor M13 links to each other with the drain electrode of the 14 field effect transistor M14.The normal phase input end of this operational amplifier OPA with this in the current mirror in the drain electrode of the 4th field effect transistor M4 and this time current mirror drain electrode of the 9th field effect transistor M9 link to each other, the inverting input of this operational amplifier OPA links to each other with an end of an end of this resistance R 1 and this first capacitor C 1, and the drain electrode of grid, drain electrode and the 11 field effect transistor M11 of the grid of the output of this operational amplifier OPA and this second field effect transistor M2, the grid of the 4th field effect transistor M4, the 6th field effect transistor M6 links to each other.This output CHOUT links to each other with the drain electrode of this second field effect transistor M2, the drain electrode of the 7th field effect transistor M7, the other end of this resistance R 1 and an end of this second capacitor C 2.This power end AVD links to each other with the backward end of this current source I, the source class of this first field effect transistor M1, the source class of the 3rd field effect transistor M3, the source class of the 5th field effect transistor M5, the grid of the tenth field effect transistor M10, the grid of the 12 field effect transistor M12, the grid of the 14 field effect transistor M14, the other end of this first capacitor C 1 and the other end of this second capacitor C 2.This ground end AVS links to each other with the grid of the 3rd field effect transistor M3, the grid of the 5th field effect transistor M5, the source class of the 8th field effect transistor M8, the source class of the tenth field effect transistor M10, the source class of the 12 field effect transistor M12 and the source class of the 14 field effect transistor M14.
The operation principle of charge pump circuit better embodiment of the present invention is as follows: SLWDN imports a low level voltage when this first input end, when this second input SPDUP imports a high level voltage, SLWDN is effective for this first input end, this first field effect transistor M1 conducting, the electric current of this current source I flows to this output CHOUT by this first field effect transistor M1 and this second field effect transistor M2, promptly should go up current mirror and produce by the charging current I1 of this power end AVD to this output CHOUT, charge pump circuit is in charged state; SLWDN imports a high level voltage when this first input end, when this second input SPDUP imports a low level voltage, SPDUP is effective for this second input, the 8th field effect transistor M8 conducting, the electric current of this output CHOUT flows to this ground end AVS by the 7th field effect transistor M7 and the 8th field effect transistor M8, promptly this time current mirror produces the discharging current I2 to this ground end AVS by this output CHOUT, and charge pump circuit is in discharge condition.
In charge pump circuit charging and discharge process, this first field effect transistor M1, the 3rd field effect transistor M3, the 5th field effect transistor M5, the tenth field effect transistor M10, the 12 field effect transistor M12 and the 14 field effect transistor M14 are conducting state, the 6th field effect transistor M6 provides a grid voltage that design needs for the 4th field effect transistor M4 and this second field effect transistor M2, and the 13 field effect transistor M13 provides the grid voltage of design needs for the 11 field effect transistor M11, the 9th field effect transistor M9 and the 7th field effect transistor M7.This second field effect transistor M2, the 4th field effect transistor M4, the 7th field effect transistor M7, the 9th field effect transistor M9 and this operational amplifier OPA form feedback control loop jointly, and keep the normal phase input end of this operational amplifier OPA to equate by negative feedback, thereby make current mirror produces on this charging current I1 and the discharging current I2 of this time current mirror generation to mate with the voltage of negative-phase input.Because flowing through the electric current of the 6th field effect transistor M6 equates with the electric current that flows through the 11 field effect transistor M11, can release the electric current that flows through the 6th field effect transistor M6 equates with the electric current that flows through the 13 field effect transistor M13, thereby draw the electric current that flows through this second field effect transistor M2 and equate that with the electric current that flows through the 7th field effect transistor M7 promptly charging current I1 equates with discharging current I2.
The present invention is connected to the last current mirror of being made up of P type field effect transistor with the output of operational amplifier OPA, the inverting input of operational amplifier OPA is linked to each other with this output CHOUT by low pass filter, after making positive feedback signal by output CHOUT output, process is by resistance R 1, behind the low pass filter that first capacitor C 1 and second capacitor C 2 are formed, very little with what be attenuated, reduced the feedback intensity of positive feedback, even and the positive feedback phenomenon occurs, make output CHOUT to rise very high in moment, through voltage controlled oscillator after the low pass filter also is the meeting very low frequency of output suddenly, this processing to frequency divider can not throw into question, in addition, grid voltage control stabilization owing to the following current mirror of being made up of N type field effect transistor can not drag down output CHOUT moment yet.Therefore guaranteed the stability of output CHOUT output signal.
Charge pump circuit of the present invention is by the different connected modes of operational amplifier OPA, and between operational amplifier OPA and output CHOUT, be connected the feedback intensity that low pass filter reduces positive feedback, eliminated the concussion of the output signal that the positive feedback phenomenon causes, guaranteed the stability of charge pump circuit output signal, made that whole phase-locked loop can operate as normal.
Claims (7)
1. charge pump circuit, comprise a current source, one first input end, one second input, an and output, it is characterized in that: described charge pump circuit also comprises a last current mirror that links to each other with described first input end and described current source, the one following current mirror that links to each other with described second input and described current source, one operational amplifier and a low pass filter that links to each other with described operational amplifier and described output that links to each other with described upward current mirror and described current mirror down, described upward current mirror is a P type field effect transistor aggregate circuit, and be used to produce a charging current, described current mirror down is a N type field effect transistor aggregate circuit, and be used to produce a discharging current, one normal phase input end of described operational amplifier links to each other with described upward current mirror and described current mirror down, one inverting input of described operational amplifier links to each other with described output by described low pass filter, and an output of described operational amplifier links to each other with the described current mirror of going up.
2. charge pump circuit as claimed in claim 1, it is characterized in that: the described current mirror of going up comprises one first field effect transistor, one second field effect transistor, one the 3rd field effect transistor, one the 4th field effect transistor, one the 5th field effect transistor and one the 6th field effect transistor, described first input end links to each other with the grid of described first field effect transistor, the drain electrode of described first field effect transistor links to each other with the source class of described second field effect transistor, the drain electrode of described the 3rd field effect transistor links to each other with the source class of described the 4th field effect transistor, and the drain electrode of described the 5th field effect transistor links to each other with the source class of described the 6th field effect transistor.
3. charge pump circuit as claimed in claim 2, it is characterized in that: described current mirror down comprises one the 7th field effect transistor, one the 8th field effect transistor, one the 9th field effect transistor, the tenth field effect transistor, the 11 field effect transistor, the 12 field effect transistor, the 13 field effect transistor and 1 the 14 field effect transistor, described second input links to each other with the grid of described the 8th field effect transistor, the drain electrode of described the 8th field effect transistor links to each other with the source class of described the 7th field effect transistor, the grid of the grid of described the 7th field effect transistor and described the 9th field effect transistor, the grid of described the 11 field effect transistor, the grid of described the 13 field effect transistor, one forward end of drain electrode and described current source links to each other, the source class of described the 9th field effect transistor links to each other with the drain electrode of described the tenth field effect transistor, the source class of described the 11 field effect transistor links to each other with the drain electrode of described the 12 field effect transistor, and the source class of described the 13 field effect transistor links to each other with the drain electrode of described the 14 field effect transistor.
4. charge pump circuit as claimed in claim 3, it is characterized in that: described low pass filter comprises a resistance, one first electric capacity and one second electric capacity, the normal phase input end of described operational amplifier links to each other with the drain electrode of described the 4th field effect transistor and the drain electrode of described the 9th field effect transistor, the inverting input of described operational amplifier links to each other the grid of the output of described operational amplifier and described second field effect transistor with an end of described resistance and an end of described first electric capacity, the grid of described the 4th field effect transistor, the grid of described the 6th field effect transistor, the drain electrode of drain electrode and described the 11 field effect transistor links to each other.
5. charge pump circuit as claimed in claim 4 is characterized in that: described output links to each other with the other end of the drain electrode of described second field effect transistor, the drain electrode of described the 7th field effect transistor, described resistance and an end of described second electric capacity.
6. charge pump circuit as claimed in claim 5, it is characterized in that: described charge pump circuit also comprises a power end, and described power end links to each other with the source class of the source class of the source class of a backward end of described current source, described first field effect transistor, described the 3rd field effect transistor, described the 5th field effect transistor, the grid of described the tenth field effect transistor, the grid of described the 12 field effect transistor, the grid of described the 14 field effect transistor, the other end of described first electric capacity and the other end of described second electric capacity.
7. charge pump circuit as claimed in claim 6, it is characterized in that: described charge pump circuit also comprises a ground end, holds with the source class of the grid of the grid of described the 3rd field effect transistor, described the 5th field effect transistor, described the 8th field effect transistor, the source class of described the tenth field effect transistor, the source class of described the 12 field effect transistor and the source class of described the 14 field effect transistor to link to each other describedly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101825154A CN102255501A (en) | 2011-07-01 | 2011-07-01 | Charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101825154A CN102255501A (en) | 2011-07-01 | 2011-07-01 | Charge pump circuit |
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| Publication Number | Publication Date |
|---|---|
| CN102255501A true CN102255501A (en) | 2011-11-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101825154A Pending CN102255501A (en) | 2011-07-01 | 2011-07-01 | Charge pump circuit |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6771114B2 (en) * | 2001-09-10 | 2004-08-03 | Nec Electronics Corporation | Charge pump current compensating circuit |
| CN101546956A (en) * | 2008-03-26 | 2009-09-30 | 英飞凌科技股份有限公司 | Self-regulated charge pump with loop filter |
| CN101572481A (en) * | 2009-06-11 | 2009-11-04 | 和芯微电子(四川)有限公司 | Charge pump circuit |
| CN102006063A (en) * | 2009-09-02 | 2011-04-06 | 中国科学院微电子研究所 | Autotracking switch type charge pump for phase lock loop |
| CN202111688U (en) * | 2011-07-01 | 2012-01-11 | 四川和芯微电子股份有限公司 | Charge pump circuit |
-
2011
- 2011-07-01 CN CN2011101825154A patent/CN102255501A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6771114B2 (en) * | 2001-09-10 | 2004-08-03 | Nec Electronics Corporation | Charge pump current compensating circuit |
| CN101546956A (en) * | 2008-03-26 | 2009-09-30 | 英飞凌科技股份有限公司 | Self-regulated charge pump with loop filter |
| CN101572481A (en) * | 2009-06-11 | 2009-11-04 | 和芯微电子(四川)有限公司 | Charge pump circuit |
| CN102006063A (en) * | 2009-09-02 | 2011-04-06 | 中国科学院微电子研究所 | Autotracking switch type charge pump for phase lock loop |
| CN202111688U (en) * | 2011-07-01 | 2012-01-11 | 四川和芯微电子股份有限公司 | Charge pump circuit |
Non-Patent Citations (4)
| Title |
|---|
| CN-QJ: "MJ螺纹紧固件1100MPa/235℃带垫圈及沉孔的六角自锁螺母", 《中华人民共和国航空航天工业部航天工业标准》 * |
| 刘新社，等: "《果蔬贮藏与加工技术》", 31 August 2009, 化学工业出版社 * |
| 国家机械工业局: "玻璃转子流量计 JB/T 9255-1999", 《中华人民共和国机械行业标准》 * |
| 罗云波，等: "《园艺产品贮藏加工学 加工篇》", 31 May 2011, 中国农业大学出版社 * |
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Address after: 610041 Sichuan city of Chengdu province high tech Zone Kyrgyzstan Road 33 block A No. 9 Applicant after: IPGoal Microelectronics (Sichuan) Co., Ltd. Address before: 402 room 7, building 610041, incubator Park, hi tech Zone, Sichuan, Chengdu Applicant before: IPGoal Microelectronics (Sichuan) Co., Ltd. |
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Application publication date: 20111123 |