CN102244014A - Manufacturing method of stackable package structure - Google Patents
Manufacturing method of stackable package structure Download PDFInfo
- Publication number
- CN102244014A CN102244014A CN2011101622554A CN201110162255A CN102244014A CN 102244014 A CN102244014 A CN 102244014A CN 2011101622554 A CN2011101622554 A CN 2011101622554A CN 201110162255 A CN201110162255 A CN 201110162255A CN 102244014 A CN102244014 A CN 102244014A
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- Prior art keywords
- carrier
- viscose
- manufacture method
- wafer
- crystal grain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The invention relates to a manufacturing method for a stackable package structure. The manufacturing method comprises the following steps of: (a) arranging a first carrier on a first surface of a wafer, wherein the wafer comprises the first surface, a second surface and a plurality of conduction columns, and the second surface is opposite to the first surface; (b) arranging a second carrier on the second surface; (c) removing the first carrier; (d) arranging a plurality of crystalline grains on the first surface; (e) removing the second carrier; and (f) cutting the wafer to form the stackable package structure. By using the second carrier, a crystalline grain to wafer process can be performed, so that the process time is shortened, the process is simplified and the product yield is increased.
Description
Technical field
The present invention is about a kind of manufacture method of encapsulating structure, in detail, and about a kind of manufacture method of stack type encapsulation structure.
Background technology
Known wafer with several conduction columns (Conductive Via) structure, its active surface sticks a carrier, is beneficial to finish the structure of this wafer.Again the back side of this wafer is adhered to all rubber tapping bands of a framework, to remove this carrier; Then, this active surface with this wafer changes all rubber tapping bands that are labelled to another framework again, is several first crystal grain to cut this wafer.Afterwards, at least one first crystal grain is arranged at a substrate, storehouse second crystal grain is to this first crystal grain, to form compound crystal grain again.Encapsulate at least one compound crystal grain and this substrate at last, to form stack type encapsulation structure.
The manufacture method of known stack type encapsulation structure needs the secondary commentaries on classics to be labelled to different frameworks, may cause fragmentation.Behind the cutting crystal wafer, carry out the storehouse of crystal grain more in addition, make whole technology comparatively complicated crystal grain.
Therefore, be necessary to provide a kind of manufacture method of stack type encapsulation structure, to address the above problem.
Summary of the invention
The invention provides a kind of manufacture method of stack type encapsulation structure, comprise: the first surface of one first carrier in a wafer (a) is set, wherein this wafer comprises this first surface, a second surface and several conduction columns, and this second surface is with respect to this first surface; (b) one second carrier is set in this second surface; (c) remove this first carrier; (d) several crystal grain are set in this first surface; (e) remove this second carrier; Reach and (f) cut this wafer, to form stack type encapsulation structure.
Utilize this second carrier, can carry out crystal grain, to shorten the process time, simplify technology and to improve the technology yield to wafer (chip to wafer) technology.
Description of drawings
The schematic diagram of first embodiment of the manufacture method of Fig. 1 to 18 demonstration stack type encapsulation structure of the present invention; And
The schematic diagram of second embodiment of the manufacture method of Figure 19 to 22 demonstration stack type encapsulation structure of the present invention.
Embodiment
Referring to figs. 1 to 18, the schematic diagram of first embodiment of the manufacture method of demonstration stack type encapsulation structure of the present invention.With reference to figure 1, provide a wafer 21.This wafer 21 comprises a first surface 211, a second surface 212 and several holes 214.In the present embodiment, this wafer 21 is a silicon substrate, and these holes 214 are blind hole, and is opened on this first surface 211.In the present embodiment, this first surface 211 is an active surface and comprises some driving components (not illustrating) that this second surface 212 is a back side.
With reference to figure 2, (for example: pi (Polyimide form an insulating material 221, PI), epoxy resin (Epoxy), benzocyclobutene (Benzocyclobutene, BCB) etc. non-conductive macromolecule also or inorganic insulating material, for example: silicon dioxide (silicon dioxide (SiO
2)) on the sidewall of these holes 214, and make several central channels.Afterwards, insert an electric conducting material 222 (for example copper metal) and in these central channels, reach formation one first protective layer (Passivation Layer) 26 in this first surface 211.The material of this first protective layer 26 is non-conductive macromolecular material; for example: pi (Polyimide, PI), epoxy resin (Epoxy), benzocyclobutene (Benzocyclobutene, BCB) etc.; also or inorganic insulating material, for example: silicon dioxide (silicon dioxide (SiO
2)).Then carry out lithography process, forming at least one opening, and appear these conduction columns 223.The size of this opening and position can be defined by employed light shield in the lithography process.Form a first metal layer 27 again on this first protective layer 26 and in this opening, to contact these conduction columns 223 and those driving components (not illustrating).Afterwards, turn over turnback.
With reference to figure 3, one first carrier 31 this first surface 211 in this wafer 21 is set.In the present embodiment, utilize one first viscose 33 to make this first carrier 31 attach to this first surface 211.Removing partly with grinding and/or etching mode, this second surface 212 make these holes 214 become several perforations 213, and these electric conducting materials 222 becomes several conduction columns (Conductive Via) 223 with this wafer 21 of thinning.
With reference to figure 4, form one second protective layer (Passivation Layer) 23 in this second surface 212.This second protective layer 23 is non-conductive macromolecular material; for example: pi (Polyimide, PI), epoxy resin (Epoxy), benzocyclobutene (Benzocyclobutene, BCB) etc.; also or inorganic insulating material, for example: silicon dioxide (silicon dioxide (SiO
2)).In the present embodiment; this second protective layer 23 is a photosensitive macromolecular material; for example be that (Benzocyclobutene BCB), and utilizes rotary coating (Spin Coating) or spraying coating (Spray Coating) mode to form this second protective layer 23 to benzocyclobutene.
With reference to figure 5, carry out lithography process, forming at least one opening 231, and appear these conduction columns 223.The size of this opening 231 and position can be defined by employed light shield in the lithography process.
With reference to figure 6, form one second metal level 24 on this second protective layer 23 and in this opening 231, to contact these conduction columns 223.Afterwards, form several projections 25 on this second metal level 24.In the present embodiment, this second metal level 24 can be a rerouting layer (RDL), makes these projections 25 change it according to circuit design the position is set.
With reference to figure 7, one second carrier 32 this second surface 212 in this wafer 21 is set.In the present embodiment, utilize one second viscose 34 to make this second carrier 32 attach to this second surface 212.
With reference to figure 8, remove this first carrier 31.In the present embodiment, this first viscose 33 is a cryogenic separation glue material, and this second viscose 34 is a high temperature separation gel material.When the dispergation temperature of this first viscose 33 is T
1℃, and the dispergation temperature of this second viscose 34 is T
2℃ the time, T
1Should be less than T
2, preferable T
2〉=T
1+ 40 ℃.For example: the dispergation temperature T of this first viscose 33
1Be about 180 ℃ to about 200 ℃, the dispergation temperature T of this second viscose 34
2Be at least 220 ℃ to about 240 ℃.Therefore, arrive the dispergation temperature T of this first viscose 33 when heating-up temperature
1The time, can make this first viscose, 33 dispergation, separate this first carrier 31, and do not influence the supportive of this second carrier 32.
At other embodiment, the dispergation mode of this first viscose 33 is different with the dispergation mode of this second viscose 34.For example the material of this first viscose 33 is X5000 or the X5300 of Sumitomo Chemical (SUMITOMO CHEMICAL), it is solvent dispergation type viscose, be dissolvable in water γ-Ding Suan lactone (GBL, gamma-Butyrolactone) also or in the monomethyl ether propylene glycol acetic acid esters (PGMEA, Propylene Glycol Monomethyl Ether Acetate); And the material of this second viscose 34 can be ultraviolet light dispergation type viscose, for example is the SELFA film of ponding chemistry (SEKISUI CHEMICAL), can be under the irradiation of ultraviolet light dispergation.Thereby can utilize one first strip step, and for example be that this first viscose 33 is immersed in one first solvent, removing this first carrier 31, and do not influence the supportive of this second carrier 32.
At other embodiment, the use that also can see through barrier film assists to remove first carrier, please refer to Fig. 9 to Figure 13, and it shows that the present invention utilizes barrier film to remove the difference enforcement aspect schematic diagram of first carrier.With reference to figure 9, one first barrier film 41 is set in 33 of this first carrier 31 and this first viscoses, in the present embodiment, the adhesion that this first viscose 33 and this first barrier film are 41 is less than the adhesion of 31 in this first viscose 33 and this first carrier, and the area of this first barrier film 41 is less than the area of this first carrier 31; And one second barrier film 42 being set in 34 of this second carrier 32 and this second viscoses, the area of this second barrier film 42 is less than the area of this first barrier film 41, as shown in figure 10.Distance when between the edge of the edge of this first barrier film 41 and this first carrier 31 is X
1Millimeter, and the distance between the edge of the edge of this second barrier film 42 and this second carrier 32 is X
2During millimeter, X
1Should be less than X
2, preferable X
2〉=X
1+ 2 millimeters (mm).
With reference to Figure 11, in the present embodiment, the material of this first viscose 33 can be identical with the material of this second viscose 34, is all solvent dispergation type viscose.After this first viscose 33 and this second viscose 34 are immersed a solvent, because of colloidal sol speed identical, and the area of this second barrier film 42 is less than the area of this first barrier film 41, thus can manifest this first barrier film 41 earlier because of the viscose dissolving, and do not appear this second barrier film 42 this moment.At this moment because a little less than the adhesion of 41 of this first viscose 33 and this first barrier films, but thereby delamination this first viscose 33 and this first barrier film 41 and this first carrier 31, and do not influence the supportive of this second carrier 32, as shown in figure 12.
With reference to Figure 13, be another enforcement aspect of the present invention, this enforcement aspect and above-mentioned enforcement aspect difference are, this first barrier film 41 only is set in 33 of this first carrier 31 and this first viscoses, this second barrier film is not set between this second carrier and this second viscose, similarly, also removable this first carrier 31 and this first barrier film 41, and do not influence the supportive of this second carrier 32.
With reference to Figure 14, after removing this first carrier 31, can carry out a viscose and remove step, utilize solvent to remove the first residual viscose 33 clean, afterwards, several crystal grain 51,52 are set in this first surface 211, each crystal grain (is the example explanation with crystal grain 51) comprises several weld pads 511, copper post (Copper Pillar) 512 and scolder 513, in order to electrically connect with the first metal layer 27.Utilize this second carrier, can carry out above-mentioned crystal grain, to shorten the process time, simplify technology and to improve the technology yield to wafer (chip to wafer) technology.
With reference to Figure 15, these first surface 211 to one frameworks 61 of this wafer 21 are set, this framework 61 comprises all rubber tapping band (Dicing tape) 611, these crystal grain 51,52 attach to this dicing tape 611.
With reference to Figure 16, remove this second carrier 32.In the present embodiment, as mentioned above, can be heated to the dispergation temperature of this second viscose 34, so that these second viscose, 34 dispergation separate this second carrier 32.
At other embodiment, because the material of this second viscose 34 is different with the material of this first viscose 33.Can utilize one second strip step to remove this second carrier 32.Perhaps, this second carrier 32 and this second viscose 34 are immersed one second solvent, to remove this second carrier 32.
In addition, this second viscose 34 can be a ultraviolet light dispergation type two-sided tape, has the characteristic that tackness reduces under UV-irradiation, for example is the SELFA film of ponding chemistry (SEKISUI CHEMICAL), and this second carrier 32 is a transparent carrier, for example is glass.Utilize this second carrier 32 of UV-irradiation, because this second carrier 32 be transparent carrier, and this second viscose 34 has the characteristic of tackness reduction under UV-irradiation, so removable this second viscose 34 and this second carrier 32.Afterwards, cut this wafer 21, to form several compound crystal grain 62 according to line of cut.
With reference to Figure 17, at least one compound crystal grain 62 to one substrates 63 are set.Afterwards, encapsulate at least one compound crystal grain 62 and this substrate 63, to form stack type encapsulation structure 60, as shown in figure 18.
Referring to figures 19 through 22, the schematic diagram of second embodiment of the manufacture method of demonstration stack type encapsulation structure of the present invention.The method of second embodiment before the step that removes this first carrier of the manufacture method of stack type encapsulation structure of the present invention is identical with first embodiment of the manufacture method of stack type encapsulation structure of the present invention, no longer narration.
With reference to Figure 19, after removing this first carrier, several crystal grain 71,72 are set in this first surface 211, each crystal grain (is the example explanation with crystal grain 71) comprises several weld pads 711, copper post 712 and scolder 713, in order to electrically connect with the first metal layer 27.Then, encapsulate these crystal grain 71,72 and this first surface 211, utilize a sealing 75 to coat these crystal grain 71,72 and this first surface 211.Utilize this second carrier 32, can carry out above-mentioned crystal grain, to shorten the process time, simplify technology and to improve the technology yield to wafer (chip to wafer) technology.
With reference to Figure 20, remove this second carrier 32.The method that removes this second carrier of second embodiment of the invention is identical with the invention described above first embodiment, no longer narration.
With reference to Figure 21, this sealing 75 to one frameworks 76 are set, this framework 76 comprises that all rubber tapping are with 761, this sealing 75 attaches to this dicing tape 761.Cut this wafer 21 and this sealing 75 according to line of cut, to form stack type encapsulation structure 80, as shown in figure 22.
According to the manufacture method of stack type encapsulation structure of the present invention, utilize this second carrier, can carry out above-mentioned crystal grain to wafer (chip to wafer) technology, to shorten the process time, simplify technology and to improve the technology yield.And utilize the manufacture method of stack type encapsulation structure of the present invention need not be labelled to different frameworks,, further improve the technology yield so can reduce the possibility of fragmentation as the commentaries on classics of known method secondary.
Only the foregoing description only is explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, practise the foregoing description being made amendment and changing and still do not take off spirit of the present invention in the personage of this technology.Interest field of the present invention should be listed as claims.
Claims (12)
1. the manufacture method of a stack type encapsulation structure comprises:
(a) first surface of one first carrier in a wafer is set, wherein this wafer comprises this first surface, a second surface and several conduction columns, and this second surface is with respect to this first surface;
(b) one second carrier is set in this second surface;
(c) remove this first carrier;
(d) several crystal grain are set in this first surface;
(e) remove this second carrier; And
(f) cut this wafer, to form stack type encapsulation structure.
2. manufacture method as claimed in claim 1 wherein in this step (a), utilizes one first viscose to make this first carrier attach to this first surface; In this step (b), utilize one second viscose to make this second carrier attach to this second surface.
3. manufacture method as claimed in claim 2, wherein this first viscose is cryogenic separation glue material and has one first dispergation temperature T
1℃, this second viscose is a high temperature separation gel material, and has one second dispergation temperature T
2℃, this first dispergation temperature T
1℃ be lower than this second dispergation temperature T
2℃.
4. manufacture method as claimed in claim 3, wherein 1 ℃ of this first dispergation temperature T and this second dispergation temperature T
2℃ relational expression be T
2〉=T
1+ 40 ℃.
5. manufacture method as claimed in claim 2, wherein the material of this first viscose is different with the material of this second viscose.
6. manufacture method as claimed in claim 5 wherein in this step (c), utilizes one first strip step to remove this first carrier; In this step (e), utilize one second strip step to remove this second carrier.
7. manufacture method as claimed in claim 5 wherein in this step (c), immerses one first solvent with this first carrier and this first viscose, to remove this first carrier; In this step (e), this second carrier and this second viscose are immersed one second solvent, to remove this second carrier.
8. manufacture method as claimed in claim 5 wherein in this step (e), is utilized this second carrier of UV-irradiation, to remove this second viscose and this second carrier.
9. manufacture method as claimed in claim 2, wherein in this step (a), other comprises that one is provided with the step of one first barrier film between this first carrier and this first viscose, the area of this first barrier film is less than the area of this first viscose.
10. manufacture method as claimed in claim 9, wherein in this step (b), other comprises that one is provided with the step of one second barrier film between this second carrier and this second viscose, the area of this second barrier film is less than the area of this first barrier film.
11. manufacture method as claimed in claim 1 is wherein preceding in this step (e), other comprises that one is provided with the step of this first surface to one framework of this wafer, and this framework comprises all rubber tapping bands, and these crystal grain attach to this dicing tape; In this step (f), cut and form several compound crystal grain behind this wafer, at least one compound crystal grain to one substrate is set, and encapsulates at least one compound crystal grain and this substrate, to form stack type encapsulation structure.
12. manufacture method as claimed in claim 1, wherein after this step (d), other comprises the step of these crystal grain of encapsulation and this first surface, utilizes these crystal grain of a sealant covers and this first surface; After this step (e), other comprises that one is provided with the step of this sealing to one framework, and this framework comprises all rubber tapping bands, and this sealing attaches to this dicing tape; In this step (f), cut this wafer and this sealing, to form stack type encapsulation structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101622554A CN102244014B (en) | 2011-06-08 | 2011-06-08 | Manufacturing method of stackable package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101622554A CN102244014B (en) | 2011-06-08 | 2011-06-08 | Manufacturing method of stackable package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102244014A true CN102244014A (en) | 2011-11-16 |
| CN102244014B CN102244014B (en) | 2013-11-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101622554A Active CN102244014B (en) | 2011-06-08 | 2011-06-08 | Manufacturing method of stackable package structure |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064092A (en) * | 2010-10-26 | 2011-05-18 | 日月光半导体制造股份有限公司 | Carrier separation method for semiconductor technology |
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2011
- 2011-06-08 CN CN2011101622554A patent/CN102244014B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064092A (en) * | 2010-10-26 | 2011-05-18 | 日月光半导体制造股份有限公司 | Carrier separation method for semiconductor technology |
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| CN102244014B (en) | 2013-11-20 |
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