CN102236068A - Method and device for testing chip - Google Patents
Method and device for testing chip Download PDFInfo
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- CN102236068A CN102236068A CN2010101653543A CN201010165354A CN102236068A CN 102236068 A CN102236068 A CN 102236068A CN 2010101653543 A CN2010101653543 A CN 2010101653543A CN 201010165354 A CN201010165354 A CN 201010165354A CN 102236068 A CN102236068 A CN 102236068A
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Abstract
The invention provides a method and a device for testing a chip. The method is used for automatic test equipment (ATE) and comprises the following steps of: reading a test vector source file in a memory of the ATE, and displaying a list of pin description information in the test vector source file; deleting pin description information, which is not actually input or output, in the list by using a deletion module of a source file editor; storing the modified test vector source file; and operating the modified test vector source file by using the ATE to test the chip, so that resources occupied by the pin description information which is not actually actual input or output in the test are saved. By the method and the device, the resources of the ATE can be saved, test efficiency is improved, and the technical problems that the test vector source file consumes a large quantity of time and resources and the test efficiency is low in the prior art are solved.
Description
Technical field
The present invention relates to the ATE (automatic test equipment) of chip, particularly relate to a kind of method and apparatus of chip testing.
Background technology
ATE (Automatic Test Equipment, ATE (automatic test equipment)) is a kind of equipment that carries out device, circuit board and chip testing by computer control.It replaces hand labor by computer programming, robotization finish cycle tests.
ATE can be divided into following several types: digital detecting system, linear unit test macro, simulated testing system, memory testing system, board test system, mixed signal test system, SOC (System on Chip, an integrated complete system in a chip) test macro.
The exploitation of ATE is from simple Devices, low pin number, low speed test macro (10MHz, 64pins) to moderate quatity pin, middling speed test macro (40MHz, 256pins) to high number of pins, (surpass 100MHz at a high speed, 1024pins) also finally carry out the transition to present SoC test macro (1024pin, surpass 400MHz, and possess simulation, memory test ability).Following test system and test speed will be above 1.6GHz, and time sequence precision and is integrated in a test macro with numeral, simulation, storer and RF power of test in the hundreds of nano-seconds.The cost of such test macro will be very high, therefore need the device detection that uses one or more test table to walk abreast.In order to reduce testing cost, will add self testing circuit in the chip.Based on the consideration that reduces cost of testing system, modular test macro will replace general test macro simultaneously.
General A TE can be by one group of passage with certain internal memory degree of depth, and a series of timing sequencers and a plurality of power supply are formed.These resources be by load board the chip pin of signal excitation to the chip carrier socket, each pin of ATE test macro has independently test resource.In the time of test, each pin has the corresponding signal that inputs or outputs, and constitutes test vector by these signals, carries out the test of different chip functions.
Device speed has reached 1.6GHz at present, and number of pins reaches 1024, and all circuit all are integrated into single chip.Therefore the test vector source file volume that is made of the test vector at pin is big especially, even exceedance G bytes, can be unable to do what one wishes when revising the parameter of the inside with the ordinary file editing machine, usually consuming time huge, therefore, ATE has expended a large amount of time and resource when the modification of carrying out the test vector source file and configuration, caused testing efficiency low.
Summary of the invention
The method and apparatus that the purpose of this invention is to provide a kind of chip testing, the resource that can save ATE improves testing efficiency, solves prior art test vector source file and has expended a large amount of time and resource, the technical matters that testing efficiency is low.
To achieve these goals, on the one hand, provide a kind of method of chip testing, be used for ATE (automatic test equipment), comprised the steps:
Read the test vector source file in the storer of described ATE (automatic test equipment), show the tabulation of the pin descriptor in the described test vector source file;
Deleting by the removing module of source file editing machine does not have the actual pin descriptor that inputs or outputs in the described tabulation;
Preserve amended test vector source file;
Move described amended test vector source file by described ATE (automatic test equipment) and carry out chip testing.
Preferably, in the above-mentioned method, described removing module by the source file editing machine also comprises before deleting the step that does not have the actual pin descriptor that inputs or outputs in the described tabulation:
Revise the test vector waveform of described test vector source file by the waveform modified module of described source file editing machine.
Preferably, in the above-mentioned method, described removing module by the source file editing machine also comprises before deleting the step that does not have the actual pin descriptor that inputs or outputs in the described tabulation:
Revise the operational code pattern of described test vector source file by the schema modification module of described source file editing machine.
Preferably, in the above-mentioned method, described removing module by the source file editing machine also comprises before deleting the step that does not have the actual pin descriptor that inputs or outputs in the described tabulation:
If described operational code pattern is a general mode, the test vector in the then described test vector source file is set to even number line.
To achieve these goals, the embodiment of the invention also provides a kind of device of chip testing, is used for ATE (automatic test equipment), comprising:
Read and display module, be used for: read the test vector source file of the storer of described ATE (automatic test equipment), show the tabulation of the pin descriptor in the described test vector source file;
The source file editing machine comprises removing module, and described removing module is used for: deleting described tabulation does not have the actual pin descriptor that inputs or outputs;
Preserve and execution module, be used for: preserve amended test vector source file, and move described amended test vector source file by described ATE (automatic test equipment) and carry out chip testing.
Preferably, in the above-mentioned device, described source file editing machine also comprises:
The waveform modified module is used to revise the test vector waveform of described test vector source file.
Preferably, in the above-mentioned device, described source file editing machine also comprises:
The schema modification module is used to revise the operational code pattern of described test vector source file.
Preferably, in the above-mentioned device, described schema modification module also is used for: if described operational code pattern is a general mode, the test vector in the then described test vector source file is set to even number line.
There is following technique effect at least in the present invention:
1) deletes by the removing module of source file editing machine and do not have the actual pin descriptor that inputs or outputs in the described tabulation, thereby the pin of these descriptor correspondences no longer takies the test resource of ATE (automatic test equipment), ATE (automatic test equipment) can be vacateed more test pin resource, thereby ATE (automatic test equipment) can be tested more chip simultaneously, has improved testing efficiency.
2) deletion does not have the actual pin descriptor that inputs or outputs, and has greatly reduced the size of test vector source file, and the memory consumption when having reduced operation test vector source file has improved travelling speed;
3) can revise the test vector waveform of described test vector source file automatically according to the title of user's input by the waveform modified module, thereby make the user revise this important parameter easily;
4) can pass through the schema modification module, revise the operational code pattern of described test vector source file, thereby make the user revise this important parameter easily.
5) when the operational code pattern is general mode, test vector in the described automatically test vector source file of schema modification module is set to even number line, because general mode two row just can be formed a complete waveform cycle, so this automatic modification can be avoided makeing mistakes.
6) the present invention has not only improved the testing efficiency of ATE (automatic test equipment), can also allow the Test Engineer that the some of them important parameter is revised fast and accurately, thereby can significantly reduce the Production Time of chip sample, shortens the chip testing procedure development cycle.
Description of drawings
The flow chart of steps of the method that Fig. 1 provides for the embodiment of the invention;
The flow chart of steps of editor's test vector source file that Fig. 2 provides for the embodiment of the invention;
The structural drawing of the device that Fig. 3 provides for the embodiment of the invention.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention is clearer, specific embodiment is described in detail below in conjunction with accompanying drawing.
The flow chart of steps of the method that Fig. 1 provides for the embodiment of the invention; As shown in the figure, the embodiment of the invention provides a kind of method of chip testing, is used for ATE (automatic test equipment), wherein, comprises the steps:
Also comprise before the described step 102: the test vector waveform of revising described test vector source file by the waveform modified module of described source file editing machine; Revise the operational code pattern of described test vector source file by the schema modification module of described source file editing machine.Wherein, if described operational code pattern is a general mode, the test vector in the then described test vector source file is set to even number line.
The flow chart of steps of editor's test vector source file of the method that Fig. 2 provides for the embodiment of the invention; As shown in the figure, the process of editor's test vector source file is as follows:
As seen, the present invention can revise fast at the parameter that the Test Engineer is concerned about, it has following function:
1) can revise the tset name of test vector source file fast, opcode mode.
2) delete unwanted output pin, and can stop deletion to comprise the pin in input cycle;
3) can arrange putting in order of pin;
4) title of modification pin
5) if opcode mode is normal (common) pattern, test vector is set to even number line.
The embodiment of the invention also provides a kind of device of chip testing, is used for ATE (automatic test equipment), and it comprises:
Read and display module 310, be used for: read the test vector source file of the storer of described ATE (automatic test equipment), show the tabulation of the pin descriptor in the described test vector source file;
Source file editing machine 320 comprises removing module 321, and described removing module is used for: deleting described tabulation does not have the actual pin descriptor that inputs or outputs;
Preserve and execution module 330, be used for: preserve amended test vector source file, and move described amended test vector source file by described ATE (automatic test equipment) and carry out chip testing, there is not the actual shared resource of pin descriptor that inputs or outputs described in the test thereby save.
Described source file editing machine also comprises: waveform modified module 322 is used to revise the test vector waveform of described test vector source file; Schema modification module 323 is used to revise the operational code pattern of described test vector source file, if described operational code pattern is a general mode, the test vector in the then described test vector source file is set to even number line.
As from the foregoing, the embodiment of the invention has following advantage:
1) deletes by the removing module of source file editing machine and do not have the actual pin descriptor that inputs or outputs in the described tabulation, thereby the pin of these descriptor correspondences no longer takies the test resource of ATE (automatic test equipment), ATE (automatic test equipment) can be vacateed more test pin resource, thereby ATE (automatic test equipment) can be tested more chip simultaneously, has improved testing efficiency.
2) deletion does not have the actual pin descriptor that inputs or outputs, and has greatly reduced the size of test vector source file, and the memory consumption when having reduced operation test vector source file has improved travelling speed;
3) can revise the test vector waveform of described test vector source file automatically according to the title of user's input by the waveform modified module, thereby make the user revise this important parameter easily;
4) can pass through the schema modification module, revise the operational code pattern of described test vector source file, thereby make the user revise this important parameter easily.
5) when the operational code pattern is general mode, test vector in the described automatically test vector source file of schema modification module is set to even number line, because general mode two row just can be formed a complete waveform cycle, so this automatic modification can be avoided makeing mistakes.
6) the present invention has not only improved the testing efficiency of ATE (automatic test equipment), can also allow the Test Engineer that the some of them important parameter is revised fast and accurately, thereby can significantly reduce the Production Time of chip sample, shortens the chip testing procedure development cycle.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (8)
1. the method for a chip testing is used for ATE (automatic test equipment), it is characterized in that, comprises the steps:
Read the test vector source file in the storer of described ATE (automatic test equipment), show the tabulation of the pin descriptor in the described test vector source file;
Deleting by the removing module of source file editing machine does not have the actual pin descriptor that inputs or outputs in the described tabulation;
Preserve amended test vector source file; Move described amended test vector source file by described ATE (automatic test equipment) and carry out chip testing.
2. method according to claim 1 is characterized in that, described removing module by the source file editing machine also comprises before deleting the step that does not have the actual pin descriptor that inputs or outputs in the described tabulation:
Revise the test vector waveform of described test vector source file by the waveform modified module of described source file editing machine.
3. method according to claim 1 is characterized in that, described removing module by the source file editing machine also comprises before deleting the step that does not have the actual pin descriptor that inputs or outputs in the described tabulation:
Revise the operational code pattern of described test vector source file by the schema modification module of described source file editing machine.
4. method according to claim 3 is characterized in that, described removing module by the source file editing machine also comprises before deleting the step that does not have the actual pin descriptor that inputs or outputs in the described tabulation:
If described operational code pattern is a general mode, the test vector in the then described test vector source file is set to even number line.
5. the device of a chip testing is used for ATE (automatic test equipment), it is characterized in that, comprising:
Read and display module, be used for: read the test vector source file of the storer of described ATE (automatic test equipment), show the tabulation of the pin descriptor in the described test vector source file;
The source file editing machine comprises removing module, and described removing module is used for: deleting described tabulation does not have the actual pin descriptor that inputs or outputs;
Preserve and execution module, be used for: preserve amended test vector source file, and move described amended test vector source file by described ATE (automatic test equipment) and carry out chip testing.
6. device according to claim 5 is characterized in that, described source file editing machine also comprises:
The waveform modified module is used to revise the test vector waveform of described test vector source file.
7. device according to claim 5 is characterized in that, described source file editing machine also comprises:
The schema modification module is used to revise the operational code pattern of described test vector source file.
8. device according to claim 7 is characterized in that, described schema modification module also is used for: if described operational code pattern is a general mode, the test vector in the then described test vector source file is set to even number line.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104298590A (en) * | 2013-07-16 | 2015-01-21 | 爱德万测试(新加坡)私人有限公司 | Rapid semantic processor for pin-based APG (Automatic Pattern Generator) |
| CN109633421A (en) * | 2018-11-27 | 2019-04-16 | 珠海欧比特宇航科技股份有限公司 | A kind of test method of SOC chip, device, equipment and storage medium |
| CN111044877A (en) * | 2018-10-12 | 2020-04-21 | 好修科技股份有限公司 | Circuit board editing and testing system and method |
| CN111596200A (en) * | 2020-05-25 | 2020-08-28 | 上海岱矽集成电路有限公司 | Integrated circuit tester |
| CN112630622A (en) * | 2020-12-17 | 2021-04-09 | 珠海芯网测控有限公司 | Method and system for pattern compiling and downloading test of ATE (automatic test equipment) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104298590A (en) * | 2013-07-16 | 2015-01-21 | 爱德万测试(新加坡)私人有限公司 | Rapid semantic processor for pin-based APG (Automatic Pattern Generator) |
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| CN111596200A (en) * | 2020-05-25 | 2020-08-28 | 上海岱矽集成电路有限公司 | Integrated circuit tester |
| CN112630622A (en) * | 2020-12-17 | 2021-04-09 | 珠海芯网测控有限公司 | Method and system for pattern compiling and downloading test of ATE (automatic test equipment) |
| CN112630622B (en) * | 2020-12-17 | 2022-05-31 | 珠海芯业测控有限公司 | Method and system for pattern compiling, downloading and testing of ATE (automatic test equipment) |
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| CN102236068B (en) | 2015-11-25 |
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Address after: 214028 national integrated circuit design (21-1), Changjiang Road, New District, Jiangsu, Wuxi, China, China (610) Patentee after: WUXI ZHONGGAN MICROELECTRONIC CO., LTD. Address before: National integrated circuit design Park (source building), 21-1 Changjiang Road, New District, Jiangsu, Wuxi, China 610 Patentee before: Wuxi Vimicro Co., Ltd. |