CN109633421A - A kind of test method of SOC chip, device, equipment and storage medium - Google Patents
A kind of test method of SOC chip, device, equipment and storage medium Download PDFInfo
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- CN109633421A CN109633421A CN201811426321.2A CN201811426321A CN109633421A CN 109633421 A CN109633421 A CN 109633421A CN 201811426321 A CN201811426321 A CN 201811426321A CN 109633421 A CN109633421 A CN 109633421A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a kind of test method of SOC chip, device, equipment and storage mediums.Simulation document is generated according to all functional informations to be measured of versatile interface and corresponding default test information, the simulation document is converted into be used for the test vector information of tester table, and is detecting through the test pattern and signal pins information completion test in test vector information and is outputing test data.Improve testing efficiency.
Description
Technical field
The present invention relates to chip testing field, especially a kind of test method of SOC chip, device, equipment and storage are situated between
Matter.
Background technique
Currently, the stability of chip is for product as effect of the intelligent chip in sci-tech product is more and more important
Using most important, therefore chip is needed through stringent test before putting goods on the market to find existing defect.It is surveyed in chip
In examination field, traditional method, which mainly passes through, to be accomplished manually, lower by artificial usually efficiency, and it is easy to appear artificial mistakes
Accidentally.It is most of in current existing scheme to be tested using pin function of the test equipment to test chip, but this method
Once a kind of function can only be tested, when encountering versatile interface, need to carry out multi-pass operation, efficiency is more low.
Summary of the invention
For overcome the deficiencies in the prior art, the purpose of the present invention is to provide a kind of test methods of SOC chip, dress
It sets, equipment and storage medium, testing efficiency can be improved according to the test for completing SOC chip versatile interface in practical applications.
Technical solution used by the present invention solves the problems, such as it is:
In a first aspect, the present invention provides a kind of test methods of SOC chip, comprising the following steps:
All functional informations to be measured and corresponding default test information, generation for reading selected versatile interface emulate
File；
Simulation document is read, simulation document is converted into test vector information and is saved in the server；
After detecting the connection completion signal that tester table is sent, test vector information is sent to tester table by server
In；
The tester table reads test pattern and signal pins information in the test vector information, and execution test is simultaneously defeated
Test data corresponding to test pattern out.
Further, it after the test vector information is sent to tester table, is converted into according to the model of tester table readable
Vector file format.
Further, the signal pins information includes input data, output data, input pattern and the output of versatile interface
Mode.
Further, the test pattern includes DC parameter test, functional test and AC parameter test.
Further, before the execution is tested and exports test data corresponding to test pattern, further includes: according to selected
Test pattern read SOC chip corresponding to test parameter setting, and by test parameter setting be sent in SOC chip.
Further, in the file that the test data storage is specified into the test vector information.
Second aspect, the present invention also provides a kind of test devices of SOC chip, including following device:
Simulation document generation unit, for reading all functional informations to be measured of selected versatile interface and corresponding
Default test information, generates simulation document；
Simulation document is converted to test vector information simultaneously for reading simulation document by test vector information acquisition unit
It saves in the server；
Test vector information transmitting unit, after detecting that signal is completed in the connection of tester table transmission, server will
Test vector information is sent in tester table；
Test data acquiring unit reads the test pattern and letter in the test vector information for the tester table
Number foot information, executes to test and simultaneously exports test data corresponding to test pattern.
Further, further include following device:
Vector file format converting unit, for stating after test vector information is sent to tester table, according to tester table
Model be converted into readable vector file format；
Test parameter setting unit, for the test parameter according to corresponding to selected test pattern reading SOC chip
Setting, and test parameter setting is sent in SOC chip；
Test data storage unit, the file for specifying test data storage into the test vector information
In.
The third aspect, the present invention provides a kind of test equipment of SOC chip,
Memory including at least one control processor and for being communicated to connect at least one control processor；Storage
Device is stored with the instruction that can be executed by least one control processor, and instruction is executed by least one control processor, so that extremely
A few control processor is able to carry out the test method of SOC chip as described above.
Fourth aspect, the present invention provides a kind of computer readable storage medium, computer-readable recording medium storage has
Computer executable instructions, the test method that computer executable instructions are used to that computer to be made to execute SOC chip as described above.
5th aspect, the present invention also provides a kind of computer program product, the computer program product includes storage
Computer program on computer readable storage medium, the computer program include program instruction, when described program instructs
When being computer-executed, computer is made to execute the test method of SOC chip as described above.
The one or more technical solutions provided in the embodiment of the present invention at least have the following beneficial effects: that the present invention adopts
With a kind of test method of SOC chip, device, equipment and storage medium.All according to versatile interface believe to brake
Breath and corresponding default test information generate simulation document, and the simulation document is converted into be used for the test vector of tester table
Information, and detecting through the test pattern and signal pins information completion test in test vector information and exporting test number
According to.To the method compared with the prior art, multiple functional tests can be arranged simultaneously by simulation document in the present invention, to realize primary
It tests multi-functional, improves testing efficiency.
Detailed description of the invention
The invention will be further described with example with reference to the accompanying drawing.
Fig. 1 is a kind of flow chart of the test method for SOC chip that the embodiment of the present invention one provides；
Fig. 2 is a kind of detailed step figure of the test method for SOC chip that the embodiment of the present invention one provides；
Fig. 3 is a kind of structural schematic diagram of the test device of SOC chip provided by Embodiment 2 of the present invention；
Fig. 4 is a kind of structural schematic diagram of the test equipment for SOC chip that the embodiment of the present invention three provides.
Specific embodiment
Currently, the stability of chip is for product as effect of the intelligent chip in sci-tech product is more and more important
Using most important, therefore chip is needed through stringent test before putting goods on the market to find existing defect.It is surveyed in chip
In examination field, traditional method, which mainly passes through, to be accomplished manually, lower by artificial usually efficiency, and it is easy to appear artificial mistakes
Accidentally.It is most of in current existing scheme to be tested using pin function of the test equipment to test chip, but this method
Once a kind of function can only be tested, when encountering versatile interface, need to carry out multi-pass operation, efficiency is more low.
Based on this, present invention employs a kind of test method of SOC chip, device, equipment and storage mediums.According to more function
All functional informations to be measured of energy interface and corresponding default test information generate simulation document, and the simulation document is converted into
For the test vector information of tester table, and detecting through the test pattern and signal pins information in test vector information
It completes to test and output test data.To the method compared with the prior art, the present invention can be arranged simultaneously multiple by simulation document
Functional test is once tested multi-functional, improves testing efficiency to realize.
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that described herein, specific examples are only used to explain the present invention, not
For limiting the present invention.
It should be noted that each feature in the embodiment of the present invention can be combined with each other, in this hair if do not conflicted
Within bright protection scope.In addition, though having carried out functional module division in schematic device, shows patrol in flow charts
Sequence is collected, but in some cases, it can be shown in the sequence execution in the module division being different from device or flow chart
The step of out or describing.
In an embodiment of the present invention, the equipment that chip and tester table can be disposable type, chip are for SOC chip
It can.The embedded chip of preferred model S698PM in the present embodiment, the tester table of model J750EX.Based on J750EX
Tester table tests the phenomenon that can quickly and accurately note abnormalities to S698PM chip versatile interface, improves SOC chip test
Efficiency shortens test period, reduces testing cost, therefore the embedded chip of model S698PM is preferably used in the present embodiment
It is illustrated with the tester table of model J750EX.
Referring to Fig.1, the present invention provides a kind of test methods of SOC chip, comprising the following steps:
Step S1, read selected versatile interface all functional informations to be measured and corresponding default test information,
Generate simulation document；
Step S2 reads simulation document, and simulation document is converted to test vector information and is saved in the server；
Step S3, after detecting the connection completion signal that tester table is sent, test vector information is sent to by server
In tester table；
Step S4, the tester table read test pattern and signal pins information in the test vector information, execute
It tests and exports test data corresponding to test pattern.
Wherein, in the step S1 of the present embodiment, simulation document can be the file including any information, can be used to test
?.The functional and corresponding test information of versatile interface institute is preferably included in the present embodiment.As corresponding to versatile interface
Function it is more, therefore need to carry out the test of multiple parameters to a pin during the test, pass through simulation document at this time
It is functional to the institute of special pin to enumerate, and corresponding test method is set, then converting resulting test vector
It also will include corresponding multiple test methods in information, to realize that single tests multiple functions.
Wherein, in the step S2 of the present embodiment, the conversion of simulation document and test vector information can be arbitrary form
Conversion, it is readable to be able to satisfy tester table.Preferred simulation document is that Modelsim emulates resulting text in the present embodiment
Part, in order to the reading and conversion of J750EX tester table.
Wherein, in the step S3 of the present embodiment, the connection of tester table can be any form of connection, can make
S698PM chip and tester table establish connection.Preferably the address of S698PM chip, data, piece choosing are made in the present embodiment
Energy signal pins and J750EX tester table are electrically connected, and the power channel of supply pin and J750 tester table is electrically connected, and ground draws
The ground of foot and J750 tester table is electrically connected.The electrical connection of the S698PM chip and J750EX tester table is by turning
Fishplate bar is attached, and places S698PM chip by installing chip test base additional on pinboard.All IO of S698PM chip
Pin, power supply and ground pin are connect by chip test base with pinboard, and pinboard is placed into the mother on J750EX tester table
On plate, completes S698PM chip I/O foot, power supply and ground pin and connect respectively with the electrical of J750EX board channel, supply pin and ground
It connects.After the completion of connection, testboard sends connection to server and completes signal.
Wherein, in the step S4 of the present embodiment, each test pattern corresponds to a function of versatile interface, tests mould
It include map pins corresponding to S698PM chip, channel mapping, setting pin value, setting operating condition, definition in formula
S698PM chip input clock cycle defines S698PM chip signal foot time-constrain, determines parameter item to be measured.
Further, in another embodiment of the present invention, after the test vector information is sent to tester table, according to
The model of tester table is converted into readable vector file format.
Wherein, in the present embodiment, test vector information can be any form of reading in tester table, be able to achieve
Test.Test vector information is preferably converted into vector file format in the present embodiment, in order to tester table reading.
Further, in another embodiment of the present invention, the signal pins information includes the input number of versatile interface
According to, output data, input pattern and output mode.
Wherein, in the present embodiment, signal pins information may include various forms of information, preferred more function in the present embodiment
Input data, output data, input pattern and the output mode of energy interface, convenient for drawing for tester table identification S698PM chip
Foot, it is ensured that input and output it is correct.
Further, in another embodiment of the present invention, the test pattern includes DC parameter test, functional test
And AC parameter test.
Wherein, in the present embodiment, test pattern can be the test of arbitrary parameter, preferred DC parameter in the present embodiment
Test, functional test and AC parameter test, to realize the test in all directions of versatile interface.
Wherein, in the DC parameter test, using J750EX tester table measuring unit to versatile interface into
Row DC parameter test, the parameter tested specifically include: core power dynamic current Idd, core power quiescent current Idds,
I O power supply quiescent current Iddios inputs high/low level leakage current IIH/IIL, exports high/low level voltage VOH/VOL, short circuit
Output current IO S.
Preferably, include the input signal values that are provided according to functional mode of J750EX tester table in the functional test to
S698PM chip provides pumping signal, and S698PM chip makes corresponding function, then the letter that chip is exported according to pumping signal very much
Number value, compared with the output signal value stored in functional mode, thus complete to versatile interface functional test.
Preferably, the alternating-current parameter includes system clock to output delay time Tgrgpio0.
Further, in another embodiment of the present invention, the execution is tested and exports survey corresponding to test pattern
Before trying data, further includes: according to test parameter setting corresponding to selected test pattern reading SOC chip, and will test
Parameter setting is sent in SOC chip.
Wherein, in embodiments herein, the shared parameter set is the core voltage of S698PM chip, IO electricity
The value of pressure, input/output voltage, reference voltage；Wherein, AC parameter test and when functional test further include defining S698PM core
The input clock of piece defines the time-constrain of S698PM chip signal foot, the functional mode of multi-functional I/O port MFIO module is added
It is downloaded to the storage unit of J750EX tester table.
Further, in another embodiment of the present invention, the test data storage is into the test vector information
In specified file.
Wherein, in the present embodiment, test data can also pass through pre-set mode so that storage mode is manually specified
Specify storage mode, the file for the storage specified preferably in test vector information in the present embodiment.Due to test vector information
It is sent in tester table and is parsed, therefore specify the file of storage directly in test vector information, it can be more efficiently
Complete the mobile phone of test data.
With reference to Fig. 2, in addition, in another embodiment of the present invention, a kind of test method of SOC chip is additionally provided,
Specifically includes the following steps:
Step S3001 reads all functional informations to be measured and corresponding default test letter of selected multifunctional pin
Breath generates simulation document；
Step S3002 reads simulation document, and simulation document is converted to test vector information and is saved in the server；
Step S3003, after detecting the connection completion signal that tester table is sent, server sends test vector information
Into tester table；
Step S3004 is converted into readable vector file format according to the model of tester table；
Step S3005 according to test parameter setting corresponding to selected test pattern reading SOC chip, and will be surveyed
Examination parameter setting is sent in SOC chip；
Step S3006, the tester table read the input data of the functional interface in the test vector information, output
Data, input pattern and output mode, it is right that DC parameter test, functional test and AC parameter test institute are tested and export in execution
The test data answered；
Step S3007, will be in the test data storage file specified into the test vector information.
Referring to Fig. 3, the embodiment of the invention also provides a kind of test devices of SOC chip, fill in the test of the SOC chip
It sets in 1000, including but not limited to: simulation document generation unit 1100, test vector information acquisition unit 1200, test vector
Information transmitting unit 1300 and test data acquiring unit 1400.
Simulation document generation unit 1100 is used to read all functional informations to be measured of selected versatile interface and right
The default test information answered generates simulation document；
Simulation document is converted to test vector information for reading simulation document by test vector information acquisition unit 1200
And it saves in the server；
After test vector information transmitting unit 1300 is used to detect that signal to be completed in the connection that tester table is sent, server
Test vector information is sent in tester table；
Test data acquiring unit 1400 reads the test pattern in the test vector information for the tester table
With signal pins information, executes and test and export test data corresponding to test pattern.
Further, in another embodiment of the invention, further include but be not limited to:
Wherein, vector file format converting unit 1310 is for stating after test vector information is sent to tester table, according to
The model of tester table is converted into readable vector file format；
Test parameter setting unit 1410 is used for the test ginseng according to corresponding to selected test pattern reading SOC chip
Number setting, and test parameter setting is sent in SOC chip；
What test data storage unit 1420 was used to specify test data storage into the test vector information
In file.
It should be noted that by the test device of SOC chip in this present embodiment and the test side of above-mentioned SOC chip
Method is based on identical inventive concept, and therefore, the corresponding contents in embodiment of the method are equally applicable to present apparatus embodiment, herein not
It is described in detail again.
Referring to Fig. 4, the embodiment of the invention also provides a kind of test equipment of SOC chip, the test equipments of the SOC chip
200 can be any type of intelligent terminal, such as mobile phone, tablet computer, personal computer etc..
Specifically, the test equipment 200 of the SOC chip includes: one or more control processors 201 and memory 202,
In Fig. 4 by taking a control processor 201 as an example.
Control processor 201 can be connected with memory 202 by bus or other modes, to pass through bus in Fig. 4
For connection.
Memory 202 is used as a kind of non-transient computer readable storage medium, can be used for storing non-transient software program, non-
Transitory computer executable program and module, such as the corresponding program of the test equipment of the SOC chip in the embodiment of the present invention
Instruction/module, for example, simulation document generation unit 1100 and test vector information acquisition unit 1200 shown in Fig. 3.Control
Non-transient software program, instruction and the module that processor 201 is stored in memory 202 by operation, thereby executing SOC core
The various function application and data processing of the test device 1000 of piece, the i.e. survey of the SOC chip of realization above method embodiment
Method for testing.
Memory 202 may include storing program area and storage data area, wherein storing program area can store operation system
Application program required for system, at least one function；Storage data area can be stored to be made according to the test device 1000 of SOC chip
With the data etc. created.In addition, memory 202 may include high-speed random access memory, it can also include non-transient deposit
Reservoir, for example, at least a disk memory, flush memory device or other non-transient solid-state memories.In some embodiment party
In formula, it includes the memory remotely located relative to control processor 201 that memory 202 is optional, these remote memories can be with
By being connected to the network to the test equipment 200 of the SOC chip.The example of above-mentioned network includes but is not limited to internet, in enterprise
Portion's net, local area network, mobile radio communication and combinations thereof.
One or more of modules are stored in the memory 202, at by one or more of controls
When managing the execution of device 201, the test method of the SOC chip in above method embodiment is executed, for example, executing Fig. 1 described above
In method and step S1 to S4, realize Fig. 3 in unit 1100-1400 function.
The embodiment of the invention also provides a kind of computer readable storage medium, the computer-readable recording medium storage
There are computer executable instructions, which is executed by one or more control processors, for example, by Fig. 4
A control processor 201 execute, may make said one or multiple control processors 201 to execute in above method embodiment
The test method of SOC chip realize the unit in Fig. 3 for example, execute the method and step S1 to S4 in Fig. 1 described above
The function of 1100-1400.
The apparatus embodiments described above are merely exemplary, wherein described, unit can as illustrated by the separation member
It is physically separated with being or may not be, it can it is in one place, or may be distributed over multiple network lists
In member.Some or all of the modules therein can be selected to achieve the purpose of the solution of this embodiment according to the actual needs.
Through the above description of the embodiments, those skilled in the art can be understood that each embodiment can borrow
Help software that the mode of general hardware platform is added to realize.It will be appreciated by those skilled in the art that realizing in above-described embodiment method
All or part of the process is relevant hardware can be instructed to complete by computer program, and the program can be stored in one
In computer-readable storage medium, the program is when being executed, it may include such as the process of the embodiment of the above method.Wherein, institute
The storage medium stated can be magnetic disk, CD, read-only memory (ReadOnly Memory, ROM) or random access memory
(Random Access Memory, RAM) etc..
It is to be illustrated to preferable implementation of the invention, but the invention is not limited to above-mentioned embodiment party above
Formula, those skilled in the art can also make various equivalent variations on the premise of without prejudice to spirit of the invention or replace
It changes, these equivalent deformations or replacement are all included in the scope defined by the claims of the present application.
Claims (10)
1. a kind of test method of SOC chip, which comprises the following steps:
All functional informations to be measured and corresponding default test information, the generation emulation for reading selected versatile interface are literary
Part；
Simulation document is read, simulation document is converted into test vector information and is saved in the server；Detect tester table
After signal is completed in the connection of transmission, test vector information is sent in tester table by server；
The tester table reads test pattern and signal pins information in the test vector information, executes and tests and export survey
Test data corresponding to die trial formula.
2. a kind of test method of SOC chip according to claim 1, it is characterised in that: the test vector information hair
It send to tester table, readable vector file format is converted into according to the model of tester table.
3. a kind of test method of SOC chip according to claim 1, it is characterised in that: the signal pins information includes
Input data, output data, input pattern and the output mode of versatile interface.
4. a kind of test method of SOC chip according to claim 1, it is characterised in that: the test pattern includes straight
Flow parameter testing, functional test and AC parameter test.
5. a kind of test method of SOC chip according to claim 4, which is characterized in that the execution is tested and exported
Before test data corresponding to test pattern, further includes: according to test corresponding to selected test pattern reading SOC chip
Parameter setting, and test parameter setting is sent in SOC chip.
6. a kind of test method of SOC chip according to claim 1, it is characterised in that: the test data storage is arrived
In the file specified in the test vector information.
7. a kind of test device of SOC chip, which is characterized in that including following device:
Simulation document generation unit, for reading all functional informations to be measured of selected versatile interface and corresponding default
Information is tested, simulation document is generated；
Simulation document is converted to test vector information and saved by test vector information acquisition unit for reading simulation document
In the server；
Test vector information transmitting unit, after detecting that signal is completed in the connection of tester table transmission, server will be tested
Vector information is sent in tester table；
Test data acquiring unit reads test pattern and signal pins in the test vector information for the tester table
Information executes and tests and export test data corresponding to test pattern.
8. a kind of test device of SOC chip according to claim 7, which is characterized in that further include following device:
Vector file format converting unit, for stating after test vector information is sent to tester table, according to the type of tester table
Number it is converted into readable vector file format；
Test parameter setting unit is arranged for the test parameter according to corresponding to selected test pattern reading SOC chip,
And test parameter setting is sent in SOC chip；
Test data storage unit, for storing the test data in the file specified into the test vector information.
9. a kind of equipment, it is characterised in that: including at least one control processor and for being handled at least one described control
The memory of device communication connection；The memory is stored with the instruction that can be executed by least one described control processor, described
Instruction is executed by least one described control processor, so that at least one described control processor is able to carry out such as claim
A kind of described in any item test methods of SOC chip of 1-6.
10. a kind of computer readable storage medium, it is characterised in that: the computer-readable recording medium storage has computer can
It executes instruction, the computer executable instructions are for making computer execute a kind of SOC as claimed in any one of claims 1 to 6
The test method of chip.
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Cited By (6)
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| CN110045266A (en) * | 2019-04-23 | 2019-07-23 | 珠海欧比特宇航科技股份有限公司 | A kind of chip universal testing method and device |
| CN110321292A (en) * | 2019-08-12 | 2019-10-11 | 上海燧原智能科技有限公司 | Chip detecting method, device, electronic equipment and computer readable storage medium |
| CN111175637A (en) * | 2020-01-09 | 2020-05-19 | 深圳市正宇兴电子有限公司 | Optical SOC chip testing method and system based on function test |
| CN111273153A (en) * | 2020-01-21 | 2020-06-12 | 广芯微电子（广州）股份有限公司 | Automatic testing method, device and system for chip |
| CN112782560A (en) * | 2020-12-31 | 2021-05-11 | 海光信息技术股份有限公司 | Chip testing method, device, storage medium and equipment |
| TWI799882B (en) * | 2021-06-02 | 2023-04-21 | 矽品精密工業股份有限公司 | Test equipment |
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Application publication date: 20190416 |