CN103440363B - Abnormal signal source tracing method in a kind of FPGA placement-and-routing post-simulation - Google Patents
Abnormal signal source tracing method in a kind of FPGA placement-and-routing post-simulation Download PDFInfo
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Abstract
The invention discloses abnormal signal source tracing method in a kind of FPGA placement-and-routing post-simulation.By carrying out lexical analysis and grammatical analysis to net meter file after placement-and-routing, draw the annexation of signal between corresponding logical device and device and store with digraph, an abnormal signal is provided by user, reverse search digraph, draw the maximal connected subgraph that can have influence on this abnormal signal value, the whole signals extracted in digraph in maximal connected subgraph respective path add simulation software and emulate, and obtain corresponding signal simulation VCD file.From the node that abnormal signal connects, according to VCD file, whether the signal judging to connect so far node is successively the source of abnormal signal, recalls, the signal finding signal without exception to originate and the source of abnormal signal from the source of any one abnormal signal.The invention enables FPGA testing authentication personnel can simplify the positioning flow of the abnormal signal of post-simulation testing authentication process, shorten signal and trace to the source the time.
Description
Technical field
The present invention relates to abnormal signal source tracing method, especially relate to abnormal signal source tracing method in a kind of FPGA placement-and-routing post-simulation.
Background technology
Along with FPGA(field programmable logic array (FPLA)) design becomes day by day complicated, and corresponding testing authentication difficulty is in rapid increasing.In placement-and-routing's post-simulation proof procedure; it is the abnormal conditions such as indefinite state or burr that checking personnel usually can run into signal value; searching and tracing to the source mainly through observing waveform and the analysis to signal value at present for abnormal signal; may be that the signal in abnormal signal source adds emulator and carries out simulation analysis repeatedly; there occurs change due to internal signal name in placement-and-routing's post-simulation and automatically generate the logical blocks such as a large amount of register, look-up table and other Sheffer stroke gates, search procedure is very loaded down with trivial details and be difficult to accurately location and produce the signal source of this abnormal signal.
Summary of the invention
The object of the present invention is to provide abnormal signal source tracing method in a kind of FPGA placement-and-routing post-simulation, by the analysis to placement-and-routing's post-simulation logic netlist, extract a small amount of signal value and emulate, and the source of energy quick position abnormal signal.
The step of the technical solution adopted in the present invention is as follows:
(1) by carrying out lexical analysis and grammatical analysis to net meter file after placement-and-routing, the input/output relation of signal between the corresponding logical device of net meter file and logical device and described signal and logical device is drawn;
(2) digraph is used to store the annexation of signal between corresponding logical device and logical device;
(3) abnormal signal is provided by user;
(4) reverse search digraph, draws the maximal connected subgraph that can have influence on abnormal signal value, and the whole signals extracting the path that in described digraph, maximal connected subgraph is corresponding add simulation software, emulate, and obtains corresponding signal simulation VCD file;
(5) from using abnormal signal as export limit node, according to VCD file, whether the signal judging to connect so far node is successively the source of abnormal signal, continue backtracking from the source of any one abnormal signal, the signal finding signal without exception to originate and the source of abnormal signal also show the path of backtracking.
Need extract during the annexation of signal between net meter file constitutive logic device and logical device after described placement-and-routing and module's logic structure in analysis chip library file.
When using the annexation of signal between digraph stored logic device and logical device by abstract for logical device be the node of digraph, use the title of logical device as node identifier, between logical device, signal abstraction is the directed edge of digraph, using signal name between logical device as directed edge identifier.
User provides emulation moment when abnormal signal need provide abnormal signal title simultaneously and occur abnormal.
Described simulation software is VCS or modelsim.
Needed to process digraph before backtracking, the ring existed is reduced to a node in digraph.
The beneficial effect that the present invention has is:
The present invention is by the analysis to placement-and-routing's post-simulation logic netlist, extract a small amount of signal value to emulate, and the source of energy quick position abnormal signal, make FPGA testing authentication personnel can simplify the positioning flow of the abnormal signal of post-simulation testing authentication process, shorten signal and trace to the source the time.
Accompanying drawing explanation
Abnormal signal source tracing method process flow diagram in Tu1Shi placement-and-routing post-simulation.
Fig. 2 analyzes net meter file process flow diagram after placement-and-routing.
Fig. 3 is signal simulation process flow diagram.
Fig. 4 is abnormal signal source, location process flow diagram.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described.
As shown in Figure 1, step of the present invention is as follows:
(1) by carrying out lexical analysis and grammatical analysis to net meter file after placement-and-routing, the input/output relation of signal between the corresponding logical device of net meter file and logical device and described signal and logical device is drawn;
(2) digraph is used to store the annexation of signal between corresponding logical device and logical device;
As shown in Figure 2, above-mentioned 2 steps are specific as follows:
1) acquisition acquisition post-simulation net meter file and corresponding library file is retrieved in the path, file place set in advance or under appointment engineering catalogue.
2) flex and bison is utilized to carry out lexical analysis and grammatical analysis to net meter file, extraction logic device name, and each port signal of logical device.
3) each port signal in corresponding net meter file, search library file module determines that this port signal is input or the output port of logical device, obtains the input/output relation of signal between logical device and logical device in net meter file.
4) annexation between logical device and input/output signal is undertaken abstract by digraph, digraph stores with orthogonal list, logical device is abstract is corresponding node, the name of logical device is used to be referred to as node identifier, signal abstraction between logical device is the directed edge of digraph, using signal name between logical device as directed edge identifier, the weights of the corresponding corresponding edge of signal value, build digraph as playing initial line from being input to export using input signal, and add corresponding start node and destination node.
(3) provide an abnormal signal by user, acquisition abnormal signal title and abnormal moment need provide an inputting interface and define input format and requirement.；
(4) signal simulation flow process, as shown in Figure 3, concrete steps are as follows:
1) be that first initial line starts reverse search digraph with abnormal signal, obtain the maximal connected subgraph that can affect this signal, extract the whole signals in maximal connected subgraph respective path in digraph.
2) the whole signals extracted in step 1) are added simulation software and start emulation, simulation software is VCS or modelsim, is VCD file by signal simulation memory dump.
(5) from using abnormal signal as export limit node, according to VCD file, whether the signal judging to connect so far node is successively the source of abnormal signal, continues backtracking, find the signal that signal without exception is originated from the source of any one abnormal signal.As shown in Figure 4, concrete steps are as follows:
1) maximal connected subgraph obtained step 1) in Fig. 3 carries out pre-service, the ring in digraph is punctured into a node.
2) from the node that abnormal signal value connects, step 2 in composition graphs 3) obtain VCD file and carry out backtracking analysis.Represent with tu the moment that abnormal signal occurs, t0 represents time zero, is defined as reset moment or fpga chip of FPGA as the case may be and powers on the moment.The process analyzed is as follows:
A) node that current abnormal signal connects is read in;
B) read in input limit, analyze VCD file;
C) judge whether tu to t0 exists abnormal signal, jump to e) if do not exist, otherwise;
D) upgrading tu is that the abnormal moment appears in input limit, upgrades current abnormal signal for input limit, jumps to a);
E) judge whether to also have other input limits, if jump to b), otherwise
F) terminating module, recording also this signal is abnormal signal source
3) judge whether in the loop abnormal signal source point, if need to continue to find the signal occurring exceptional value the earliest in ring.
(6) moment of the title in abnormal signal source and generation exception is presented in this fashion for clarity, the All Paths of process process and display is traced to the source.
Claims (6)
1. an abnormal signal source tracing method in FPGA placement-and-routing post-simulation, it is characterized in that, the step of the method is as follows:
(1) by carrying out lexical analysis and grammatical analysis to net meter file after placement-and-routing, the input/output relation of signal between the corresponding logical device of net meter file and logical device and described signal and logical device is drawn;
(2) digraph is used to store the annexation of signal between corresponding logical device and logical device;
(3) abnormal signal is provided by user;
(4) reverse search digraph, draws the maximal connected subgraph that can have influence on abnormal signal value, and the whole signals extracting the path that in described digraph, maximal connected subgraph is corresponding add simulation software, emulate, and obtains corresponding signal simulation VCD file;
(5) from using abnormal signal as export limit node, according to VCD file, whether the signal judging to connect so far node is successively the source of abnormal signal, continue backtracking from the source of any one abnormal signal, the signal finding signal without exception to originate and the source of abnormal signal also show the path of backtracking.
2. abnormal signal source tracing method in a kind of FPGA placement-and-routing according to claim 1 post-simulation, is characterized in that: need extract during signal annexation between net meter file constitutive logic device and logical device after described placement-and-routing and analysis chip library file in module's logic structure.
3. abnormal signal source tracing method in a kind of FPGA placement-and-routing according to claim 1 post-simulation, it is characterized in that: when using the annexation of signal between digraph stored logic device and logical device by abstract for the logical device node for digraph, the name of logical device is used to be referred to as node identifier, between logical device, signal abstraction is the directed edge of digraph, using signal name between logical device as directed edge identifier.
4. abnormal signal source tracing method in a kind of FPGA placement-and-routing according to claim 1 post-simulation, is characterized in that: user provides emulation moment when abnormal signal need provide abnormal signal title simultaneously and occur abnormal.
5. abnormal signal source tracing method in a kind of FPGA placement-and-routing according to claim 1 post-simulation, is characterized in that: described simulation software is VCS or modelsim.
6. abnormal signal source tracing method in a kind of FPGA placement-and-routing according to claim 1 post-simulation, is characterized in that: needed to process digraph before backtracking, the ring existed is reduced to a node in digraph.
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| CN104699571B (en) * | 2015-03-23 | 2017-11-14 | 上海交通大学 | FPGA single particle upset soft error detection method based on redundant interconnections resource |
| CN111353182B (en) * | 2020-03-11 | 2023-05-05 | 电子科技大学 | Netlist loop recognition method for FPGA chip |
| CN112131814B (en) * | 2020-09-25 | 2021-12-10 | 无锡中微亿芯有限公司 | FPGA layout legalization method utilizing regional re-layout |
| CN112232018B (en) * | 2020-12-16 | 2021-05-18 | 南京集成电路设计服务产业创新中心有限公司 | Connecting line representation method based on directed graph |
| CN112560378B (en) * | 2020-12-23 | 2023-03-24 | 苏州易行电子科技有限公司 | Be applied to automation platform of integrating complete chip development flow |
| CN114692551B (en) * | 2022-03-22 | 2024-06-07 | 中国科学院大学 | Detection method for safety key signals of Verilog design file |
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| US7882465B2 (en) * | 2006-11-21 | 2011-02-01 | International Business Machines Corporation | FPGA and method and system for configuring and debugging a FPGA |
| CN102289414A (en) * | 2010-06-17 | 2011-12-21 | 中兴通讯股份有限公司 | Memory data protection device and method |
| CN102768692A (en) * | 2011-05-06 | 2012-11-07 | 中国科学院微电子研究所 | Navigation layout wiring method applied to FPGA test |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7882465B2 (en) * | 2006-11-21 | 2011-02-01 | International Business Machines Corporation | FPGA and method and system for configuring and debugging a FPGA |
| CN102289414A (en) * | 2010-06-17 | 2011-12-21 | 中兴通讯股份有限公司 | Memory data protection device and method |
| CN102768692A (en) * | 2011-05-06 | 2012-11-07 | 中国科学院微电子研究所 | Navigation layout wiring method applied to FPGA test |
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