CN111353182B - Netlist loop recognition method for FPGA chip - Google Patents

Netlist loop recognition method for FPGA chip Download PDF

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CN111353182B
CN111353182B CN202010167733.XA CN202010167733A CN111353182B CN 111353182 B CN111353182 B CN 111353182B CN 202010167733 A CN202010167733 A CN 202010167733A CN 111353182 B CN111353182 B CN 111353182B
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CN111353182A (en
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王坚
李桓
杨鍊
陈哲
郭世泽
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University of Electronic Science and Technology of China
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Abstract

The invention discloses a netlist loop recognition method facing an FPGA chip, which comprises the following steps: s1: extracting a netlist file of the FPGA chip; s2: establishing a directed graph model; s3: performing depth-first traversal on the directed graph model by combining the stack structure, and identifying a loop of the directed graph model; s4: identifying a nested loop; s5: and extracting an aggregation loop by utilizing a step-by-step circulation aggregation strategy based on the nested loop to obtain a netlist loop identification result of the FPGA chip. The invention provides a novel FPGA chip netlist loop recognition method. The netlist loop recognition method utilizes a constructed directed graph model to recognize the directed graph model; simultaneously, a concept of nested loops is provided, and the nested loops in the netlist are identified; finally, a strategy of distributed cyclic aggregation is provided, and an aggregation loop in the directed graph model is identified. The identification method is simple to operate, and can ensure correct identification of the netlist loop.

Description

Netlist loop recognition method for FPGA chip
Technical Field
The invention belongs to the technical field of chip hardware safety, and particularly relates to a netlist loop recognition method for an FPGA chip.
Background
Currently, the semiconductor industry and various production technologies are widely developed, and chips are smaller and smaller, and functions are more and more complex. However, digital integrated circuits may encounter a wide variety of hardware attacks, both at the design stage and at the actual chip fabrication stage. A new type of hardware attack of integrated circuits, known as hardware Trojan, has become an important issue in recent years. The hardware trojan may disable or alter the functionality of the integrated circuit or leak sensitive user information. Modern FPGA automation design basic flows include synthesis, mapping, place and route, and bit stream generation, where the netlist file generated after synthesis takes on an extremely important role. In addition, the netlist file is also the main file for hardware Trojan intrusion. Thus, related research on netlist files is critical for protection of hardware security.
Chip netlist loops are a common structure in netlists and often require special handling in netlist-based research. However, because of the large number of components in the netlist, the logic relationships between the components are complex, and it is difficult for researchers to accurately identify loops in the netlist, so that subsequent netlist-based research cannot be performed normally. At present, few researches related to loop identification in FPGA netlist files exist in academia. Based on the above situation, the invention provides a netlist loop recognition method for an FPGA chip.
Disclosure of Invention
The invention aims to solve the problem of a netlist loop recognition method of an FPGA chip, and provides a netlist loop recognition method facing the FPGA chip.
The technical scheme of the invention is as follows: the netlist loop recognition method for the FPGA chip comprises the following steps of:
s1: inputting a netlist file of the FPGA chip;
s2: establishing a directed graph model of a netlist file;
s3: performing depth-first traversal on the directed graph model by combining the stack structure, and identifying a loop of the directed graph model;
s4: identifying nested loops in the loops;
s5: and extracting an aggregation loop in the loop by using a step-by-step circulation aggregation strategy to obtain a netlist loop identification result of the FPGA chip.
The beneficial effects of the invention are as follows: the invention provides a novel FPGA chip netlist loop recognition method. The netlist loop recognition method utilizes a constructed directed graph model to recognize the directed graph model; simultaneously, a concept of nested loops is provided, and the nested loops in the netlist are identified; finally, a strategy of distributed cyclic aggregation is provided, and an aggregation loop in the directed graph model is identified. The identification method has the characteristics of simple operation and easy realization, and can ensure correct identification of the netlist loop.
Further, step S2 comprises the sub-steps of:
s21: setting a register set of the netlist file as R;
s22: constructing a vertex set of a netlist file as V according to the register set;
s23: and constructing a directed edge set of the netlist file as E according to the register set to obtain a directed graph model G= (V, E), and completing the establishment of the directed graph model.
The beneficial effects of the above-mentioned further scheme are: in the invention, a directed graph is represented by g= (V, E), where G represents one graph, V is the set of vertices in graph G, and E is the set of edges in graph G, which represents a simple and easy-to-operate method.
Further, in step S22, the register set R and the vertex set V have a one-to-one relationship, denoted as R i →v i ，r i ∈R，v i E V, whose vertex set V has the following properties:
for the following
Figure BDA0002408048470000021
So that r i →v i Establishment;
for the following
Figure BDA0002408048470000022
So that r i →v i Establishment;
in step S23, the directed edge set e= = ("a")<v i ，v j >|v i ，v j The properties of e V) are:
for the following
Figure BDA0002408048470000031
v j ∈E，
Figure BDA0002408048470000036
r i E R, such that R i →v i And r j →v j Is true and r i R is j Is a pre-stage register of the (c).
The beneficial effects of the above-mentioned further scheme are: in the invention, the register set is utilized to facilitate setting a one-to-one correspondence relationship with the vertex set and the directed edge set.
Further, step S3 comprises the sub-steps of:
s31: setting a loop set of the netlist file as C, wherein the accessed vertex set is W, and the non-accessed vertex set is L;
s32: optional v i ∈V，
Figure BDA0002408048470000032
Let v=v i ；
S33: accessing a vertex sequence V in the vertex set V, pushing the vertex sequence V into the stack structure S, and adding the vertex sequence V into the accessed vertex set W;
s34: optional v k E S, record satisfies v k ∈S，v k The path of =v is ring c, where k+.i;
s35: adding ring C to loop set C;
s36: performing depth-first traversal with the vertex sequence v as a starting point based on the loop set C;
s37: taking the vertex sequence v which is not visited by the depth-first traversal as a vertex set L which is not visited;
s38: and outputting a loop set C of the directed graph model according to the accessed vertex set W, the non-accessed vertex set L and the stack structure S.
The beneficial effects of the above-mentioned further scheme are: in the invention, the loop of the directed graph model is identified based on the depth-first traversal of the directed graph model and in combination with the stack structure.
Further, in step S38, if
Figure BDA0002408048470000033
And for->
Figure BDA0002408048470000034
All have v n E, if W is met, outputting a loop C of the directed graph model, otherwise, returning to the step S32;
if it is
Figure BDA0002408048470000035
Then set v t Let v=v for stack top element of stack structure S t And v t Pulling out the stack, and returning to the step S32;
if it is
Figure BDA0002408048470000041
Then optionally v j ∈L，v＝v j Returning to step S32;
if it is
Figure BDA0002408048470000042
The vertex sequence v pops.
The beneficial effects of the above-mentioned further scheme are: in the present invention, in step S38, a loop set of the directed graph model is output using the accessed vertex set, the non-accessed vertex set, and the stack structure, and the determination method is simple.
Further, step S4 comprises the sub-steps of:
s41: set the set of nested loops to Q, set loop set c= (C) 1 ，c 2 ，…c n ) The set of flags in (1) is f= { F ij |(f 11 ，f 12 ，…，f 1n ，f 21 ，f 22 ，…f nn ) Setting the flag sequence in the flag set F as F ij Wherein i is less than or equal to n, j is less than or equal to m, and n and m are respectively the two subset sizes of the loop set C;
s42: initializing a set of flags F such that a sequence of flags F ij ＝0；
S43: optional c i ，c j E C, according to C i ∩c j The arithmetic result of (a) outputs a nested loop set Q.
The beneficial effects of the above-mentioned further scheme are: in the invention, step S4 is used for judging whether nested loops exist or not, so that the judgment of the aggregation loops is facilitated.
Further, step S43 includes the sub-steps of:
s431: optional c i ，c j E C causes
Figure BDA0002408048470000043
Let the embedded ring q ij ＝(c i ，c j )；
S432: will be nested with the collar q ij To nested loop set Q such that
Figure BDA0002408048470000044
c j E c all have a flag sequence f ij ＝1；
S433: and outputting the nested loop set according to the operation result of the nested loop set Q.
The beneficial effects of the above-mentioned further scheme are: in the present invention, step S43 outputs the nested loop according to the operation result, and the judging process is easy to operate.
Further, in step S433, if
Figure BDA0002408048470000045
Then there is no nested loop, output loop set C, end the cycle; if it is
Figure BDA0002408048470000046
Then the nested loop set Q is output and the loop is ended.
The beneficial effects of the above-mentioned further scheme are: in the invention, whether to output the nested loop is judged according to whether the nested loop set is an empty set or not.
Further, step S5 comprises the sub-steps of:
s51: inputting a nested loop set Q and a loop set C into the netlist file, and setting an aggregated loop set J;
s52: initializing a set of flags F such that a sequence of flags F ij ＝0；
S53: sequence f of the tag ij Adding a flag set F, judging whether the preliminary polymerization is finished by using the flag set F, if so, finishing the preliminary polymerization, entering a step S54, otherwise, finishing the cycle;
s54: nested loop sequence Q in optional nested loop set Q ij E Q, let j=c i ∪c j J is added to the aggregation loop set J, and the step S55 is carried out;
s55: judging whether the mark set F is empty, if so, entering a step S56, otherwise, returning to the step S54;
s56: judging whether the aggregation loop set J should be output, if so, outputting an aggregation loop, ending the cycle, otherwise, entering S57;
s57: initializing a set of flags F such that a sequence of flags F ij ＝0；
S58: sequence f of the tag ij Adding a flag set F, judging whether the polymerization is finished or not by using the flag set F, if so, entering a step S59, otherwise, finishing the cycle;
s59: optional j i ，j j ∈J，
Figure BDA0002408048470000051
Let j=c i ∪c j Adding J to the aggregation loop set J;
s510: will j i And j j Remove from aggregation loop set J, proceed to S511;
s511: and judging whether the flag set F should be emptied, if so, returning to the step S56, otherwise, returning to the step S59, and completing the aggregation loop extraction.
The beneficial effects of the above-mentioned further scheme are: in the invention, step S5 adopts a step-by-step circulation aggregation strategy to finish the judgment of the aggregation loop, thereby being beneficial to extracting the aggregation loop.
Further, in step S53, if
Figure BDA0002408048470000052
All have a tag sequence f ij After the preliminary polymerization is completed, step S54 is performed;
in step S55, if
Figure BDA0002408048470000061
All have a tag sequence f ij =1, then empty flag set F;
in step S56, if
Figure BDA0002408048470000064
j j E J makes->
Figure BDA0002408048470000062
S57 is entered, otherwise, an aggregation loop is output, and the cycle is ended; />
In step S58, if
Figure BDA0002408048470000063
All have a tag sequence f ij The preliminary polymerization is ended when=1, and the process advances to step S59.
The beneficial effects of the above-mentioned further scheme are: in the present invention, different criteria are used to determine whether the polymerization should end.
Drawings
FIG. 1 is a flow chart of a netlist loop identification method;
FIG. 2 is a flowchart of step S2;
FIG. 3 is a flowchart of step S3;
FIG. 4 is a flowchart of step S4;
fig. 5 is a flowchart of step S43;
fig. 6 is a flowchart of step S5.
Detailed Description
Embodiments of the present invention are further described below with reference to the accompanying drawings.
As shown in FIG. 1, the invention provides a netlist loop recognition method facing an FPGA chip, which comprises the following steps:
s1: inputting a netlist file of the FPGA chip;
s2: establishing a directed graph model of a netlist file;
s3: performing depth-first traversal on the directed graph model by combining the stack structure, and identifying a loop of the directed graph model;
s4: identifying nested loops in the loops;
s5: and extracting an aggregation loop in the loop by using a step-by-step circulation aggregation strategy to obtain a netlist loop identification result of the FPGA chip.
In the embodiment of the present invention, as shown in fig. 2, step S2 includes the following sub-steps:
s21: setting a register set of the netlist file as R;
s22: constructing a vertex set of a netlist file as V according to the register set;
s23: and constructing a directed edge set of the netlist file as E according to the register set to obtain a directed graph model G= (V, E), and completing the establishment of the directed graph model.
In the invention, a directed graph is represented by g= (V, E), where G represents one graph, V is the set of vertices in graph G, and E is the set of edges in graph G, which represents a simple and easy-to-operate method.
In the embodiment of the present invention, as shown in fig. 2, in step S22, the register set R and the vertex set V have a one-to-one relationship, denoted as R i →v i ，r i ∈R，v i E V, whose vertex set V has the following properties:
for the following
Figure BDA0002408048470000071
So that r i →v i Establishment;
for the following
Figure BDA0002408048470000072
So that r i →v i Establishment;
in step S23, the directed edge set e= = ("a")<v i ，v j >|v i ，v j The properties of e V) are:
for the following
Figure BDA0002408048470000073
v i ∈E，
Figure BDA0002408048470000075
r j E R, such that R i →v i And r j →v j Is true and r i R is j Is a pre-stage register of the (c).
In the invention, the register set is utilized to facilitate setting a one-to-one correspondence relationship with the vertex set and the directed edge set.
In the embodiment of the present invention, as shown in fig. 3, step S3 includes the following sub-steps:
s31: setting a loop set of the netlist file as C, wherein the accessed vertex set is W, and the non-accessed vertex set is L;
s32: optional v i ∈V，
Figure BDA0002408048470000074
Let v=v i ；
S33: accessing a vertex sequence V in the vertex set V, pushing the vertex sequence V into the stack structure S, and adding the vertex sequence V into the accessed vertex set W;
s34: optional v k E S, record satisfies v k ∈S，v k The path of =v is ring c, where k+.i;
s35: adding ring C to loop set C;
s36: performing depth-first traversal with the vertex sequence v as a starting point based on the loop set C;
s37: taking the vertex sequence v which is not visited by the depth-first traversal as a vertex set L which is not visited;
s38: and outputting a loop set C of the directed graph model according to the accessed vertex set W, the non-accessed vertex set L and the stack structure S.
In the invention, the loop of the directed graph model is identified based on the depth-first traversal of the directed graph model and in combination with the stack structure.
In the embodiment of the present invention, as shown in fig. 3, in step S38, if
Figure BDA0002408048470000081
And for->
Figure BDA0002408048470000082
All have v n E, if W is met, outputting a loop C of the directed graph model, otherwise, returning to the step S32;
if it is
Figure BDA0002408048470000083
Then set v t Let v=v for stack top element of stack structure S t And v t Pulling out the stack, and returning to the step S32;
if it is
Figure BDA0002408048470000084
Then optionally v j ∈L，v＝v j Returning to step S32;
if it is
Figure BDA0002408048470000085
The vertex sequence v pops.
In the present invention, in step S38, a loop set of the directed graph model is output using the accessed vertex set, the non-accessed vertex set, and the stack structure, and the determination method is simple.
In the embodiment of the present invention, as shown in fig. 4, step S4 includes the following sub-steps:
s41: set the set of nested loops to Q, set loop set c= (C) 1 ，c 2 ，…c n ) The set of flags in (1) is f= { F ij |(f 11 ，f 12 ，…，f 1n ，f 21 ，f 22 ，…f nn ) Setting the flag sequence in the flag set F as F ij Wherein i is less than or equal to n, j is less than or equal to m, and n and m are respectively the two subset sizes of the loop set C;
s42: initializing a set of flags F such that a sequence of flags F ij ＝0；
S43: optional c i ，c j E C, according to C i ∩c j The arithmetic result of (a) outputs a nested loop set Q.
In the invention, step S4 is used for judging whether nested loops exist or not, so that the judgment of the aggregation loops is facilitated.
The properties of the flag set F are: for the following
Figure BDA0002408048470000091
c j E C, all have f ij E F is taken as a flag bit, when F ij When=1, it indicates that c has been performed i ∩c j Calculation, when f ij When=0, it indicates that c has not been performed i ∩c j And (5) calculating.
In the embodiment of the present invention, as shown in fig. 5, step S43 includes the following sub-steps:
s431: optional c i ，c j E C causes
Figure BDA0002408048470000092
Let the embedded ring q ij ＝(c i ，c j )；
S432: will be nested with the collar q ij To nested loop set Q such that
Figure BDA0002408048470000093
c j E c all have a flag sequence f ij ＝1；
S433: and outputting the nested loop set according to the operation result of the nested loop set Q.
In the present invention, step S43 outputs the nested loop according to the operation result, and the judging process is easy to operate.
In the embodiment of the present invention, as shown in fig. 5, in step S433, if
Figure BDA0002408048470000094
Then there is no nested loop, output loop set C, end the cycle; if->
Figure BDA0002408048470000095
Then the nested loop set Q is output and the loop is ended.
In the invention, whether to output the nested loop is judged according to whether the nested loop set is an empty set or not.
In the embodiment of the present invention, as shown in fig. 6, step S5 includes the following sub-steps:
s51: inputting a nested loop set Q and a loop set C into the netlist file, and setting an aggregated loop set J;
s52: initializing a set of flags F such that a sequence of flags F ij ＝0；
S53: sequence f of the tag ij Adding a flag set F, judging whether the preliminary polymerization is finished by using the flag set F, if so, finishing the preliminary polymerization, entering a step S54, otherwise, finishing the cycle;
s54: nested loop sequence Q in optional nested loop set Q ij E Q, let j=c i ∪c j J is added to the aggregation loop set J, and the step S55 is carried out;
s55: judging whether the mark set F is empty, if so, entering a step S56, otherwise, returning to the step S54;
s56: judging whether the aggregation loop set J should be output, if so, outputting an aggregation loop, ending the cycle, otherwise, entering S57;
s57: initializing a set of flags F such that a sequence of flags F ij ＝0；
S58: sequence f of the tag ij Adding a flag set F, judging whether the polymerization is finished or not by using the flag set F, if so, entering a step S59, otherwise, finishing the cycle;
s59: optional j i ，j j ∈J，
Figure BDA0002408048470000101
Let j=c i ∪c j Adding J to the aggregation loop set J;
s510: will j i And j j Remove from aggregation loop set J, proceed to S511;
s511: and judging whether the flag set F should be emptied, if so, returning to the step S56, otherwise, returning to the step S59, and completing the aggregation loop extraction.
In the invention, step S5 adopts a step-by-step circulation aggregation strategy to finish the judgment of the aggregation loop, thereby being beneficial to extracting the aggregation loop.
In the embodiment of the present invention, as shown in fig. 6, in step S53, if
Figure BDA0002408048470000102
All have a tag sequence f ij After the preliminary polymerization is completed, step S54 is performed;
in step S55, if
Figure BDA0002408048470000103
All have a tag sequence f ij =1, then empty flag set F;
in step S56, if
Figure BDA0002408048470000104
j j E J makes->
Figure BDA0002408048470000105
S57 is entered, otherwise, an aggregation loop is output, and the cycle is ended;
in step S58, if
Figure BDA0002408048470000106
All have a tag sequence f ij The preliminary polymerization is ended when=1, and the process advances to step S59.
In the present invention, different criteria are used to determine whether the polymerization should end.
For the identification method of the present invention, the following definition is given to the related concepts:
directed graph: the present invention uses g= (V, E) to represent a directed graph, where G represents one graph, V is the set of vertices in graph G, and E is the set of edges in graph G. If from vertex v i To vertex v j The edge of the pattern is referred to as a directional edge, and the sequential couple is used<v i ，v j >Expressed by the name v i Adjacent to v j ，v j Adjacent self v i . If the edge between any two vertices in the directed graph is a directed edge, the graph is referred to as a directed graph.
And (3) a loop: let vertex sequence v= (v) 0 v 1 v 2 …v m =w), then the sequence is called a path. If the start point and the end point of a path are the same, i.e., v=w, the path is referred to as a loop and denoted as C.
Nested loops: for two loops C 1 ＝(v i1 v i2 …v in ) And C 2 ＝(v j1 v j2 …v jm ) If (if)
Figure BDA0002408048470000111
Then call C 1 And C 2 As nested loops, denoted as q= (C 1 ，C 2 )。
Aggregation loop: for nested loop q= (C 1 ，C 2 )，C 1 ＝(v i1 v i2 …v in ) And C 2 ＝(v j1 v j2 …v jm ) Note that aggregation loop j=c 1 ∪C 2 . In particular for polymerization loop J i And J j (i.noteq.j), if
Figure BDA0002408048470000112
Then j=j i ∪J j Also an aggregation loop.
The netlist file of the 8051 processor is identified by the identification method of the invention.
First, a netlist file is input, and a directed graph model g= (V, E) is created. Since there are 737 register variables in the 8051 processor and 94800 pre-stage register relationships, in the directed graph g= (V, E), v= (V) 1 ，v 2 ，…v 737 )，E＝(e 1 ，e 2 ，…e 94800 )。
Based on the directed graph G, the method adopts a depth-first traversal method, and records traversal paths by combining the characteristics of the last-in first-out of the stack structure S. The set of recording loops is set to C. For example loop c 1 ＝(v 1 ，v 2 ，v 4 ，v 5 ，v 1 ) Loop c 2 ＝(v 6 ，v 7 ，v 9 ，v 6 ) Loop c 3 ＝(v 1 ，v 2 ，v 6 ，v 10 ，v 1 ) Then c= { C 1 ，c 2 ，c 3 }. Then, the loop set C is traversed, the nested loop set Q is set, and nested loops are identified. Due to c 1 ∩c 3 ＝{v 1 ，v 2 }，c 2 ∩c 3 ＝{v 6 }. Thus, nested loop q is identified 13 ＝(c 1 ，c 3 )，q 23 ＝(c 2 ，c 3 ) Will q 13 And q 23 Adding a nested loop set Q to obtain Q= { Q 13 ＝(c 1 ，c 3 )，q 23 ＝(c 2 ，c 3 )}。
And finally, performing cyclic step-by-step aggregation operation on the nested loop set Q, and setting the aggregation loop set as J. In the preliminary aggregation, a nested loop set Q is input, so the nested loop set Q is traversed. From q 13 ＝(c 1 ，c 3 )，c 1 ∩c 3 ＝{v 1 ，v 2 }, get j 13 ＝c 1 ∪c 3 ＝(v 1 ，v 2 ，v 4 ，v 5 ，v 6 ，v 10 ). And is composed of q 23 ＝(c 2 ，c 3 )，c 2 ∩c 3 ＝{v 6 }, get j 23 ＝c 2 ∪c 3 ＝(v 1 ，v 2 ，v 6 ，v 7 ，v 9 ，v 10 ). Will j 13 And j 23 Storing the data into an aggregation loop set J to obtain J= { J 13 ，j 23 }. And entering a subsequent polymerization stage, and performing polymerization operation on the polymerization loop set J. Due to j 13 ∩j 23 ＝{v 1 ，v 2 ，v 6 ，v 10 And polymerization needs to be continued. Let j=j 13 ∪j 23 Add J to aggregate loop set J, then remove J 13 And j 23 Obtaining an aggregated loop set J= { j= (v) 1 ，v 2 ，v 4 ，v 5 ，v 6 ，v 7 ，v 9 ，v 10 ) }. The aggregation loop set J does not satisfy the condition at this time:
Figure BDA0002408048470000121
j j ∈J，
Figure BDA0002408048470000122
thus, the aggregation is stopped, the nested loop set is output, and netlist loop recognition of the 8051 processor is completed. As shown in table 1, in the loop information extracted by the 8051 processor, there are two aggregation loops in total in the last aggregation loop set J. Of all registers, 199 do not belong to any loop, 536 belong to loop 1 and 2 belong to loop 2. The identification result and the reality of the invention are adoptedThe situation is matched.
TABLE 1
Loop ID Containing the number of registers Whether or not to be the same as the actual situation
No loop 199 Is that
Ring 1 536 Is that
Ring 2 2 Is that
The working principle and the working process of the invention are as follows: the identification method of the invention firstly builds a directed graph model. The paths in the directed graph model are then traversed with depth first, identifying the directed graph loops. Then, the method proposes the concept of nested loops, and the nested loops in the netlist file are identified. Finally, the invention provides a strategy of step-by-step cyclic aggregation, and the aggregation loop in the directed graph model is identified.
The beneficial effects of the invention are as follows: the invention provides a novel FPGA chip netlist loop recognition method. The netlist loop recognition method utilizes a constructed directed graph model to recognize the directed graph model; simultaneously, a concept of nested loops is provided, and the nested loops in the netlist are identified; finally, a strategy of distributed cyclic aggregation is provided, and an aggregation loop in the directed graph model is identified. The identification method has the characteristics of simple operation and easy realization, and can ensure correct identification of the netlist loop.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.

Claims (6)

1. A netlist loop recognition method facing FPGA chips is characterized by comprising the following steps:
s1: extracting a netlist file of the FPGA chip;
s2: establishing a directed graph model of a netlist file;
s3: performing depth-first traversal on the directed graph model by combining the stack structure, and identifying a loop of the directed graph model;
s4: identifying nested loops in the loops;
said step S4 comprises the sub-steps of:
s41: set the set of nested loops to Q, set loop set c= (C) 1 ，c 2 ，…c n ) The set of flags in (1) is f= { F ij |(f 11 ，f 12 ，…，f 1n ，f 21 ，f 22 ，…f nn ) Setting the flag sequence in the flag set F as F ij Wherein i is less than or equal to n, j is less than or equal to m, and n and m are respectively the two subset sizes of the loop set C;
s42: initializing a set of flags F such that a sequence of flags F ij ＝0；
S43: optional c i ，c j E C, according to C i ∩c j Outputting a nested loop set Q by the operation result of (2);
said step S43 comprises the sub-steps of:
s431: optional c i ，c j E C causes
Figure FDA0004149518900000011
Let the embedded ring q ij ＝(c i ，c j )；
S432: will be nested with the collar q ij To nested loop set Q such that
Figure FDA0004149518900000012
c j E c all have a flag sequence f ij ＝1；
S433: outputting a nested loop set according to the operation result of the nested loop set Q;
s5: based on the nested loop, extracting an aggregation loop in the loop by utilizing a step-by-step cyclic aggregation strategy to obtain a netlist loop identification result of the FPGA chip;
said step S5 comprises the sub-steps of:
s51: inputting a nested loop set Q and a loop set C into the netlist file, and setting an aggregated loop set J;
s52: initializing a set of flags F such that a sequence of flags F ij ＝0；
S53: sequence f of the tag ij Adding a flag set F, judging whether the preliminary polymerization is finished by using the flag set F, if so, finishing the preliminary polymerization, entering a step S54, otherwise, finishing the cycle;
s54: nested loop sequence Q in optional nested loop set Q ij E Q, let j=c i ∪c j J is added to the aggregation loop set J, and the step S55 is carried out;
s55: judging whether the mark set F is empty, if so, entering a step S56, otherwise, returning to the step S54;
s56: judging whether the aggregation loop set J should be output, if so, outputting an aggregation loop, ending the cycle, otherwise, entering S57;
s57: initializing a set of flags F such that a sequence of flags F ij ＝0；
S58: sequence f of the tag ij Adding a set of tokensF, judging whether the polymerization is finished or not by using the mark set F, if so, entering a step S59, otherwise, finishing the cycle;
s59: optional j i ，j j ∈J，
Figure FDA0004149518900000021
Let j=c i ∪c j Adding J to the aggregation loop set J;
s510: will j i And j j Remove from aggregation loop set J, proceed to S511;
s511: judging whether the flag set F should be emptied, if so, returning to the step S56, otherwise, returning to the step S59, and completing the extraction of the aggregation loop;
in the step S53, if
Figure FDA0004149518900000022
All have a tag sequence f ij After the preliminary polymerization is completed, step S54 is performed;
in the step S55, if
Figure FDA0004149518900000023
All have a tag sequence f ij =1, then empty flag set F;
in the step S56, if
Figure FDA0004149518900000024
Make->
Figure FDA0004149518900000025
S57 is entered, otherwise, an aggregation loop is output, and the cycle is ended;
in the step S58, if
Figure FDA0004149518900000026
All have a tag sequence f ij The preliminary polymerization is ended when=1, and the process advances to step S59.
2. The method for identifying a netlist loop for an FPGA chip according to claim 1, wherein said step S2 comprises the sub-steps of:
s21: setting a register set of the netlist file as R;
s22: constructing a vertex set of a netlist file as V according to the register set;
s23: and constructing a directed edge set of the netlist file as E according to the register set to obtain a directed graph model G= (V, E), and completing the establishment of the directed graph model.
3. The method for identifying a netlist loop for an FPGA chip according to claim 2, wherein in the step S22, the register set R and the vertex set V have a one-to-one relationship, denoted as R i →v i ，r i ∈R，v i E V, whose vertex set V has the following properties:
for the following
Figure FDA0004149518900000031
So that r i →v i Establishment;
for the following
Figure FDA0004149518900000032
So that r i →v i Establishment;
in the step S23, the directed edge set e= = ("a")<v i ，v j >|v i ，v j The properties of e V) are:
for the following
Figure FDA0004149518900000033
So that r i →v i And r j →v j Is true and r i R is j Is a pre-stage register of the (c).
4. The method for identifying a netlist loop for an FPGA chip according to claim 1, wherein said step S3 comprises the sub-steps of:
s31: setting a loop set of the netlist file as C, wherein the accessed vertex set is W, and the non-accessed vertex set is L;
s32: optional v i ∈V，
Figure FDA0004149518900000034
Let v=v i ；
S33: accessing a vertex sequence V in the vertex set V, pushing the vertex sequence V into the stack structure S, and adding the vertex sequence V into the accessed vertex set W;
s34: optional v k E S, record satisfies v k ∈S，v k The path of =v is ring c, where k+.i;
s35: adding ring C to loop set C;
s36: performing depth-first traversal with the vertex sequence v as a starting point based on the loop set C;
s37: taking the vertex sequence v which is not visited by the depth-first traversal as a vertex set L which is not visited;
s38: and outputting a loop set C of the directed graph model according to the accessed vertex set W, the non-accessed vertex set L and the stack structure S.
5. The method for identifying a netlist loop for an FPGA chip according to claim 4, wherein in said step S38, if
Figure FDA0004149518900000041
And for->
Figure FDA0004149518900000042
All have v n E, if W is met, outputting a loop C of the directed graph model, otherwise, returning to the step S32;
if it is
Figure FDA0004149518900000043
Then set v t Let v=v for stack top element of stack structure S t And v t Pulling out the stack, and returning to the step S32;
if it is
Figure FDA0004149518900000044
Then optionally v j ∈L，v＝v j Returning to step S32;
if it is
Figure FDA0004149518900000045
The vertex sequence v pops.
6. The method for identifying a netlist loop for an FPGA chip according to claim 1, wherein in step S433, if
Figure FDA0004149518900000046
Then there is no nested loop, output loop set C, end the cycle; if->
Figure FDA0004149518900000047
Then the nested loop set Q is output and the loop is ended. />
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