CN102226991B - 铜钯合金单晶键合丝及其制造方法 - Google Patents

铜钯合金单晶键合丝及其制造方法 Download PDF

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CN102226991B
CN102226991B CN2011101560149A CN201110156014A CN102226991B CN 102226991 B CN102226991 B CN 102226991B CN 2011101560149 A CN2011101560149 A CN 2011101560149A CN 201110156014 A CN201110156014 A CN 201110156014A CN 102226991 B CN102226991 B CN 102226991B
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徐云管
彭庶瑶
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JIANGXI LAN WEI ELECTRONIC TECHNOLOGY Co Ltd
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Abstract

一种铜钯合金单晶键合丝及其制造方法,铜钯单晶键合丝的基体材料由下列重量百分比数的原料组成:钯1.35%-10.18%,Ca 0.0001—0.0003%、Re 0.0002—0.0008%、其余为铜,其制造方法包括:提取高纯铜和高纯钯、制备单晶铜钯合金棒、然后在其表面镀钯、粗精拔、热处理、表面清洗和分卷步骤。本发明摒弃了传统工艺先拉拔、后电镀工艺,先制成线径小于3mm的单晶铜钯合金丝,然后电镀钯层,最后拉拔成钯铜合金键合丝成品。本产品可以有效提升键合铜丝的抗氧化性能,使其抗氧化性与键合金丝相当;大大延长键合铜丝产品拆封后的保质期;内部加入钯、钙、稀土等元素使得合金的成品比其它方式的生产的材料的机械强度更高,有利于进一步缩小键合丝的线径,缩短焊接间距,更加适用于高密度、多引脚集成电路封装。

Description

铜钯合金单晶键合丝及其制造方法
技术领域
本发明涉及微电子后道封装工序用金属键合丝及其制造方法,尤其涉及一种铜钯合金单晶键合丝及其制造方法。
背景技术
微电子器件芯片的键合工序,是指在一定温度下采用超声加压的方法将键合丝两端分别焊接在芯片焊盘和引线框架引脚上,实现芯片内部电路与外部电路的连接。早期的键合丝多由纯金制成,但随着黄金资源的日益稀缺、价格持续攀升,微电子封装成本大幅上升,为此业内人士研发成功了以铜丝产品来替代昂贵的金丝产品。这些键合铜丝价格低廉,且在拉伸、剪切强度和延展等方面的性能优于金丝,已经成功应用于如DIP、SOP和功率器件等产品的封装生产。但是,随着微电子器件芯片行业日益、快速向小型化、多引脚高密度方向发展,对于键合铜丝的性能要求也越来越苛刻,特别是在键合工艺中,不仅要求键合铜丝具备良好的耐高温氧化、耐热稳定性和很高的机械强度,还要具有较好的接合性及焊接性且不能有拉拔断线问题;另外由于封装密度加大、打线数量增多,除了进一步缩减键合铜丝的线径外,还有必要在铜丝表面覆盖绝缘层,以减少短路现象发生。现在,行业中已经有人用电镀钯层替代电镀金层的键合铜丝制造工艺,因为钯的成本要比金便宜得多,钯在高温、高湿或硫化物含量高的空气中性能稳定,能耐酸的侵蚀;钯有良好的延展性和可塑性,但又比金硬,能承受弯曲和摩擦,可长期保持良好的外观和光泽。但由于镀钯键合铜丝一直无法解决镀钯键合铜丝的低成品率和拉拔断线问题。
发明内容
本发明的目的是提供一种铜钯合金单晶键合丝及其制造方法,它克服现有合金类键合铜丝表面易氧化、高温稳定性差和拉拔断线问题,以及镀金类键合铜丝生产成本高、电镀层硬度低不耐摩擦的缺陷和不足,向社会提供一种以以高纯铜丝为基体在内部加高纯钯、钙、稀土等元素,以镀钯层替代镀金层的低成本、高性能键合铜丝产品及其制造方法,满足微电子器件芯片向小型化、多引脚高密度方向发展的需求。
本发明的目的是这样来实现的,铜钯单晶键合丝的基体材料由下列重量百分比数的原料组成:钯1.35%-10.18%,Ca 0.0001—0.0003%、Re 0.0002—0.0008%、其余为铜,之和等于100%。然后对铜钯合金丝电镀纯钯保护层,表面镀钯层控制在2μm-7μm ; 所述镀铜钯合金单晶键合丝直径为18μm-50μm;铜的纯度大于99.9995%,钯的纯度大于99.999%、Ca 99.—99.5%、Re为混合型稀土。
铜钯合金单晶键合丝的制造方法包括以下步骤:
①提取高纯铜:以国家标准1号纯铜为原料,提取纯度大于99.9995%的高纯铜,清洗、烘干备用;
②制备单晶铜钯合金棒:将高纯铜内部加高纯钯、钙、稀土置于金属单晶连铸室,连铸得到φ3mm、纵向和横向晶粒数均为1个的高纯铜钯合金棒;内部各元素比例为钯为1.35%-10.18%,Ca0.0001—0.0003%、Re0.0002—0.0008%、其余为铜,之和等于100%。
③粗拔:将φ3mm单晶铜钯合金棒拉拔成直径小于1mm的铜钯合金丝;
④热处理:将直径小于1mm的单晶铜钯合金丝退火;
⑤表面镀钯:对铜钯合金丝电镀纯钯保护层,电镀用钯的纯度要求大于99.999%,表面镀钯层控制在2μm-7μm 的厚度,单晶铜钯合金内部钯和表层镀纯钯的重量之和占总重量的百分比控制在1.35%-10.18%;其余为铜;
⑥精拔:将前述纯钯保护层的铜钯单晶合金键合丝,精密拉拔成φ18μm-50μm的铜钯合金单晶键合丝;
⑦热处理:将铜钯合金单晶键合丝连续退火; 
⑧表面清洗:先用酸液酸洗,然后经超声波清洗,再由高纯水清洗、洪干;
⑨分卷:单卷定尺。
在所述③粗拔步骤,是将φ3mm单晶铜钯合金棒拉拔成φ0.2mm的铜钯合金丝。
在所述⑤表面镀钯步骤:对退火后的铜钯合金丝电镀纯钯保护层,表面镀钯层控制在2μm-7μm ; 单晶铜钯合金内部钯和表层镀纯钯的重量之和占总重量的百分比控制在1.35%-10.18%;
在所述⑥精拔步骤,将电镀有纯钯保护层的铜钯合金丝精密拉拔成φ23μm的键合铜钯合金丝。
本发明的优点是:摒弃了传统工艺通常采用的——先拉拔、后电镀即直接应用的落后工艺;而是先将高纯铜在内部加入钙、稀土等元素置于金属单晶连铸机制成高纯铜钯合金棒,然后电镀一定厚度的纯钯保护层,镀钯层厚度主要根据铜钯合金单晶键合丝成品线径确定,成品线径越小,拉拔率越大,则所需镀层越厚;反之所需镀层越薄;一般情况下,镀层厚度控制在2μm-7μm,单晶铜钯合金内部钯和表层镀纯钯的重量之和占总重量的百分比控制在1.35%-10.18%;其余为铜;电镀后的半成品再经多道次工序精密拉拔成φ18μm-50μm等不同规格的铜钯合金及镀钯单晶键合丝成品。在将电镀有纯钯保护层的φ0.2mm铜钯合金丝精密拉拔成铜钯合金及镀钯单晶键合丝成品过程中,镀钯保护层的材质更加致密、均匀,表面光滑、线型一致,基体表面镀钯层和内部钯、钙、稀土等元素和铜分子互相交融、渗透,镀钯层结合强度大幅提高,确保成品外观保持银白色金属光泽,大大延长键合铜丝产品拆封后的保持期;内部加入钯、钙、稀土等元素使得合金的成品比其它方式的生产的材料的机械强度更高、抗氧化性能更好,有利于进一步缩小键合丝的线径,缩短焊接间距,更加适用于高密度、多引脚集成电路封装。消除了30度以下拉拔断线问题。有利于进一步缩小键合铜钯合金丝的线径,缩短焊接间距,更加适用于高密度、多引脚集成电路封装。本发明专利制造方法具有构思新颖、工序简单、受益显著的优点,可以广泛用于各类复合型结构的金属键合丝产品制造领域。
具体实施方式
实施例一
①提取高纯铜:将硝酸铜溶液按1:4比例加高纯水进行稀释,配制成电解液;以国家标准1号纯铜作为阳极浸入电解液,并确保有95%体积比的纯铜浸入电解液中;以高纯铜箔作为阴极浸入电解液中,同样确保有955体积比的高纯铜箔浸入电解液中;在阳极、阴极之间输入7-9V、2.5-3.5A的直流电,以补充新鲜电解液方式维持电解液温度不超过60℃;待阴极积聚纯度大于99.9995%的高纯铜,及时更换高纯铜箔,再以清洗、烘干备用。
②铜钯合金棒:在一个有氮气保护的水平连铸金属单晶的连铸室,加入提纯所得的纯度大于99.9995%的高纯铜,同时加入0.03-0.08%纯度大于99.999%的钯和纯度大于99.5%的Ca 0.0001—0.0003%和混合型稀土Re 0.0002—0.0008%;应用中频感应加热至1150-1220℃,待完全熔化、精炼和除气后,将熔液注入连铸室中间的储液池保温,在维持2-5L/min净化氮气流量的连铸室中,完成对铜钯合金熔液的水平单晶连铸,得到φ3mm、纵向和横向晶粒数均为1个的高纯铜钯合金棒;单晶铜钯合金棒可有效降低铜丝的电阻率、提高导电率,增强其搞氧化性能和机械强度。本工序更为详细的方法及其所应用设备,可参阅国家知识产权局于2008年4月30日授权公告的ZL200510023514.X名称为“金属单晶连铸工艺的控制方法及装备”发明专利技术,应属于公知技术范畴。
③粗拔:应用常规拉拔设备和工艺,将φ3mm单晶铜钯合金棒经多道次工序,拉拔成φ0.2mm的铜钯合金丝。
④热处理:将φ0.2mm的铜钯合金丝置于退火炉中,在420-460℃温度下保温25min,保温期间通以氮气保护,然后随炉冷却。
⑤表面镀钯:应用常规电镀设备和工艺,对退火后的φ0.2mm铜钯合金丝电镀纯钯防氧化保护层,电镀用钯的纯度要求大于99.999%;电流密度1-1.2A/dm2,,铜丝速度为4-5m/min,镀层厚度控制在2μm-7μm;镀钯后的铜钯合金丝产品,单晶铜钯合金内部钯和表层镀纯钯的重量之和占总重量的百分比控制在1.35%-10.18%;其余为铜。
[0028]⑥精拔:应用常规精密拉拔设备和工艺,将前述电镀有纯钯防氧化保护层的φ0.2mm铜钯合金丝经多道次工序,精密拉拔成φ23μm,引厚度镀钯层可以有效隔离铜丝表面与空气的接触,大大增强成品抗氧化性能,确保外观保持银白色金属光泽,有效延长键合铜钯合金丝产品拆封后的保持期。
⑦热处理“将φ23μm镀钯键合铜钯合金丝由退火炉在350℃温度下连续退火,键合铜钯合金丝线速度为65m/min。
⑧表面清洗:先用浓度为1-2%的酸液进行酸洗,然后经超声波清洗,再由高纯水清洗两次后烘干。
⑨分卷:以500m为单卷定尺,控制绕丝张力为8g,绕丝速度为60-65m/min,线间距4mm.
实施例二
步骤①至步骤④同实施例一。
⑤表面镀钯:应用常规电镀设备和工艺,对退火后的φ0.2mm铜钯合金丝电镀纯钯防氧化保护层,电镀用钯的纯度要求大于99.999%;电流密度4-4.5A/dm2,铜丝速度为4-5m/min,镀层厚度控制在2μm-7μm;镀钯后的铜钯合金丝产品,单晶铜钯合金内部钯和表层镀纯钯的重量之和占总重量的百分比控制在1.35%-10.18%;其余为铜,其余为铜。
⑥精拔:应用常规拉拔设备和工艺,将前述电镀有纯钯防氧化保护层的φ0.2mm铜钯合金丝经多道次工序,精密拉拔成φ23μm的镀钯键合铜钯合金丝;对于此φ23μm的镀钯键合铜钯合金丝,按照金属压延加工中体积不变定律,即在任一截面上,钯面积与铜钯合金面积之比始终是相同的,所以纯钯防氧化保护层的厚度为0.23-0.805μm,此厚度镀钯层完全足以有效隔离铜丝表面与空气的接触,大大增强成品抗氧化性能,确保外观保持银白色金属光泽,有效延长键合铜钯合金丝产品招拆封后保持期。
其余步骤⑦至步骤⑨同实施例一。
本发明一种新型铜钯单晶材料加工键合丝及其制造方法,如实施例一和实施例二所述,摒弃了传统工艺采用的—先拉拔、后电镀即直接应用的落后工艺;而是先制成φ0.2mm的铜钯合金丝后,电镀一定厚度的纯钯保护层,镀钯层的厚度主要根据键合铜钯合金丝成品线径确定,即成品线径越小,拉拔率越大,则所需镀层越厚;反之成品线径越大,拉拔率越小,所需镀层越薄;一般情况下镀层厚度控制在2μm-7μm,单晶铜钯合金内部钯和表层镀纯钯的重量之和占总重量的百分比控制在1.35%-10.18%;其余为铜;电镀后的半成品再精密拉拔成φ18μm-50μm等不同规格的铜钯合金及镀钯单晶键合丝成品。在精密拉拔过程中,镀钯层材质更加致密、均匀,表面光滑、线型一致,基体表面镀钯层和内部钯、钙、稀土等元素和铜分子互相交融、渗透,镀钯层结合强度大幅提高,确保外观保持良好的金属光泽,大大延长键合铜丝产品拆封后的保持期。内部加入钯、钙、稀土等元素使得合金的成品比其它方式的生产的材料的机械强度更高、抗氧化性能更好,有利于进一步缩小键合丝的线径,缩短焊接间距,更加适用于高密度、多引脚集成电路封装。
将按照实施例一和实施例二方法制造的两种φ23μm镀钯键合铜钯合金丝成品应用于封装工序时,其测试结果与纯铜键合丝的对比结果如下:
从上述对比结果表格可以得知,本发明专利方法制造的铜钯合金及镀钯单晶键合丝产品,其封装后的拉断力和推球剪切力(铲除焊点力)均明显高于相同规格的镀钯键合铜丝产品,与芯片焊盘、引线框架引脚的焊接牢固度更高,具备更加稳定的剪切断裂载荷。
将按照实施例一和实施例二方法制造的两种φ23μm镀钯键合铜钯合金丝成品理化指标与等径的镀钯键合铜丝对比结果如下表:
从上述结比结果表格可以得知,本发明专利方法制造的新型铜钯单晶材料加工键合丝产品,其机械强度要高于只表面镀钯键合铜丝产品;成品键合丝硬度适中、焊接成球性好;又由于内部加入钯、钙、稀土等元素使得合金的成品比其它方式的生产的材料的机械强度更高、抗氧化性能更好,缩短焊接间距,更加适用于高密度、多引脚集成电路封装。本产品可以有效提成键合铜丝的抗氧化性能,确保外观保持良好的金属光泽,大大延长键合铜钯合金丝产品拆封后的保质期。

Claims (2)

1.一种铜钯合金单晶键合丝的制造方法,其特征是方法步骤如下:
①提取高纯铜:以国家标准1号纯铜为原料,提取纯度大于99.9995%的高纯铜,清洗、烘干备用;
②制备单晶铜钯合金棒:将高纯铜内部加高纯钯、钙、混合型稀土Re置于金属单晶连铸室,其中,钯的纯度大于99.999%、Ca 的纯度大于99.5%,连铸得到φ3mm、纵向和横向晶粒数均为1个的高纯铜钯合金棒;内部各元素比例为钯为0.03%-0.08%、Ca0.0001—0.0003%、Re0.0002—0.0008%、其余为铜,之和等于100%;
③粗拔:将φ3mm单晶铜钯合金棒拉拔成直径小于1mm的单晶铜钯合金丝;
④热处理:将直径小于1mm的单晶铜钯合金丝退火;
⑤表面镀钯:对单晶铜钯合金丝电镀纯钯保护层,电镀用钯的纯度要求大于99.999%,表面镀钯层控制在2μm-7μm 的厚度,单晶铜钯合金丝内部钯和表层镀纯钯的重量之和占总重量的百分比控制在1.35%-10.18%;
⑥精拔:将具有前述纯钯保护层的单晶铜钯合金丝,精密拉拔成φ18μm-50μm的铜钯合金单晶键合丝;
⑦热处理:将铜钯合金单晶键合丝连续退火; 
⑧表面清洗:先用酸液酸洗,然后经超声波清洗,再由高纯水清洗、烘干;
⑨分卷:单卷定尺。
2.一种采用权利要求1所述的制造方法制备的铜钯合金单晶键合丝。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI512121B (zh) * 2013-05-03 2015-12-11 Heraeus Materials Singapore Pte Ltd 用於接合應用之銅線

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG190479A1 (en) * 2011-12-01 2013-06-28 Heraeus Materials Tech Gmbh Secondary alloyed 1n copper wire for bonding in microelectronics device
CN102517528B (zh) * 2011-12-09 2013-06-05 徐云管 一种单晶铜合金材料制造超高张力线的方法
CN103824833A (zh) * 2012-11-16 2014-05-28 吕传盛 半导体封装用的铜合金线
CN103219245B (zh) * 2013-03-01 2015-11-25 溧阳市虹翔机械制造有限公司 一种镀钯键合铜丝的制造方法
CN103199072A (zh) * 2013-03-14 2013-07-10 江西蓝微电子科技有限公司 镀金铜钯合金单晶键合丝及其制造方法
CN104353669B (zh) * 2014-09-12 2016-08-17 北京科技大学 一种高性能金包铜键合微丝的制备方法
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CN105177345A (zh) * 2015-08-22 2015-12-23 汕头市骏码凯撒有限公司 一种微电子封装用高可靠性铜合金键合丝及其制备方法
CN106086962A (zh) * 2016-06-06 2016-11-09 上海铭沣半导体科技有限公司 一种封装用镀金钯键合铜线的生产工艺
CN108598058B (zh) * 2017-12-21 2020-05-19 汕头市骏码凯撒有限公司 一种铜合金键合丝及其制造方法
CN109811183A (zh) * 2019-03-27 2019-05-28 广东迪奥应用材料科技有限公司 一种用于制备高导电率薄膜的铜基合金及溅射靶材

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1318011A (zh) * 1998-09-16 2001-10-17 库利克及索发投资有限公司 包覆有贵金属的复合金属线
CN1949492A (zh) * 2006-11-03 2007-04-18 宁波康强电子股份有限公司 一种键合铜丝及其制备方法
CN101607360A (zh) * 2008-06-17 2009-12-23 北京达博有色金属焊料有限责任公司 超微细键合金丝规模化生产方法
CN101800205A (zh) * 2009-02-09 2010-08-11 日月光半导体制造股份有限公司 半导体封装构造及其封装方法
CN101802994A (zh) * 2008-01-25 2010-08-11 新日铁高新材料株式会社 半导体装置用接合线

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1318011A (zh) * 1998-09-16 2001-10-17 库利克及索发投资有限公司 包覆有贵金属的复合金属线
CN1949492A (zh) * 2006-11-03 2007-04-18 宁波康强电子股份有限公司 一种键合铜丝及其制备方法
CN101802994A (zh) * 2008-01-25 2010-08-11 新日铁高新材料株式会社 半导体装置用接合线
CN101607360A (zh) * 2008-06-17 2009-12-23 北京达博有色金属焊料有限责任公司 超微细键合金丝规模化生产方法
CN101800205A (zh) * 2009-02-09 2010-08-11 日月光半导体制造股份有限公司 半导体封装构造及其封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI512121B (zh) * 2013-05-03 2015-12-11 Heraeus Materials Singapore Pte Ltd 用於接合應用之銅線

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