CN102222614B - The formation method of power metal-oxide field effect transistor - Google Patents
The formation method of power metal-oxide field effect transistor Download PDFInfo
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- CN102222614B CN102222614B CN201110172460.9A CN201110172460A CN102222614B CN 102222614 B CN102222614 B CN 102222614B CN 201110172460 A CN201110172460 A CN 201110172460A CN 102222614 B CN102222614 B CN 102222614B
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Abstract
The embodiment provides a kind of formation method of power metal-oxide field effect transistor, comprise: substrate is provided, described substrate comprises first area and the second area discrete with described first area, the live width of described first area is greater than the live width of second area, the substrate surface of described first area is formed with the first insulating barrier, the substrate surface of described second area is formed with the second insulating barrier, and described first insulating barrier and the second surface of insulating layer are formed with electrode layer, described electrode layer surface is formed with grinding barrier layer; Perform the first grinding, remove the grinding barrier layer of the described first area of part and expose the electrode layer of described second area; After described first grinding, perform the second grinding, expose the grinding barrier layer of described first area and the second insulating barrier of described second area.The formation method of the embodiment of the present invention effectively improves the stability of power metal-oxide field effect transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of formation method of power metal-oxide field effect transistor.
Background technology
Power metal-oxide field effect transistor has the features such as power is low, switching speed is fast, is widely used in the switching device of power supply.
The formation method of the power metal-oxide field effect transistor of prior art is as follows:
Please refer to Fig. 1, substrate 100 is provided, described substrate 100 comprises first area I and the discrete second area II in described first area and between first area I and second area II and the three region III adjacent with second area II with described first area I, the ratio of the live width of described first area I and the live width of second area II is 10: 1, and described live width is the illustrated width being parallel to substrate 100 surface; Substrate 100 surface of described first area I is formed with the first insulating barrier 101, and substrate 100 surface of described second area II is formed with the second insulating barrier 103, and substrate 100 surface of described 3rd region III is formed with gate insulation layer 104; The electrode layer 105 that described first insulating barrier 101, second insulating barrier 103, gate insulation layer 104 surface are formed; Described electrode layer 105 surface is formed with grinding barrier layer 107; Be formed with opening 111 in the electrode layer 105 of described 3rd region III and grinding barrier layer 107, described opening 111 exposes gate insulation layer 104 surface; Surface, described grinding barrier layer 107 is formed with separator 109, and described separator 109 fills full described opening 111.
Be not destroyed for making the electrode layer 105 on the first insulating barrier 101 surface, and expose the second insulating barrier 103, need to grind the separator 109 shown in Fig. 1, grinding barrier layer 107, electrode layer 105, the method that in prior art, usual employing is once ground, after grinding terminates, as shown in Figure 2, described first area I exposes grinding barrier layer 107, described second insulating barrier 103 surface also remains electrode layer 105, causes the unstable properties of the power metal-oxide field effect transistor of follow-up formation; Or as shown in Figure 3, expose second insulating barrier 103 of described second area II, the segment electrode layer 105 of described first area I is destroyed, the described electrode layer 105 destroyed may come off and affect subsequent process steps in subsequent process, thus causes the unstable properties of power metal-oxide field effect transistor.
The formation method of more MOS field effect tubes please refer to the application documents that publication number is " CN101777497A ".
Summary of the invention
The problem that embodiments of the invention solve is to provide a kind of formation method improving the stability of power metal-oxide field effect transistor.
For solving the problem, The embodiment provides a kind of formation method of power metal-oxide field effect transistor, comprising:
Substrate is provided, described substrate comprises first area and the second area discrete with described first area, the live width of described first area is greater than the live width of second area, the substrate surface of described first area is formed with the first insulating barrier, the substrate surface of described second area is formed with the second insulating barrier, covers the electrode layer of described first insulating barrier and the second insulating barrier, covers the grinding barrier layer of described electrode layer;
Perform the first grinding, remove the grinding barrier layer of the described first area of part and expose the electrode layer of described second area;
After described first grinding, perform the second grinding, remove the grinding barrier layer of the described first area of part and expose the second insulating barrier of described second area.
Alternatively, the ratio of the live width of described first area and the live width of second area is 5: 1 ~ 20: 1.
Alternatively, described first grinding employing first ground slurry, described first ground slurry to the grinding rate of separator is
to the grinding rate on grinding barrier layer be
described second grinding employing second ground slurry, the grinding selectivity ratio of described second ground slurry between electrode layer and grinding barrier layer is greater than 30: 1.
Alternatively, the thickness on described grinding barrier layer is
Alternatively, after described first grinding, the thickness on described grinding barrier layer is for being greater than
Alternatively, after described second grinding, the thickness on described grinding barrier layer is for being greater than
Alternatively, after described second grinding, the thickness of described second insulating barrier is for being greater than
Alternatively, described substrate also comprises the 3rd region, and described 3rd region is between described first area and second area, and adjacent with second area with described first area; The substrate surface in described 3rd region is higher than the substrate surface of described first area and second area, and the substrate surface in described 3rd region is formed with gate insulation layer, and described gate electrode insulation surface is lower than the first insulating barrier and the second surface of insulating layer; Described electrode layer is also positioned at the described gate electrode insulation surface in the 3rd region; Described grinding barrier layer is also positioned at the described electrode layer surface in the 3rd region; Opening is formed in the grinding barrier layer in described 3rd region and electrode layer; Described grinding barrier layer surface is also formed with separator, and described separator fills full described opening; Perform after the first grinding and second grinds, the insulation surface in described 3rd region is lower than the grinding barrier layer surface of first area.
Compared with prior art, embodiments of the invention have the following advantages:
Embodiments of the invention, after grinding exposes the grinding barrier layer of described first area and the electrode layer of described second area for the first time, carry out second time grinding, and the grinding selectivity ratio of described second ground slurry between electrode layer and grinding barrier layer is greater than 30: 1.Therefore the speed etching the grinding barrier layer of described first area is comparatively slow, until expose the second insulating barrier of described second area, described first area also exists grinding barrier layer.The electrode layer of the first surface of insulating layer of the power metal-oxide field effect transistor adopting the method for embodiments of the invention to be formed is not destroyed, and the second surface of insulating layer does not have electrode layer to remain yet, the stable performance of power metal-oxide field effect transistor.
Also there is the 3rd region between described first area and second area and adjacent with second area with described first area in embodiments of the invention, opening is formed in the electrode layer in described 3rd region and grinding barrier layer, full isolated material is filled, for follow-up formation electric capacity in described opening.In an embodiment of the present invention, the isolated material surfacing in the described opening of follow-up formation, the good stability of the electric capacity of formation, the stable performance of power metal-oxide field effect transistor.
Accompanying drawing explanation
Fig. 1 ~ Fig. 3 is the cross-sectional view of the formation method of the power metal-oxide field effect transistor of prior art;
Fig. 4 is the schematic flow sheet of the formation method of the power metal-oxide field effect transistor of embodiments of the invention;
Fig. 5 ~ Fig. 7 is the cross-sectional view of the formation method of the power metal-oxide field effect transistor of embodiments of the invention.
Embodiment
From background technology, in the formation method of power metal-oxide field effect transistor of the prior art, usual employing is once ground, and after grinding terminates or the second surface of insulating layer also remains electrode layer, is unfavorable for subsequent process steps; Or the segment electrode layer of first area suffers the stability of destroying infection power metal-oxide field effect transistor.
The inventor of the embodiment of the present invention studies for the problems referred to above, due to the structure of whole substrate surface inevitably can be ground in process of lapping, the inventor of the embodiment of the present invention finds employing twice grinding, in the first grinding, after removing the grinding barrier layer of part first area and the electrode layer of second area, in order to not destroy the electrode layer of first area, and expose the second insulating barrier, the large ground slurry of the grinding selectivity ratio between described electrode layer and described grinding barrier layer can be adopted to carry out the second grinding, in the second process of lapping, only remove the grinding barrier layer of sub-fraction first area, the electrode layer of first area is preserved complete, and the second insulating barrier can be exposed, avoid electrode layer to be destroyed, and the problem of the poor stability of the power metal-oxide field effect transistor caused.
Further, the inventor of the embodiment of the present invention, after research, provides a kind of formation method of power metal-oxide field effect transistor.
For enabling above-mentioned purpose, the feature and advantage of the embodiment of the present invention more become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, embodiments of the invention utilize schematic diagram to be described in detail, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 4 shows the schematic flow sheet of the formation method of the power metal-oxide field effect transistor of the specific embodiment of the invention, comprising:
Step S201, substrate is provided, described substrate comprises the discrete second area in first area and described first area and between first area and second area and three region adjacent with second area with described first area, the live width of described first area is greater than the live width of second area, and the substrate surface in described 3rd region is higher than the substrate surface of described first area and second area; The substrate surface of described first area is formed with the first insulating barrier, the substrate surface of described second area is formed with the second insulating barrier, the substrate surface in described 3rd region is formed with gate insulation layer, and described gate electrode insulation surface is lower than described first insulating barrier and the second surface of insulating layer; The surface of described first insulating barrier, the second insulating barrier and gate insulation layer is formed with electrode layer; The surface of described electrode layer is formed with grinding barrier layer; Be formed with opening in the electrode layer in described 3rd region and grinding barrier layer, described opening exposes gate electrode insulation surface; Described grinding barrier layer surface is formed with separator, and described separator fills full described opening.
Step S203, perform the first grinding, removal unit divides the grinding barrier layer of the described first area of separator, part and the grinding barrier layer of second area, exposes the electrode layer of described second area;
Step S205, after executing described first grinding, performs the second grinding, removes the separator in the grinding barrier layer of part first area, the electrode layer of second area and part the 3rd region, expose the second insulating barrier of described second area.
Specifically please refer to Fig. 5 ~ Fig. 7, Fig. 5 ~ Fig. 7 shows the cross-sectional view of the formation method of the power metal-oxide field effect transistor of the embodiment of the present invention.
Perform step S201, please refer to Fig. 5, substrate 300 is provided, described substrate comprises the discrete second area II of first area I and described first area I and between first area I and second area II and the three region III adjacent with second area II with described first area I, the live width of described first area I is greater than the live width of second area II, and substrate 300 surface of described 3rd region III is surperficial higher than the substrate 300 of described first area I and second area II; Substrate 300 surface of described first area I is formed with the first insulating barrier 301, the second insulating barrier 303 is formed on substrate 300 surface of described second area II, substrate 300 surface of described 3rd region III is formed with gate insulation layer 305, and described gate insulation layer 305 surface is lower than described first insulating barrier 301 and the second insulating barrier 302 surface; The surface of described first insulating barrier 301, second insulating barrier 303 and gate insulation layer 304 is formed with electrode layer 305; The surface of described electrode layer 305 is formed with grinding barrier layer 307; Be formed with opening 311 in the electrode layer 305 of described 3rd region III and grinding barrier layer 307, described opening 311 exposes gate insulation layer 305 surface; Surface, described grinding barrier layer 307 is formed with separator 309, and described separator 309 fills full described opening 311.
Described substrate 300 is silicon base.Described substrate 300 comprises the discrete second area II of first area I and described first area I and between first area I and second area II and the three region III adjacent with second area II with described first area I, the live width of described first area I is greater than the live width of second area II, and substrate 300 surface of described 3rd region III is surperficial higher than the substrate 300 of described first area I and second area II.Usually, when forming power metal-oxide field effect transistor, the ratio of the live width of described first area I and the live width of described second area II is 5: 1 ~ 20: 1.In an embodiment of the present invention, the live width of described first area is 300 μm, and the live width of described second area is 30 μm, and the ratio of live width is 10: 1.
It should be noted that, in an embodiment of the present invention, described live width refers to and the illustrated direction width parallel with substrate surface.
Described first insulating barrier 301 is positioned at substrate 300 surface of first area I.The material of described first insulating barrier 301 is oxide, such as silicon dioxide etc.The formation method of described first insulating barrier 301 is depositing operation, such as physics or chemical deposition, or thermal oxide growth technique.In an embodiment of the present invention, the method for described first insulating barrier is thermal oxide growth technique.
Described second insulating barrier 303 is positioned at substrate 300 surface of second area II.The material of described second insulating barrier 303 is oxide, such as silicon dioxide etc.The formation method of described second insulating barrier 303 is depositing operation, such as physics or chemical deposition, or thermal oxide growth technique.In an embodiment of the present invention, the method for described first insulating barrier is thermal oxide growth technique.
In an embodiment of the present invention, described first insulating barrier 301 is identical with the thickness of the second insulating barrier 303, for
first insulating barrier live width 301 is identical with the live width ratio of second area II with first area I with the ratio of the live width of the second insulating barrier 303, is 10: 1.
Described gate insulation layer 304 is formed in substrate 300 surface of described 3rd region III, for isolated electrode layer 305 and substrate 300.Described gate insulation layer 304 surface is lower than described first insulating barrier 301 and the second insulating barrier 303 surface.In an embodiment of the present invention, the formation method of described gate insulation layer 304 is depositing operation, and the material of described gate insulation layer 304 is identical with the material of described first insulating barrier 301, second insulating barrier 303, and be silicon dioxide, the thickness of described gate insulation layer 304 is
Described electrode layer 305 is formed in the surface of described first insulating barrier 301, second insulating barrier 303 and gate insulation layer 304.The material of described electrode layer 305 is polysilicon.
Described grinding barrier layer 307 is formed in described electrode layer 305 surface, and the electrode layer 305 for the protection of first area I is not damaged by the first grinding and the second grinding in subsequent process; The material on described grinding barrier layer 307 is silicon nitride, and the formation process on described grinding barrier layer 307 is depositing operation, such as physics or chemical deposition; Because described gate insulation layer 304 surface is lower than described first insulating barrier 301 and the second insulating barrier 303 surface, the surface, grinding barrier layer 307 being positioned at the 3rd region III therefore adopting depositing operation to be formed is lower than the surface, grinding barrier layer 307 of described first area I and second area II; Consider that described grinding barrier layer 307 for grinding as first and the second stop-layer ground in subsequent process, described grinding barrier layer 307 is too thin, is not enough to the stop-layer that grinds as follow-up first time or is not enough to the stop-layer that grinds as follow-up second time; Described grinding barrier layer 307 is too thick, is unfavorable for saving the process time.Therefore, in an embodiment of the present invention, the thickness on described grinding barrier layer 307 is
Described opening 311 is formed at the electrode layer 305 of described 3rd region III and grinds in barrier layer 307, and described opening 311 exposes described gate insulation layer 304 surface, and described opening 311 is for follow-up filling isolated material.
Described separator 309 is formed in surface, described grinding barrier layer 307.In an embodiment of the present invention, described separator 309 also for filling completely described opening 311, for forming electric capacity in subsequent process.The forming step of described separator 309 is: adopt tetraethoxysilane (TEOS) to be formed on surface, described grinding barrier layer 307 as raw material, the material of described separator 309 is silica.
It should be noted that, for forming electric capacity in subsequent process, needing the separator 309 removing part the 3rd region III.The inventor of the embodiment of the present invention finds after deliberation, if directly adopt etching method to remove the separator 309 of the described 3rd region III of part, can pit be there is in the isolated material surface in described opening 311, affect the stability of power metal-oxide field effect transistor, adopt the method for grinding to form electric capacity and then can not there are the problems referred to above.Therefore, in an embodiment of the present invention, electric capacity can also be formed by the follow-up first grinding, the second grinding.
Perform step S203, please refer to Fig. 6, perform the first grinding, removal unit divides the grinding barrier layer 307 of the described first area I of separator 309, part and the grinding barrier layer 307 of second area II, exposes the electrode layer 305 of described second area II.
Because first insulating barrier 301 of first area I and second insulating barrier 303 of second area II have different live widths, cover the electrode layer 305 of the first insulating barrier 301, the live width on grinding barrier layer 307 is also different from the electrode layer 305 of covering second insulating barrier 303, the live width on grinding barrier layer 307, and the surface on the grinding barrier layer 307 of described 3rd region III is lower than the surface on the grinding barrier layer 307 of described first area I and second area II, therefore when execution first is ground, the grinding rate on the grinding barrier layer 307 of first area I is different from the grinding rate on the grinding barrier layer 307 of second area II.
When considering that follow-up execution second is ground, for exposing the second insulating barrier, the grinding barrier layer 307 of part first area I inevitably also can be removed.Therefore, after executing the first grinding, the thickness on the grinding barrier layer 307 of described first area I can not be too little.The thickness on the grinding barrier layer 307 of described first area I is too little, so when follow-up execution second is ground, the grinding barrier layer 307 of described first area I is completely removed, the electrode layer 305 of described first area I will be destroyed, thus affects the stability of power metal-oxide field effect transistor.Therefore, the inventor of the embodiment of the present invention finds after a large amount of experimental studies, and after executing described first grinding, the thickness on the grinding barrier layer 307 of described first area I is for being greater than
time, the electrode layer 305 not destroying first area I during the second grinding can be avoided.
In the present embodiment, the concrete steps of the first grinding are: adopt the first ground slurry to grind described separator 309 and grinding barrier layer 307, described first ground slurry to the grinding rate of separator 309 is
to the grinding rate on grinding barrier layer 307 be
when exposing the electrode layer 305 of second area II, described first grinding terminates, and now the grinding barrier layer 307 of described first area I also has remaining, and thickness is greater than
Perform step S205, please refer to Fig. 7, after executing described first grinding, perform the second grinding, remove the separator 309 of the grinding barrier layer 307 of part first area I, the electrode layer 305 of second area II and part the 3rd region III, expose second insulating barrier 303 of described second area II.
After executing described first grinding, perform the second grinding.The second ground slurry is adopted when described second grinding.
Consider that the electrode layer 305 removing second area II is ground in execution second; when exposing the second insulating barrier 303; inevitably remove the grinding barrier layer 307 of part first area I, and the grinding barrier layer 307 of described first area I is not destroyed for the protection of the electrode layer 305 of first area I.Therefore, in an embodiment of the present invention, need to select the large ground slurry of grinding selectivity ratio between electrode layer 305 and grinding barrier layer 307 as the second ground slurry, namely described second ground slurry is when grinding electrode layer 305 of the same area and grinding barrier layer 307, and the thickness grinding the electrode layer 305 of removal in same time is greater than the thickness on the grinding barrier layer 307 of removal; And the live width considering first area I is greater than the live width of second area II, also can have a certain impact to the grinding rate that the grinding barrier layer 307 of described first area I and the electrode layer 305 of described second area II are carried out when second time is ground, after terminating for making second time grinding, the electrode layer 305 of described first area I does not wreck, and expose the second insulating barrier 303, the grinding selectivity ratio of the second ground slurry usually chosen between electrode layer 305 and grinding barrier layer 307 is greater than 30: 1.
The concrete steps of described second grinding are: grind the grinding barrier layer 307 of described first area I, the electrode layer 305 of described second area II and the separator 309 of the 3rd region III, until expose second insulating barrier 303 of described second area II.
After executing described second grinding, expose described second insulating barrier 303, described first area I also remains part grinding barrier layer 307.The inventor of the embodiment of the present invention finds after experimental study repeatedly, and the thickness when described part grinding barrier layer is greater than
time, can effectively protect the electrode layer 305 of described first area I not to be destroyed, and when the thickness of described second insulating barrier 303 is greater than
time, the good stability of power metal-oxide field effect transistor.
It should be noted that, after the second grinding, also there is the separator 309 of skim in the surface of described 3rd region III.For forming electric capacity in described opening 311, in subsequent technique, the separator 309 of described skim can be removed by the method for wet etching.In an embodiment of the present invention, the forming step of described electric capacity is: adopt hydrofluoric acid to remove the separator 309 of described skim; Then hot phosphoric acid is adopted to remove grinding barrier layer 307.Isolated material surfacing in described opening 311, the good stability of the described electric capacity of formation, can not have influence on the yield of power metal-oxide field effect transistor.
After above-mentioned steps completes, completing of embodiments of the invention power metal-oxide field effect transistor.
To sum up, embodiments of the invention have the following advantages:
Embodiments of the invention, after the first grinding exposes the grinding barrier layer of described first area and the electrode layer of described second area, carry out the second grinding, and the grinding selectivity ratio of described second ground slurry between electrode layer and grinding barrier layer is greater than 30: 1.Therefore the speed etching the grinding barrier layer of described first area is comparatively slow, until expose the second insulating barrier of described second area, described first area also exists grinding barrier layer.The electrode layer of the first surface of insulating layer of the power metal-oxide field effect transistor adopting the method for embodiments of the invention to be formed is not destroyed, and the second surface of insulating layer does not have electrode layer to remain yet, the stable performance of power metal-oxide field effect transistor.
Also there is the 3rd region between described first area and second area and adjacent with second area with described first area in embodiments of the invention, opening is formed in the electrode layer in described 3rd region and grinding barrier layer, full isolated material is filled, for follow-up formation electric capacity in described opening.In an embodiment of the present invention, the isolated material surfacing in the described opening of follow-up formation, the good stability of the electric capacity of formation, the stable performance of power metal-oxide field effect transistor.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (8)
1. a formation method for power metal-oxide field effect transistor, comprising:
Substrate is provided, described substrate comprises first area and the second area discrete with described first area, the live width of described first area is greater than the live width of second area, the substrate surface of described first area is formed with the first insulating barrier, the substrate surface of described second area is formed with the second insulating barrier, and described first insulating barrier and the second surface of insulating layer are formed with electrode layer, described electrode layer surface is formed with grinding barrier layer;
It is characterized in that, also comprise:
Perform the first grinding, remove the grinding barrier layer of the described first area of part and expose the electrode layer of described second area;
After described first grinding, perform the second grinding, remove the grinding barrier layer of the described first area of part and expose the second insulating barrier of described second area, the grinding selectivity ratio of ground slurry between electrode layer and grinding barrier layer that described second grinding adopts is large.
2. the formation method of power metal-oxide field effect transistor as claimed in claim 1, it is characterized in that, the ratio of the live width of described first area and the live width of second area is 5:1 ~ 20:1.
3. the formation method of power metal-oxide field effect transistor as claimed in claim 1, is characterized in that, described first grinding employing first ground slurry, described first ground slurry to the grinding rate of separator is
to the grinding rate on grinding barrier layer be
described second grinding employing second ground slurry, the grinding selectivity ratio of described second ground slurry between electrode layer and grinding barrier layer is greater than 30:1.
4. the formation method of power metal-oxide field effect transistor as claimed in claim 1, it is characterized in that, the thickness on described grinding barrier layer is
5. the formation method of power metal-oxide field effect transistor as claimed in claim 1, is characterized in that, after described first grinding, the thickness on described grinding barrier layer is for being greater than
6. the formation method of power metal-oxide field effect transistor as claimed in claim 1, is characterized in that, after described second grinding, the thickness on described grinding barrier layer is for being greater than
7. the formation method of power metal-oxide field effect transistor as claimed in claim 1, is characterized in that, after described second grinding, the thickness of described second insulating barrier is for being greater than
8. the formation method of power metal-oxide field effect transistor as claimed in claim 1, it is characterized in that, described substrate also comprises the 3rd region, and described 3rd region is between described first area and second area, and adjacent with second area with described first area; The substrate surface in described 3rd region is higher than the substrate surface of described first area and second area, and the substrate surface in described 3rd region is formed with gate insulation layer, and described gate electrode insulation surface is lower than the first insulating barrier and the second surface of insulating layer; Described electrode layer is also positioned at the described gate electrode insulation surface in the 3rd region; Described grinding barrier layer is also positioned at the described electrode layer surface in the 3rd region; Opening is formed in the grinding barrier layer in described 3rd region and electrode layer; Described grinding barrier layer surface is also formed with separator, and described separator fills full described opening; Perform after the first grinding and second grinds, the insulation surface in described 3rd region is lower than the grinding barrier layer surface of first area.
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| CN1490881A (en) * | 2002-10-01 | 2004-04-21 | 国际商业机器公司 | Enlaid gate multi-mesa MOS transistor and manufacture thereof |
| CN1726587A (en) * | 2002-12-14 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Manufacture of a trench-gate semiconductor device |
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| CN1490881A (en) * | 2002-10-01 | 2004-04-21 | 国际商业机器公司 | Enlaid gate multi-mesa MOS transistor and manufacture thereof |
| CN1726587A (en) * | 2002-12-14 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Manufacture of a trench-gate semiconductor device |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140403 |
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Effective date of registration: 20140403 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: Zuchongzhi road in Pudong Zhangjiang hi tech park Shanghai city Pudong New Area No. 1399 201203 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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