JPH0766285A - Manufacture of soil substrate - Google Patents

Abstract

PURPOSE:To provide an SOI substrate manufacturing method wherein element regions are formed uniform in thickness. CONSTITUTION:Element regions S1 and S2 are formed on a first Si substrate 1, an SiO2 insulating layer 3 is deposited thereon, a second Si substrate 2 is pasted thereon, and then the first Si substrate 1 is polished to make the element regions S1 and S2 exposed for the formation of an SOI substrate, wherein etching is so carried out as to make the surface of the SiO2 insulating layer 3 flush with the exposed surface of the thinnest element region S1 and the element region S2 protrude from the surface of the SiO2 insulating layer 3. A piled layer 5 formed of material of the same polishing rate with the element regions S1 and S2 is formed on the surface and then polished again to make the element regions S1 and S2 equal in thickness.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an SOI substrate in which a plurality of element regions made of silicon are formed on an insulating layer.

[0002]

2. Description of the Related Art An SOI (Silicon on insulator) substrate is one in which a silicon single crystal thin film is formed on an insulating layer, and by operating a CMOS transistor or the like on the silicon single crystal thin film, the operating speed is high. This is to obtain a semiconductor device that is resistant to soft errors and latch-up phenomena.

A method of manufacturing such an SOI substrate is shown in FIG.
It demonstrates in order of a process based on the cross-sectional view of FIG. In the following description, silicon is Si. First, FIG.
After the first Si substrate 1 is prepared as shown in (a), element regions S1 and S2 are formed by photolithography or the like as shown in FIG. 3 (b). As a result, the element regions S1 and S2 are formed in a convex shape on the surface of the first Si substrate 1.

Further, an insulating layer composed of the SiO ₂ layer 3 is deposited on the surface of the first Si substrate 1 on which the element regions S1 and S2 are formed, for example, about 500 nm to 1100 nm. Si
The O ₂ layer 3 has a hardness higher than that of the first Si substrate 1, and serves as a stopper when polishing the first Si substrate 1 in a later step.

Further, a polycrystalline Si layer 4 having a thickness of about 5 μm is formed on the SiO ₂ layer 3 to facilitate the attachment of the second Si substrate 2 in a later step. It should be noted that the surface of the polycrystalline Si layer 4 has, for example, 150 steps due to the element regions S1 and S2.
nm to about 200 nm remains.

Next, as shown in FIG. 3C, the surface of the formed polycrystalline Si layer 4 is polished by about 2 to 3 μm to flatten the surface of the polycrystalline Si layer 4. Then, as shown in FIG. 3D, the second Si is formed on the planarized polycrystalline Si layer 4.
The substrates 2 are bonded together, and as shown in FIG. 4A, the first Si substrate 1 and the second Si substrate 2 are turned upside down to chamfer the outer peripheral portion. This chamfering is for scraping off the end portion where the bonding of the second Si substrate 2 tends to be insufficient.

Next, as shown in FIG. 4B, the surface of the first Si substrate 1 is ground so that the first Si substrate 1 remains above the upper surface of the SiO ₂ layer 3 by about 5 to 7 μm. To In this state, as shown in FIG. 4C, the first Si substrate 1 is chemically polished to expose the element regions S1 and S2 using the surface of the SiO ₂ layer 3 as a stopper. As a result, the convex element regions S1 and S2 formed on the first Si substrate 1 are in a state of being covered with the SiO ₂ layer 3 except the exposed surface, and the element regions S1 and S2 are separated from each other. It becomes the substrate.

[0008]

However, the manufacturing method of such an SOI substrate has the following problems, and this problem will be described with reference to FIG. FIG. 5 shows the conventional S
FIG. 6 is a cross-sectional view of a main part in the method of manufacturing the OI substrate, and
FIG. 5A shows the state after the bonding in FIG. 5A, the middle of the polishing in FIG. 5B, and the state after the polishing in FIG. 5C. That is, as shown in FIG. 5A, in the state where the second Si substrate 2 is bonded, the first Si substrate 1 has a total thickness variat of the substrate itself.
There is a so-called thickness variation t which is ion: TTV).

Therefore, as shown in FIG. 5B, the first
In the middle of polishing the Si substrate 1 of
Despite the exposure of No. 1, the element region S2 is not yet exposed, which causes variations in polishing. As shown in FIG. 5C, this variation remains even after the polishing is completed, resulting in a difference in thickness between the element region S1 and the element region S2. The polishing rate is high when the area of the first Si substrate 1 is large, but slows down when the area of the first Si substrate 1 is narrowed as the SiO ₂ layer 3 is exposed. The difference in thickness between the element region S1 and the element region S2 is smaller than the thickness variation t of the first Si substrate 1.

However, if there is a difference in thickness between the element region S1 and the element region S2 as described above, the electrical characteristics of semiconductor elements such as CMOS transistors manufactured here will also vary, This is a problem in providing a stable product. Therefore, it is an object of the present invention to provide a method of manufacturing an SOI substrate that can make the thickness of each element region constant.

[0011]

The present invention is a method for manufacturing an SOI substrate, which has been made to solve such problems. That is, a plurality of element regions are formed on the Si substrate and S
In a method for manufacturing an SOI substrate in which an insulating layer that is harder than the i substrate is applied, a bonding substrate is further bonded, and then a Si substrate is polished to expose these element regions,
The insulating layer is etched so that the surface of the insulating layer is aligned with the exposed surface of the thinnest one element area of the exposed element area, and the other element area thicker than the one element area is insulated. Of the element region, and then a stacked layer made of a material having the same polishing rate as that of the element region is formed on the surface of the element region and the insulating layer, and then the stacked layer is polished to remove the protruding portions of other element regions. Then, the thickness of one element region and that of the other element region are matched.

[0012]

By adjusting the surface of the insulating layer to the exposed surface of the thinnest one element region, the other element regions thicker than the one element region project from the surface of the insulating layer. Will be done. In order to remove this protruding portion, a stacked layer made of a material having the same polishing rate as that of the element region is formed on the surface of the element region and the insulating layer as a cutting margin. By polishing this stacked layer, the stacked layer becomes flat, and further polishing also polishes the protruding portions of other element regions. If this polishing is performed until the one element region is exposed in the flattened state, the one element region and the other element region have the same thickness.

[0013]

EXAMPLE An example of a method for manufacturing an SOI substrate according to the present invention will be described below with reference to the drawings. 1 to 2 are cross-sectional views of relevant parts for explaining the method for manufacturing an SOI substrate of the present invention in the order of steps. It should be noted that the conventional S shown in FIGS.
Since each manufacturing process of the OI substrate is common, the process after the selective polishing shown in FIG. 4C will be described.

First, as shown in FIG. 1A, after selective polishing, there is a difference in thickness between the element region S1 and the element region S2. That is, the element regions S1 and S2 formed on the first Si substrate 1 via the polycrystalline Si layer 4 and the SiO ₂ layer 3 are provided on the second Si substrate 2, and each element region S1, The thicknesses of S2 are different from each other.

In this state, as shown in FIG. 1B, the SiO ₂ layer 3 is etched so that the exposed surface of the element region S1 is aligned with the surface of the SiO ₂ layer 3. That is, in order to make the exposed surface of the thinnest one of the element regions S1 and S2 (here, the element region S1) and the surface of the SiO ₂ layer 3 coincide with each other, the SiO ₂ layer 3 is, for example, a fluorine layer. Etch with hydrofluoric acid (HF). As a result, the exposed surface of the element region S1 and the surface of the SiO ₂ layer 3 coincide with each other, and the element region S2, which is thicker than the element region S1, becomes S
The iO ₂ layer 3 is projected from the surface by the thickness thereof.

By polishing the protruding portion of the element region S2, the element region S1 and the element region S2 can be made to have the same thickness. However, if only such a very thin protruding portion is to be polished, the other portion is not polished. As shown in FIG. 1C, a stacked layer 5 having the same polishing rate as that of the element regions S1 and S2 is formed on the surface of each of the element regions S1 and S2 and the SiO ₂ layer 3 as shown in FIG. 1C. .

That is, since only the protruding portion is polished,
The stacking layer 5 made of, for example, polycrystalline Si and having the same polishing rate as this portion (element region S2) is formed in an amount corresponding to the height of the protruding portion to provide a cutting margin. As a result, the step T formed on the stacked layer 5 is removed during polishing of the stacked layer 5, and the surface of the stacked layer 5 can be flattened. For example, when the step T is 50 nm, the stacked layer 5 having a thickness of 1200 nm or more is required to remove the step T. The minimum height of the stacked layer 5 required to remove the step T depends on the polishing conditions.

FIG. 2A shows a state where the stacked layer 5 is being removed by re-polishing. In this way, the step T of the stacked layer 5 is removed during the repolishing, the surface becomes flat, and the polishing is further continued.

Then, as shown in FIG. 2B, re-polishing is completed when the element regions S1 and S2 are exposed. That is, since the surface of the stacked layer 5 is flat during the re-polishing shown in FIG. 2A, and the polishing rate of the element region S2 is equal to the polishing rate of the stacked layer 5, the polishing should be continued as it is. Therefore, polishing progresses while maintaining a flat surface. Therefore, if the polishing is finished when the element region S1 is exposed, the SOI substrate in which the element region S1 and the element region S2 have the same thickness can be manufactured.

The element area S having a higher surface roughness accuracy
When it is desired to obtain the exposed surface of S1 and S2, mechanochemical polishing may be performed as re-polishing. The present invention is the same whether the first Si substrate 1 or the second Si substrate 2 is a chip-shaped one or a wafer-shaped one. Further, in this embodiment, the second Si substrate 2 is used as a bonding substrate for the first Si substrate 1, the SiO ₂ layer 3 is used as an insulating layer, and the polycrystalline Si layer 4 is used for bonding the bonding substrate. However, the present invention is not limited to these.

[0021]

As described above, the method of manufacturing an SOI substrate of the present invention has the following effects. That is, even if there are variations in the thickness of the silicon substrate for forming the plurality of element regions, the thickness of each element region in the final SOI substrate can be made constant. This makes it possible to make the electrical characteristics of the semiconductor elements such as CMOS transistors manufactured in the respective element regions uniform, thus providing a stable semiconductor product.

[Brief description of drawings]

FIG. 1 is a sectional view (No. 1) of an essential part for explaining a method for manufacturing an SOI substrate of the present invention in the order of steps, in which (a) shows a state after selective polishing
(B) shows etching of the SiO ₂ layer, and (c) shows formation of a stacked layer.

FIG. 2 is a cross-sectional view of a main part (part 2) for explaining the method of manufacturing an SOI substrate of the present invention in the order of steps, in which (a) is a state during repolishing
(B) shows the state after re-polishing.

FIG. 3 is a cross-sectional view for explaining a conventional example in the order of steps (No. 1)
Here, (a) shows the preparation of the first Si substrate, (b) shows the formation of the element region, (c) shows the planarization, and (d) shows the bonding of the second Si substrate.

4A and 4B are cross-sectional views illustrating a conventional example in the order of steps (No. 2)
Here, (a) shows chamfering, (b) shows surface grinding, and (c) shows selective polishing.

5A and 5B are cross-sectional views of a main part for explaining a conventional example, where FIG. 5A shows a state after bonding, FIG. 5B shows a state during polishing, and FIG.

[Explanation of symbols]

1 First Si Substrate 2 Second Si Substrate 3 SiO ₂ Layer 4 Polycrystalline Si Layer 5 Stacked Layer S1, S2 Element Area

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 7, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

Next, as shown in FIG. 4B, the surface of the first Si substrate 1 is ground so that the first Si substrate 1 remains about 5 to 7 μm above the upper surface of the SiO ₂ layer 3. To In this state, as shown in FIG. 4C, the first Si substrate 1 is chemically polished so that the element regions S1 and S2 are formed using the surface of the SiO ₂ layer 3 as a stopper.
As a result, the convex element regions S1 and S2 formed on the first Si substrate 1 are covered with the SiO ₂ layer 3 except the exposed surface, and the element regions S1 and S2 are separated from each other. It becomes the substrate.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

[0008]

However, the manufacturing method of such an SOI substrate has the following problems, and this problem will be described with reference to FIG. FIG. 5 shows the conventional S
FIG. 6 is a cross-sectional view of a main part in the method of manufacturing the OI substrate, and
5A shows the state after surface grinding, the state in the middle of polishing in FIG. 5B, and the state after polishing in FIG. 5C. That is, as shown in FIG. 5A, in the state where the second Si substrate 2 is bonded, the second Si substrate 2 has a maximum and minimum total thickness difference (thickness) of the substrate itself.
The first Si substrate 1 has a so-called thickness variation (TTV), a so-called thickness variation, and a surface-grinding precision variation t.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

5A and 5B are cross-sectional views of a main part for explaining a conventional example, in which FIG. 5A shows after surface grinding, FIG. 5B shows during polishing, and FIG. 5C shows after polishing.

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

Claims (1)

[Claims] 1. A plurality of element regions are formed on a silicon substrate, an insulating layer which is harder than the silicon substrate is applied, and a bonding substrate is further bonded, and then the silicon substrate is polished to expose the element regions. In the method for manufacturing an SOI substrate, after exposing the element region, the insulating layer is etched so that the surface of the insulating layer is aligned with the exposed surface of the thinnest one element region of the element region. And projecting another element region thicker than the one element region from the surface of the insulating layer, and then forming a stacked layer made of a material having the same polishing rate as that of the element region on the element region and the insulating layer. It is characterized in that it is formed on the surface, and the protruding portion of the other element region is removed by polishing the stacked layer so that the thicknesses of the one element region and the other element region are matched. SOI substrate Manufacturing method.