CN102222032B - Fault injection method of fault injection device of 1394 bus - Google Patents
Fault injection method of fault injection device of 1394 bus Download PDFInfo
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Abstract
The invention relates to a device and method for fault injection of a 1394 bus, which belong to the electronic testing field and aim to solve the problem of poor evaluation result accuracy of a testing method in the prior art because of failing to comprehensively consider the factors of all aspects of a fault mode. The logical saving input/output end of an FPGA (Field Programmable Gate Array) of the device in the invention is connected with the input/output end of an EEPROM (Electrically Erasable Programmable Read-Only Memory); the data buffering input/output end of the FPGA is connected with the input/output end of an SRAM (Static Random Access Memory); the first 1394 chip input/output end of the FPGA is connected with the first input/output end of a first physical layer interface chip; the second input/output end of the first physical layer interface chip serves as a first 1394 bus interface; the second 1394 chip input/output end of the FPGA is connected with the first input/output end of a second physical layer interface chip; and the second input/output end of the second physical layer interface chip serves as a second 1394 bus interface; and the FPGA is connected with a host computer through an RS232 (Recommend Standard 232) serial bus.
Description
Technical field
The present invention relates to a kind of fault filling method of fault injection device of 1394 buses, belong to the Electronic Testing field.
Background technology
Along with the raising that the developing rapidly of electronic technology, reliability of electronic equipment require, testability has become new research point.The intension of testability mainly comprises ATE (automatic test equipment) (ATE) and two aspects of built-in test (BIT).BIT refers to detection that system or equipment inside provides and the ability of isolated fault, whether reaches the requirement of testability design objective in order to estimate BIT, just must verify the ability of BIT, and Failure Injection Technique then is the effective means of checking BIT testability index.Failure Injection Technique is by the artificial fault of introducing, and observation BIT detects, the ability of isolated fault, thereby whether the testability index of verification system meets designing requirement, and makes improvement according to the design of test result system.
IEEE1394 predecessor is a technology of being drafted by Apple Computers (Apple) company in 1986, Apple is called live wire (FireWire), nineteen ninety-five IEEE formally announces it as a kind of industrial standard, official name is high performance serial bus IEEE1394-1995 standard.IEEE association had announced again the revised edition for the IEEE1394-1995 standard---IEEE1394a in 2000.Up-to-date version is the IEEE1394b standard of releasing in 2002 at present.
But the method for testing of prior art does not consider the integrality of fault mode, the each side factors such as versatility, validity and practicality of injection, so its evaluation result poor accuracy.
Summary of the invention
The present invention seeks to not consider the integrality of fault mode, the each side factors such as versatility, validity and practicality of injection for the method for testing that solves prior art, therefore the problem of its evaluation result poor accuracy provides a kind of fault filling method of fault injection device of 1394 buses.
The fault injection device of a kind of 1394 buses of the present invention, it comprises 1394 fault injectors and host, 1394 fault injectors comprise FPGA, the first physical layer interface chip, the second physical layer interface chip, SRAM and EEPROM,
The logic of FPGA is preserved input/output terminal and is linked to each other with the input/output terminal of EEPROM, the data buffering input/output terminal of FPGA links to each other with the input/output terminal of SRAM, the one 1394 chip input/output terminal of FPGA links to each other with the first input/output terminal of the first physical layer interface chip, the second input/output terminal of the first physical layer interface chip is the one 1394 bus interface, the 2 1394 chip input/output terminal of FPGA links to each other with the first input/output terminal of the second physical layer interface chip, the second input/output terminal of the second physical layer interface chip is the 2 1394 bus interface, and FPGA links to each other with host by the RS232 universal serial bus.
Based on the fault filling method of the fault injection device of described a kind of 1394 buses, the method may further comprise the steps:
Host sends to the fault injection order of fault injector and the forming process of fault parameter is:
Step 11, subscriber interface module receive the fault of user's input and inject order and parameter, and send to the parameter collection module;
Step 12, parameter collection module send to the fault injection module with fault injection order and the parameter of collecting;
Order and parameter that step 13, fault injection module identification fault is injected, and convert it into data stream and be transferred to respectively communication module and data analysis module;
Step 14, communication module send to 1394 fault injectors by the RS232 universal serial bus with fault injection order and parameter, carry out fault and inject.
The acquisition process that fault is injected the result is:
Step 21, communication module receive the feedback data of 1394 fault injectors, and send to as a result recycling module;
The feedback data of the transmission of step 22, data analysis module reception result recycling module, and and the fault that sends of fault injection module order and the parameter injected be analyzed, the correctness of coming validation fault to inject is obtained fault and is injected the result.
Advantage of the present invention: the present invention carries out experimental verification to the BIT of IEEE1394 bus, ATE etc.By artificially fault being incorporated on the IEEE1394 bus, and observation, analyzing total wire system be in the behavior that is injected under the failure condition, and for the testability experiment provides qualitative or quantitative evaluation result, the evaluation result of obtaining is accurate.
Description of drawings
Fig. 1 is the structural representation of the fault injection device of a kind of 1394 buses of the present invention;
Fig. 2 is the structural representation of FPGA;
Fig. 3 is the structural representation of host;
Fig. 4 is the syndeton synoptic diagram of FPGA and the first physical layer interface chip or the second physical layer interface chip;
Fig. 5 is the process flow diagram of the fault filling method of a kind of 1394 buses of the present invention;
Fig. 6 is the process flow diagram that fault that host sends to fault injector is injected the forming process of order and fault parameter;
Fig. 7 is the process flow diagram that fault is injected result's acquisition process.
Embodiment
Embodiment one: present embodiment is described below in conjunction with Fig. 1, the fault injection device of described a kind of 1394 buses of present embodiment, it comprises 1394 fault injectors and host 6,1394 fault injectors comprise FPGA1, the first physical layer interface chip 2, the second physical layer interface chip 3, SRAM4 and EEPROM5
The logic of FPGA1 is preserved input/output terminal and is linked to each other with the input/output terminal of EEPROM5, the data buffering input/output terminal of FPGA1 links to each other with the input/output terminal of SRAM4, the one 1394 chip input/output terminal of FPGA1 links to each other with the first input/output terminal of the first physical layer interface chip 2, the second input/output terminal of the first physical layer interface chip 2 is the one 1394 bus interface, the 2 1394 chip input/output terminal of FPGA1 links to each other with the first input/output terminal of the second physical layer interface chip 3, the second input/output terminal of the second physical layer interface chip 3 is the 2 1394 bus interface, and FPGA1 links to each other with host 6 by the RS232 universal serial bus.
The fault injection device of IEEE1394 bus of the present invention is when reality is used, be linked in 1394 universal serial bus by two 1394 bus interface series connection, in the situation of not injecting fault, can Physical layer with the data on 1394 buses receive, buffer memory and forwarding, make the equipment at bus two ends can finish normal bus communication.Simultaneously, can also introduce dissimilar faults to bus.Fault type basic on the bus comprises: physical fault and communication protocol fault.Physical fault is relevant with the bus electrical specification.IEEE1394 adopts difference transmission lines, each port has a control module to be responsible for mutual conversion between logical signal and physics twisted-pair feeder signal (TPA and TPB) signal, may reach 100 meters and 1394 physics twisted-pair feeder is the longest, transmission line can be subject to the electrical Interference of surrounding environment.The electric fault pattern that may occur on the transmission line Just because of this, comprises: voltage instability or voltage between the transmission line have surpassed rated range.Simultaneously, the intrinsic fault mode of bus hardware comprises: signal open circuit, saltus step, constant be 1 or 0.The communication protocol fault is relevant with bus protocol, specifically comprises signal data packet loss, damage, and transmission delay exceeds standard, buffer overflow etc.Consider the integrality of fault mode, the each side factors such as versatility, validity and practicality of injection, the fault that the present invention can inject is the communication protocol fault.
The present invention comprises two parts: host 6 and fault injector, control software is installed in the host 6, the hardware of fault injector for realizing injecting, the control software of host 6 provides friendly interpersonal interactive interface to the user, can accept user's input (mouse, keyboard etc.), and control the fault injection process to the injection order of fault injector transmission fault and parameter.Fault is injected order and is comprised injection beginning, time-out and end etc.; Fault parameter then comprises trouble duration, time between failures, fault type, the fault injection moment etc.Simultaneously, host end control software is also accepted the feedback of fault injector, injects the relevant information such as result, bus system state and shows with the form of chart to obtain fault.
Fault injector is core of the present invention, and fault implanting machine system is provided.Injector can carry out reception, buffer memory and the forwarding of 1394 bus datas under the control of host, can also carry out fault and inject, and makes data-bag lost, damage or delay.Fault injector is divided into four parts from hardware.
FPGA and peripheral circuit thereof.Mainly comprise a slice high-capacity and high-speed FPGA1 as processing core, the logic of FPGA1 is kept among a slice EEPROM5, and has been equipped with large capacity SRAM4 and cushions as mass data.
1394 interface chips.Mainly comprise the first physical layer interface chip 2 and the second physical layer interface chip 3, finish digital signal/conversion, data transmission, the equipment connection of physics twisted-pair feeder signal and the monitoring that removes, the transmission of rate signal, hang-up and restoring signal etc.
Communication network.The data exchange interface of failure definition injector and host, common mode has RS232, USB and Ethernet etc.Use in the present invention the RS232 mode.
Embodiment two: present embodiment is described below in conjunction with Fig. 2, present embodiment is described further embodiment one, FPGA1 comprises main control module 1-1, FPGA fault injection module 1-2, SRAM controller 1-3, a PHY/LINK interface module 1-4 and the 2nd PHY/LINK interface module 1-5
The first input/output terminal of FPGA fault injection module 1-2 links to each other with main control module 1-1, and the RS232 universal serial bus that passes through of main control module 1-1 links to each other with host 6,
The second input/output terminal of FPGA fault injection module 1-2 links to each other with the first input/output terminal of SRAM controller 1-3, and the second input/output terminal of SRAM controller 1-3 links to each other with SRAM4;
The 3rd input/output terminal of FPGA fault injection module 1-2 links to each other with the first input/output terminal of a PHY/LINK interface module 1-4, and the second input/output terminal of a PHY/LINK interface module 1-4 links to each other with the first physical layer interface chip 2;
The 4th input/output terminal of FPGA fault injection module 1-2 links to each other with the first input/output terminal of the 2nd PHY/LINK interface module 1-5, and the second input/output terminal of the 2nd PHY/LINK interface module 1-5 links to each other with the second physical layer interface chip 3.
PHY/LINK is the conversion of digital signal/physics twisted-pair feeder signal, bi-directional conversion.
1) main control module 1-1: and the control software communication in the host 6, order and parameter received, with control injection process and result's recovery.
2) FPGA fault injection module 1-2.Be subjected to the control of main control module 1-1, carry out buffer memory, forwarding and the fault injection process of 1394 bus datas.When not injecting fault, it accepts the input of an end PHY/LINK interface module, and data buffer storage in SRAM4, is then taken out the PHY/LINK interface module that data are passed to the other end.When needing to inject fault, FPGA fault injection module 1-2 is to taking out the PHY/LINK interface module of passing to again the other end after data are made amendment, postponed.
3) a PHY/LINK interface module 1-4 and the 2nd PHY/LINK interface module 1-5: be subjected to the control of FPGA fault injection module 1-2, be used for finishing link layer to the access of the first physical layer interface chip 2 or the second physical layer interface chip 3.
4) SRAM controller 1-3.Be subjected to the control of FPGA fault injection module 1-2, be used for finishing the read and write access to the large capacity SRAM4 in outside.
Embodiment three: present embodiment is described below in conjunction with Fig. 3, present embodiment is described further embodiment one, host 6 comprises subscriber interface module 6-1, data analysis module 6-2, parameter collection module 6-3, fault injection module 6-4, as a result recycling module 6-5 and communication module 6-6
The communication ends of communication module 6-6 links to each other with 1394 fault injectors by the RS232 universal serial bus, the fault command input end of communication module 6-6 links to each other with the Fisrt fault order output terminal of fault injection module 6-4, the return data output terminal of communication module 6-6 links to each other with the input end of recycling module 6-5 as a result, the output terminal of recycling module 6-5 links to each other with the first input end of data analysis module 6-2 as a result, the second fault order output terminal of fault injection module 6-4 links to each other with the second input end of data analysis module 6-2, the output terminal of data analysis module 6-2 shows that with the data of subscriber interface module 6-1 input end links to each other, subscriber interface module 6-1 receives user's input command and parameter, the output terminal of subscriber interface module 6-1 links to each other with the input end of parameter collection module 6-3, and the output terminal of parameter collection module 6-3 links to each other with the input end of fault injection module 6-4.
Subscriber interface module 6-1: friendly interpersonal interactive interface is provided, can accepts user's input (mouse, keyboard etc.), make the user can carry out the operations such as fault type selection, parameter input; The information such as the result that the demonstration fault is injected and bus state.
Data analysis module 6-2: the information such as the injection result that the fault parameter of analysis user setting, injector return and bus state, with the correctness of validation fault injection.These information are further processed and send to subscriber interface module 6-1 and show.
Parameter collection module 6-3: from the input that subscriber interface module 6-1 accepts the user, collect fault and inject order and parameter and send to fault injection module 6-4.
Fault injection module 6-4: identify order and the data of fault injection and corresponding parameter is changed into data stream transmitting and arrive communication module 6-6 and data analysis module 6-2, with the work of control injector.
Recycling module 6-5 as a result: collect fault by recycling module 6-5 as a result from fault injector 6-4 and inject the relevant information such as result, bus state and feed back to data analysis module 6-1 for further processing.
Embodiment four: below in conjunction with Fig. 4 present embodiment is described, present embodiment is described further embodiment one, and the first physical layer interface chip 2 and the second physical layer interface chip 3 are all selected the TSB41AB3 chip.
FPGA1 is identical with the annexation of the first physical layer interface chip 2 and the annexation of FPGA1 and the second physical layer interface chip 3, all as shown in Figure 4.
The present invention adopts IEEE1394 physical layer interface chip TSB41AB3 to reduce the difficulty of fpga logic design.TSB41AB3 is the physical chip of supporting 3 cable interfaces, by to 24.576MHz crystal oscillator frequency multiplication as clock source, maximum transmission rate reaches 400Mbps, supports the PHY/LINK interface of standard.The PHY/LINK interface mainly relies on CTL[1:0], D[7:0], LREQ, LPS, LINKON and SCLK signal wire come control signal and several data bag between physical layer for transmission and the link layer module.The interface main signal is defined as follows:
1) D[7:0]: bidirectional data line.The PHY/LINK interface is supported 100Mbps, 200Mbps, three kinds of transmission speeds of 400Mbps, uses respectively D[7:6 according to transmission speed], D[7:4], D[7:0], untapped data line sets to 0.
2) CTL[1:0]: two-way control line, be used for to determine D[7:0] transmission direction.
3) LREQ: link layer sends request type that a string bit stream asks access to universal serial bus, bit stream to define to be sent out and the transmission speed of packet with LREQ to Physical layer, and it is different to press request type, and bitstream length is that 6～17bits does not wait.
4) LPS: indication link layer duty.
5) LINKON: the link start signal, the notifying link layer powers on.Link layer begins to export the LPS signal after detecting the LINKON signal automatically.
Embodiment five: below in conjunction with Fig. 5 present embodiment is described, based on the fault filling method of the fault injection device of embodiment one described a kind of 1394 buses, the method may further comprise the steps:
Embodiment six: present embodiment is described further embodiment five, and the fault in the step 1 is injected order and comprised that injection begins, injection suspends and inject the finish command; Fault parameter comprises trouble duration, time between failures, fault type and fault injection constantly.
Embodiment seven: below in conjunction with Fig. 6 present embodiment is described, present embodiment is described further embodiment five, and host 6 sends to the fault injection order of fault injector and the forming process of fault parameter is:
Step 11, subscriber interface module 6-1 receive the fault of user's input and inject order and parameter, and send to parameter collection module 6-3;
Step 12, parameter collection module 6-3 send to fault injection module 6-4 with fault injection order and the parameter of collecting;
Order and parameter that step 13, fault injection module 6-4 identification fault is injected, and convert it into data stream and be transferred to respectively communication module 6-6 and data analysis module 6-2;
Step 14, communication module 6-6 send to 1394 fault injectors by the RS232 universal serial bus with fault injection order and parameter, carry out fault and inject.
Embodiment eight: below in conjunction with Fig. 7 present embodiment is described, present embodiment is described further embodiment five, and the acquisition process that the fault in the step 2 is injected the result is:
Step 21, communication module 6-6 receive the feedback data of 1394 fault injectors, and send to as a result recycling module 6-5;
The feedback data of the transmission of step 22, data analysis module 6-2 reception result recycling module 6-5, and and the fault that sends of fault injection module 6-4 order and the parameter injected be analyzed, the correctness of coming validation fault to inject is obtained fault and is injected the result.
Claims (3)
1. fault filling method based on the fault injection device of 1394 buses, the fault injection device of described 1394 buses comprises 1394 fault injectors and host (6), 1394 fault injectors comprise FPGA (1), the first physical layer interface chip (2), the second physical layer interface chip (3), SRAM (4) and EEPROM (5)
The logic of FPGA (1) is preserved input/output terminal and is linked to each other with the input/output terminal of EEPROM (5), the data buffering input/output terminal of FPGA (1) links to each other with the input/output terminal of SRAM (4), the one 1394 chip input/output terminal of FPGA (1) links to each other with the first input/output terminal of the first physical layer interface chip (2), the second input/output terminal of the first physical layer interface chip (2) is the one 1394 bus interface, the 2 1394 chip input/output terminal of FPGA (1) links to each other with the first input/output terminal of the second physical layer interface chip (3), the second input/output terminal of the second physical layer interface chip (3) is the 2 1394 bus interface, and FPGA (1) links to each other with host (6) by the RS232 universal serial bus;
It is characterized in that the method may further comprise the steps:
Step 1, host (6) receive user's input command, and fault injection order and fault parameter are sent to fault injector;
Step 2, fault injector return to host (6) with data, obtain fault and inject the result;
Fault in the step 1 is injected order and is comprised that injection begins, injection suspends and inject the finish command; Fault parameter comprises trouble duration, time between failures, fault type and fault injection constantly.
2. the fault filling method of the fault injection device based on 1394 buses according to claim 1, host (6) comprises subscriber interface module (6-1), data analysis module (6-2), parameter collection module (6-3), fault injection module (6-4), as a result recycling module (6-5) and communication module (6-6)
The communication ends of communication module (6-6) links to each other with 1394 fault injectors by the RS232 universal serial bus, the fault command input end of communication module (6-6) links to each other with the Fisrt fault order output terminal of fault injection module (6-4), the return data output terminal of communication module (6-6) links to each other with the input end of recycling module (6-5) as a result, the output terminal of recycling module (6-5) links to each other with the first input end of data analysis module (6-2) as a result, the second fault order output terminal of fault injection module (6-4) links to each other with the second input end of data analysis module (6-2), the output terminal of data analysis module (6-2) shows that with the data of subscriber interface module (6-1) input end links to each other, subscriber interface module (6-1) receives user's input command and parameter, the output terminal of subscriber interface module (6-1) links to each other with the input end of parameter collection module (6-3), the output terminal of parameter collection module (6-3) links to each other with the input end of fault injection module (6-4)
It is characterized in that host (6) sends to the fault injection order of fault injector and the forming process of fault parameter is:
Step 11, subscriber interface module (6-1) receive the fault of user's input and inject order and parameter, and send to parameter collection module (6-3);
Step 12, parameter collection module (6-3) send to fault injection module (6-4) with fault injection order and the parameter of collecting;
Order and parameter that step 13, fault injection module (6-4) identification fault is injected, and convert it into data stream and be transferred to respectively communication module (6-6) and data analysis module (6-2);
Step 14, communication module (6-6) send to 1394 fault injectors by the RS232 universal serial bus with fault injection order and parameter, carry out fault and inject.
3. the fault filling method of the fault injection device based on 1394 buses according to claim 1 is characterized in that, the acquisition process that the fault in the step 2 is injected the result is:
Step 21, communication module (6-6) receive the feedback data of 1394 fault injectors, and send to as a result recycling module (6-5);
The feedback data of the transmission of step 22, data analysis module (6-2) reception result recycling module (6-5), and and the fault that sends of fault injection module (6-4) order and the parameter injected be analyzed, the correctness of coming validation fault to inject is obtained fault and is injected the result.
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| CN104572389A (en) * | 2013-10-18 | 2015-04-29 | 神讯电脑(昆山)有限公司 | Automatic testing method of 1394 interface |
| CN105823909B (en) * | 2015-01-07 | 2018-11-16 | 中国航空综合技术研究所 | A kind of rear-driving type direct fault location interface adapter suitable for electronic product |
| CN104778104B (en) * | 2015-04-20 | 2018-12-04 | 北京全路通信信号研究设计院集团有限公司 | A kind of error-detecting method and serial data communications busses of serial data communications busses |
| CN105067933B (en) * | 2015-08-31 | 2018-08-31 | 中国人民解放军63908部队 | General-purpose system and test method for electronics testability demonstration and assessment |
| CN107818271B (en) * | 2016-09-14 | 2023-08-29 | 国民技术股份有限公司 | Fault injection analysis method and system based on chip layout |
| CN108334060B (en) * | 2018-03-15 | 2019-10-18 | 北京润科通用技术有限公司 | A kind of bus failure injection device |
| CN108494599B (en) * | 2018-03-29 | 2021-09-07 | 北京润科通用技术有限公司 | ARINC664 bus fault injection system and method |
| CN108958997B (en) * | 2018-05-23 | 2022-03-04 | 哈尔滨工业大学 | Serial bus fault simulation system and simulation method |
| CN109976960A (en) * | 2019-03-29 | 2019-07-05 | 北京润科通用技术有限公司 | A kind of bus test data method for implanting and device |
| CN113064782B (en) * | 2021-03-22 | 2023-03-24 | 山东英信计算机技术有限公司 | Memory error injection automation system, use method and medium |
| CN114915579A (en) * | 2022-03-15 | 2022-08-16 | 山东大学 | System and method for testing industrial Ethernet safety performance |
| CN115079671A (en) * | 2022-06-30 | 2022-09-20 | 哈尔滨工业大学（威海） | Fault injection system of serial multi-bus |
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