CN107818271B - Fault injection analysis method and system based on chip layout - Google Patents
Fault injection analysis method and system based on chip layout Download PDFInfo
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- CN107818271B CN107818271B CN201610826655.3A CN201610826655A CN107818271B CN 107818271 B CN107818271 B CN 107818271B CN 201610826655 A CN201610826655 A CN 201610826655A CN 107818271 B CN107818271 B CN 107818271B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
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Abstract
The invention discloses a fault injection analysis method and system based on a chip layout. The method comprises the following steps: acquiring a chip layout of a chip to be tested; performing fault injection in a selected area on the chip to be tested; collecting operation data of the chip to be tested in a fault injection state; analyzing the state of the chip to be tested according to the collected operation data, and further judging the sensitivity of the selected area to fault injection; and distinguishing and marking the corresponding areas of the chip layout according to the sensitivity. By the mode, layout analysis and fault injection analysis are combined, distinguishing marks are carried out on the layout according to different sensitivity of different chip areas to fault injection, and further sensitive areas can be positioned better and rapidly, and guiding evaluation can be carried out on chip protection design intuitively.
Description
Technical Field
The invention relates to the field of chip safety, in particular to a fault injection analysis method and system based on a chip layout.
Background
With the continuous promotion of EMV migration and domestic gold card engineering, the release of financial IC cards (bank IC cards, financial social security cards and the like) and the popularization of mobile payment, the demand of the market for smart card chips is increasing, and the smart card chip industry enters a rapid growth period. However, with the increasing popularity of smart cards, various attack techniques for smart cards are also developing. For a financial IC card, the security is a critical ring, and how to accurately position the sensitive area of the chip in the chip verification stage, so that important protection is ensured during chip design, sensitive information of the chip is ensured not to be leaked, and the method is a problem that important consideration is required in the process of designing the financial IC chip.
In the cryptanalysis, side channel cryptanalysis and aiming at a security chip comprises three attack modes: non-invasive attacks, semi-invasive attacks and invasive attacks can be performed with an efficient attack and hacking.
Fault injection is a semi-invasive attack whose principle is to try to introduce some erroneous behaviour in the program logic of the chip by changing the environmental parameters (the electrical properties of the chip will change with different voltages, temperatures, light, ionizing radiation and surrounding magnetic fields), to bring the chip into an uncertain operating state, such as disturbing the program flow or making the algorithm result wrong, and to implement an attack on the chip in this state. The implementation cost of fault injection is not high, but the attack success rate is high, and a significant security threat is formed to the chip. The common fault injection means are many, including abnormal voltage, frequency, temperature, radiation, light, eddy current and other environmental factors, and also include voltage burr attack, local light attack, electromagnetic manipulation attack and the like.
In the prior art, the most effective fault injection attack means is laser injection, for laser fault injection, the front protection of the chip is relatively easy, the front of the chip can be easily protected from attack, but the protection difficulty is very high for the attack on the back of the chip, on the premise of comprehensively considering the cost, a designer is required to have targeted key protection when designing a protection scheme, how to realize key protection of a sensitive area, and a chip verification stage is required to prepare and locate the sensitive area of the chip, so that redundancy of the protection scheme is avoided.
In view of this, there is a strong need for a solution that can effectively distinguish between sensitive and non-sensitive areas of a chip.
Disclosure of Invention
The invention provides a fault injection analysis method and a fault injection analysis system based on a chip layout, which are used for realizing quick positioning of areas with different sensitivities of a chip.
In order to solve the technical problems, the invention provides a fault injection analysis method based on a chip layout, which comprises the following steps: acquiring a chip layout of a chip to be tested; performing fault injection in a selected area on the chip to be tested; collecting operation data of the chip to be tested in a fault injection state; analyzing the state of the chip to be tested according to the collected operation data, and further judging the sensitivity of the selected area to fault injection; and distinguishing and marking the corresponding areas of the chip layout according to the sensitivity.
Before the step of fault injection in the selected area of the chip to be tested, the method further comprises the following steps: collecting operation data of the chip to be tested in a fault-free injection state to obtain an operation curve of the chip to be tested; determining an operation key time point of the chip to be tested according to the operation curve; the method for collecting the operation data of the chip to be tested in the fault injection state comprises the following steps: and collecting operation data of the chip to be tested in the fault injection state at the operation key time point.
The step of distinguishing and marking the corresponding area of the chip layout according to the sensitivity comprises the following steps: and marking the sensitive area of the chip to be tested on the chip layout according to the sensitivity.
The method for marking the sensitive area of the chip to be tested on the chip layout according to the sensitivity comprises the following steps: and marking sensitive parameters of a sensitive area of the chip to be tested on the chip layout.
The method for marking the sensitive area of the chip to be tested on the chip layout according to the sensitivity comprises the following steps: and distinguishing and marking different sensitive areas of the chip to be tested on the chip layout according to the sensitivity.
Wherein the different sensitive areas include a combination of at least two of an error area, a reset area, and an alarm area.
The step of distinguishing and marking the corresponding area of the chip layout according to the sensitivity further comprises the following steps: marking the non-sensitive area of the chip to be tested on the chip layout according to the sensitivity, wherein the marks of the non-sensitive area and the sensitive area are different.
The chip layout is a back layout of the chip to be tested, and the step of performing fault injection in the selected area of the chip to be tested comprises the following steps: and performing fault injection on the selected area on the back surface of the chip to be tested.
In order to solve the technical problems, the invention provides a fault injection analysis system based on a chip layout, which comprises: the workstation is used for acquiring and displaying the chip layout of the chip to be tested; the fault injection platform is used for carrying out fault injection in a selected area on the chip to be tested; the data acquisition device is used for acquiring the operation data of the chip to be tested in the fault injection state; the workstation analyzes the state of the chip to be tested according to the collected operation data, further judges the sensitivity of the selected area to fault injection, and further carries out distinguishing marking on the corresponding area of the chip layout according to the sensitivity.
The workstation further marks the sensitive area of the chip to be tested on the chip layout according to the sensitivity.
The workstation further marks sensitive parameters of the sensitive area of the chip to be tested on the chip layout.
The workstation further performs differentiated marking on different sensitive areas of the chip to be tested on the chip layout according to the sensitivity.
Wherein the different sensitive areas include a combination of at least two of an error area, a reset area, and an alarm area.
The workstation further marks the non-sensitive area of the chip to be tested on the chip layout according to the sensitivity, wherein the marks of the non-sensitive area and the sensitive area are different.
The chip layout is a back layout of the chip to be tested, and the fault injection platform performs fault injection in a selected area on the back of the chip to be tested.
The fault injection analysis method and system based on the chip layout provided by the invention have the beneficial effects that: the layout analysis and the fault injection analysis are combined, and distinguishing marks are carried out on the layout according to different sensitivity of different chip areas to fault injection, so that the sensitive areas can be positioned better and quickly, and the chip protection design can be intuitively and instructively evaluated. The areas with different sensitivities are protected with different intensities, so that the defect of adding a protection function in the non-sensitive position of the chip is avoided, and the cost is reduced.
Drawings
For a clearer description of the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a flow chart of a fault injection analysis method according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a chip layout used in the fault injection analysis method shown in FIG. 1;
FIG. 3 is a schematic diagram of a first marking mode of the chip layout shown in FIG. 2;
FIG. 4 is a schematic diagram of a second tagging approach of the chip layout shown in FIG. 2;
FIG. 5 is a schematic diagram of a third marking mode of the chip layout shown in FIG. 2;
fig. 6 is a schematic block diagram of a fault injection analysis system according to a second embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a flowchart of a fault injection analysis method according to a first embodiment of the present invention. The fault injection analysis method of the present embodiment includes the following steps:
step 101, obtaining a chip layout of a chip to be tested;
step 102, performing fault injection in a selected area on a chip to be tested;
step 103, collecting operation data of the chip to be tested in a fault injection state;
104, analyzing the state of the chip to be tested according to the collected operation data, and further judging the sensitivity of the selected area to fault injection;
step 105, distinguishing and marking the corresponding area of the chip layout according to the sensitivity;
step 106, judging whether the analysis is finished, if so, entering step 107, and if not, entering step 108;
step 107, ending the analysis flow;
step 108, selecting other fault injection regions, and returning to step 102, thereby implementing analysis of multiple regions of the chip.
By the mode, layout analysis and fault injection analysis are combined, distinguishing marks are carried out on the layout according to different sensitivity of different chip areas to fault injection, and further sensitive areas can be positioned better and rapidly, and guiding evaluation can be carried out on chip protection design intuitively.
The above steps will be described in detail with reference to specific embodiments, and it should be noted that in the following embodiments, the back side of the chip is taken as an example, that is, the chip layout is selected as the back side layout of the chip to be tested, and fault injection is performed in the selected area on the back side of the chip to be tested. It is fully within the contemplation of those skilled in the art, after reading the present disclosure, to apply the above described analysis method to other locations of the chip.
In step 101, to obtain a backside layout of a chip, a backside process is required to be performed on the chip, that is, a decapsulation operation is performed on the chip, and a stripping process is performed on the backside of the chip. In a preferred processing mode, firstly, hot concentrated nitric acid is dripped on the area of the back surface of the chip corresponding to the surface of the epoxy resin, and the epoxy resin is corroded to expose a bare chip (die); then, removing the passivation layer on the surface of the bare chip by using hot phosphoric acid; then, the residue was rinsed with acetone, and the chip was cleaned with ultrasonic waves, thereby completing the peeling treatment.
And then, further acquiring the chip layout subjected to the stripping treatment, and carrying out layout treatment on the chip layout. For example, the obtained original chip layout is subjected to gray scale processing to form a gray scale chip layout, which can be specifically shown in fig. 2.
In step 102, there are many common fault injection means, including abnormal voltage, frequency, temperature, radiation, light, eddy current, and other environmental factors, as well as voltage glitch attack, local light attack, electromagnetic manipulation attack, and the like. In the following embodiments, laser fault injection is described in detail as an example, but those skilled in the art can fully appreciate that fault injection can be implemented by any one of the fault injection means or combination as described above or known in the art after reading the present invention.
In step 103, the operation data of the chip to be tested in the fault injection state is preferably collected by a filter or other data collection device in cooperation with sensors such as an external resistor, a probe, a coil and the like. The collected data can be any data capable of reflecting the running state of the chip, such as current, voltage, electric field, magnetic field and the like. When the probe mode is adopted for data acquisition, the probe can be utilized to directly detect operation data on key target wires (such as power supply branch wires and password circuit signal wires) in the chip to be detected. For example, the voltage or current signal is obtained by placing an opening on the chip to be tested and bonding the probe to the critical target trace, or the electric field or magnetic field signal on the critical target trace is obtained by placing the probe close to the chip surface.
In addition, in a preferred embodiment, before step 103, operation data of the chip to be tested in the fault-free injection state is collected in advance to obtain an operation curve (e.g., a power curve) of the chip to be tested, and an operation key time point of the chip to be tested is determined according to the operation curve. Therefore, in step 103, the operation data of the chip to be tested in the fault injection state only needs to be collected at the operation key time point.
In step 104, it is determined whether the chip is abnormal in operation in the fault injection state according to the collected operation data, if the chip is abnormal in operation, the fault injection area is considered to be a sensitive area, and if the chip is still capable of operating normally, the fault injection area is considered to be a non-sensitive area. In a preferred embodiment, the fault injection parameters are changed during the fault injection process, and multiple sets of operation data of different fault injection parameters are acquired to perform statistical analysis, and finally the sensitivity of the fault injection area is determined. For example, if the chip still can operate normally under a plurality of fault injection parameters, the fault injection region is a non-sensitive region, and under a certain or a plurality of specific fault injection parameters, the chip is abnormal in operation, and the fault injection region is considered to be a sensitive region. At this time, it is preferable to record a sensitive parameter of the fault injection region, i.e., a fault injection parameter (e.g., laser power, etc.) that enables an effective attack on the fault injection region.
In addition, the sensitive area can be further divided according to the type of abnormal operation of the chip, for example, the abnormal operation can include error operation result, chip reset and alarm, and the sensitive area can be further divided into an error area, a reset area and an alarm area.
In step 105, the sensitive area of the chip to be tested is preferably marked on the chip layout according to the sensitivity of the fault injection area to the fault injection. Specifically, in step 104, if it is determined that the chip operation is abnormal, the position corresponding to the current fault injection region is marked on the chip layout. Furthermore, along with the circulation of the flow, a plurality of similar marks can be displayed on the chip layout, so that the sensitive area of the chip to be tested can be visually presented through the chip layout, and the sensitive area is particularly shown in fig. 3. Wherein the delta mark represents the sensitive area of the chip to be tested. Of course, the sensitive parameters of the sensitive areas of the chip to be tested can be marked on the chip layout, so that a technician can intuitively acquire the effective attack means corresponding to each sensitive area through the chip layout.
Further, in step 104, under the condition that different sensitive areas can be effectively distinguished according to the running state of the chip, different sensitive areas of the chip to be tested can be marked in a differentiated manner, that is, different sensitive areas are represented by different marks, as shown in fig. 4. The sensitive area marked by the chip layout may be a combination of at least two of the error area, the reset area, and the alarm area described above. For example, in fig. 4, "Δmarkrepresents an error region of the chip to be tested," o "mark represents a reset region of the chip to be tested," v "mark represents an alarm region of the chip to be tested.
In addition, the non-sensitive area of the chip to be tested can be marked on the chip layout according to the sensitivity, and the marks of the non-sensitive area and the sensitive area are different, as shown in fig. 5. For example, in fig. 5, "Δmarkrepresents an error region of the chip to be tested," o "mark represents a reset region of the chip to be tested," v "mark represents an alarm region of the chip to be tested, the above three marks correspond to a sensitive region of the chip to be tested, and" ζ "mark represents a non-sensitive region of the chip to be tested.
Through the mode, a technician can intuitively distinguish the sensitive area and the non-sensitive area of the chip to be detected and even distinguish different sensitive areas through the chip layout, so that subsequent attack and protection design can be carried out.
In step 106, it is determined whether the entire back surface or the predetermined area of the chip to be tested has been traversed, if the entire back surface or the predetermined area of the chip to be tested has been traversed, the analysis is considered to be completed, and step 107 is performed, if there is an undetected area, step 108 is performed, and then the fault injection area is reselected and the above-described flow is re-executed.
Referring to fig. 6, fig. 6 is a schematic block diagram of a fault injection analysis system according to a second embodiment of the present invention. The fault injection analysis system of the present embodiment includes a workstation 61, a fault injection platform 62, and a data acquisition device 63.
In this embodiment, the workstation 61 is configured to acquire and display a chip layout of the chip 60 to be tested, the fault injection platform 62 is configured to perform fault injection in a selected area on the chip 60 to be tested, and the data acquisition device 63 is configured to acquire operation data of the chip 60 to be tested in a fault injection state. The workstation 61 analyzes the state of the chip 60 to be tested according to the collected operation data, further judges the sensitivity of the selected area to fault injection, and the workstation 61 further marks the corresponding area of the chip layout in a distinguishing mode according to the sensitivity. In a preferred embodiment, the chip layout may be a backside layout of the chip under test 60, with the fault injection platform 62 performing fault injection at selected areas on the backside of the chip under test 60. Those skilled in the art will fully appreciate, upon reading the present disclosure, that other locations of the chip may be analyzed for fault injection using the system described above.
In a preferred embodiment, the workstation 61 marks the sensitive area of the chip to be tested on the chip layout according to the sensitivity, and the workstation 61 preferably further marks the sensitive parameters of the sensitive area of the chip to be tested on the chip layout.
In another preferred embodiment, the workstation 61 further discriminatory marks different sensitive areas of the chip to be tested on the chip layout according to sensitivity. The different sensitive areas include a combination of at least two of an error area, a reset area, and an alarm area.
In another preferred embodiment, the workstation 61 further marks the non-sensitive areas of the chip to be tested on the chip layout according to the sensitivity, wherein the marks of the non-sensitive areas and the sensitive areas are different.
The specific operation flow and the specific implementation manner of the above elements are described in detail in the fault injection analysis method in conjunction with fig. 1, and are not described herein.
The embodiment of the invention combines layout analysis and fault injection analysis, and carries out differentiated marking on the layout according to different sensitivity of different chip areas to fault injection, thereby being capable of better and rapidly positioning the sensitive area and intuitively carrying out guiding evaluation on chip protection design. For example, areas with different sensitivity degrees are protected with different intensities, the defect that a protection function is added in a non-sensitive position of a chip is avoided, and the cost is reduced. In addition, the sensitive parameters of the sensitive area of the chip are further marked on the layout, so that the sensitive area can be displayed on layout analysis, the most effective attack parameters can be displayed, the attack parameters are displayed and analyzed, and the fault injection parameters are efficiently selected. In addition, under the black box attack, the sensitive area related to the algorithm operation can be positioned with high probability by the fault injection analysis method and the system, and the main functional area (such as the physical position of the algorithm module, the physical position of the CPU, the physical position of the storage unit and the like) of the chip can be reversed.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (7)
1. The fault injection analysis method based on the chip layout is characterized by comprising the following steps of:
acquiring a chip layout of a chip to be tested;
performing fault injection in a selected area on the chip to be tested;
collecting operation data of the chip to be tested in a fault injection state;
analyzing the state of the chip to be tested according to the collected operation data, and further judging the sensitivity of the selected area to fault injection;
distinguishing and marking the corresponding areas of the chip layout according to the sensitivity;
the step of distinguishing and marking the corresponding area of the chip layout according to the sensitivity comprises the following steps: marking sensitive areas of the chip to be tested on the chip layout according to the sensitivity,
the step of marking the sensitive area of the chip to be tested on the chip layout according to the sensitivity comprises the following steps: marking sensitive parameters of a sensitive area of the chip to be tested on the chip layout, wherein the sensitive parameters comprise fault injection parameters for realizing effective attack on the selected area; and distinguishing and marking different sensitive areas of the chip to be tested on the chip layout according to the sensitivity, wherein the different sensitive areas comprise at least two combinations of an error area, a reset area and an alarm area.
2. The fault injection analysis method according to claim 1, wherein before the step of performing fault injection on the selected area on the chip to be tested, further comprising:
collecting operation data of the chip to be tested in a fault-free injection state to obtain an operation curve of the chip to be tested;
determining an operation key time point of the chip to be tested according to the operation curve;
the step of collecting the operation data of the chip to be tested in the fault injection state comprises the following steps:
and collecting operation data of the chip to be tested in the fault injection state at the operation key time point.
3. The fault injection analysis method according to claim 1, wherein the step of differentially marking the corresponding region of the chip layout according to sensitivity further comprises:
marking a non-sensitive area of the chip to be tested on the chip layout according to the sensitivity, wherein the marks of the non-sensitive area and the sensitive area are different.
4. The fault injection analysis method according to claim 1, wherein the chip layout is a backside layout of the chip to be tested, and the step of performing fault injection on the selected area on the chip to be tested comprises: and performing fault injection on the selected area on the back surface of the chip to be tested.
5. A fault injection analysis system based on a chip layout, the system comprising:
the workstation is used for acquiring and displaying the chip layout of the chip to be tested;
the fault injection platform is used for carrying out fault injection on the selected area on the chip to be tested;
the data acquisition device is used for acquiring the operation data of the chip to be tested in the fault injection state;
wherein the workstation analyzes the state of the chip to be tested according to the collected operation data, further judges the sensitivity of the selected area to fault injection, and further carries out distinguishing marking on the corresponding area of the chip layout according to the sensitivity,
the distinguishing and marking the corresponding area of the chip layout according to the sensitivity comprises the following steps: marking sensitive parameters of a sensitive area of the chip to be tested on the chip layout, wherein the sensitive parameters comprise fault injection parameters for realizing effective attack on the selected area; and distinguishing and marking different sensitive areas of the chip to be tested on the chip layout according to the sensitivity, wherein the different sensitive areas comprise at least two combinations of an error area, a reset area and an alarm area.
6. The fault injection analysis system of claim 5, wherein the workstation further marks non-sensitive regions of the chip under test on the chip layout based on the sensitivity, wherein the marks of the non-sensitive regions and the sensitive regions are different.
7. The fault injection analysis system of claim 5, wherein the chip layout is a backside layout of the chip under test, and the fault injection platform performs fault injection in a selected area on the backside of the chip under test.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6484276B1 (en) * | 1999-10-25 | 2002-11-19 | Lucent Technologies Inc. | Method and apparatus for providing extensible object-oriented fault injection |
| JP2006120793A (en) * | 2004-10-20 | 2006-05-11 | Iwate Toshiba Electronics Co Ltd | Wafer marking system and failure chip marking method |
| CN102222032A (en) * | 2011-05-20 | 2011-10-19 | 哈尔滨工业大学 | Device and method for fault injection of 1394 bus |
| CN102750216A (en) * | 2012-03-01 | 2012-10-24 | 浙江吉利汽车研究院有限公司 | Fault injection system for intelligent bus |
| CN203141798U (en) * | 2012-12-30 | 2013-08-21 | 宁波弘讯科技股份有限公司 | Fault early warning system of injection molding machine |
| CN104881618A (en) * | 2014-12-31 | 2015-09-02 | 中国科学院深圳先进技术研究院 | Method and system for quantitatively evaluating safety of safety chips |
| CN105095750A (en) * | 2014-05-15 | 2015-11-25 | 国民技术股份有限公司 | Method and device for analyzing attack on smart card chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3012237B1 (en) * | 2013-10-22 | 2017-03-03 | Commissariat Energie Atomique | ELECTRONIC CHIP COMPRISING PROTECTIVE MEANS ON ITS REAR PANEL |
-
2016
- 2016-09-14 CN CN201610826655.3A patent/CN107818271B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6484276B1 (en) * | 1999-10-25 | 2002-11-19 | Lucent Technologies Inc. | Method and apparatus for providing extensible object-oriented fault injection |
| JP2006120793A (en) * | 2004-10-20 | 2006-05-11 | Iwate Toshiba Electronics Co Ltd | Wafer marking system and failure chip marking method |
| CN102222032A (en) * | 2011-05-20 | 2011-10-19 | 哈尔滨工业大学 | Device and method for fault injection of 1394 bus |
| CN102750216A (en) * | 2012-03-01 | 2012-10-24 | 浙江吉利汽车研究院有限公司 | Fault injection system for intelligent bus |
| CN203141798U (en) * | 2012-12-30 | 2013-08-21 | 宁波弘讯科技股份有限公司 | Fault early warning system of injection molding machine |
| CN105095750A (en) * | 2014-05-15 | 2015-11-25 | 国民技术股份有限公司 | Method and device for analyzing attack on smart card chip |
| CN104881618A (en) * | 2014-12-31 | 2015-09-02 | 中国科学院深圳先进技术研究院 | Method and system for quantitatively evaluating safety of safety chips |
Non-Patent Citations (1)
| Title |
|---|
| 微处理器故障注入工具与故障敏感度分析;张英武;袁国顺;;半导体技术(07);第42-44+52页 * |
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