CN102214625A - Semiconductor wafer electrode structure and manufacturing method thereof - Google Patents
Semiconductor wafer electrode structure and manufacturing method thereof Download PDFInfo
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- CN102214625A CN102214625A CN2010101371532A CN201010137153A CN102214625A CN 102214625 A CN102214625 A CN 102214625A CN 2010101371532 A CN2010101371532 A CN 2010101371532A CN 201010137153 A CN201010137153 A CN 201010137153A CN 102214625 A CN102214625 A CN 102214625A
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Abstract
The invention discloses a semiconductor wafer electrode structure and a manufacturing method thereof. According to the semiconductor wafer electrode structure, the centre area of the surface of an electrode is even and the periphery area of the surface of the electrode is rough; the attaching viscosity needed by wire bonding and ball junction ends is provided by the centre area; and the periphery area is used for preventing oscillation energy during wire bonding from being transversely transferred to the outer side of an electrode such that the ball junction ends joined with the electrode can accord with the wire bonding technical standard. The manufacturing method comprises the steps of: defining the centre area of the electrode on the surface layer of the semiconductor wafer by the mask lithography; roughening the area of the surface layer of the semiconductor chip beyond a photomask; and evaporating the electrode metal onto the flat and rough surfaces of the surface layer of the semiconductor wafer, and therefore the electrode structure with even surface centre area and rough periphery area is formed on the surface layer of the semiconductor wafer. The semiconductor wafer electric structure disclosed by the invention has the effect of enhancing the spherical wire bonding quality.
Description
Technical field
The present invention relates to a kind of semiconductor wafer electrode structure and manufacture method, relate in particular to a kind of smooth and design that outer peripheral areas is coarse in electrode surface central area that makes.
Background technology
Light-emitting diode (LED) is that a volume is little, luminous efficacy is high, and light source component across full color, therefore its application mode is ever-changing, so derive encapsulation (Assembly) external form of many forms, product after the encapsulation generally is referred to as lamp (Lamp) or surface adhesion components (SMD), and encapsulation is mainly considered a little except external form, and the quality reliability also is the important consideration point; So, no matter be Lamp form or SMD form, routing (Wire bonding) is important step of encapsulation procedure leading portion, refer to metal material electrode (Pad) with the preparation of LED front wafer surface, use heat, pressure and ultrasonic waves homenergic that metal is adhered to electrode surface and form and conduct, electric current can be to conduct to outside lead frame (Leadframe) by metal wire; And as shown in Figure 1, metal wire 10 1 ends are typically ball-type routing (Ball bond) to the adhesive means of the electrode 21 of semiconductor wafer 20, and metal wire 10 other ends are to the adhesive means of lead frame 30 wedge type routing (Wedge bond) normally.
Inferior pressing, the ball-type routing uses wire bonder (Wire bonder) to reach usually, and the core of wire bonder is the routing head (Bonding head) of exerting pressure, thermal energy comes from the microheater (Mini heater) of clamping lead frame usually, yet pressure and these two energy of heat all come from the routing head, have decisive influence for the routing quality; But any plant equipment all has its mechanical differences and unsteadiness (Fluctuation), for the ball-type routing, be offset nothing more than routing because the problem that these difference caused is modal, that is electrode centers is departed from the center of balling end, this can cause the pressure and the ultrasonic energy meeting that come from the routing head undesired, be passed to the luminescent layer zone of adjacent electrode periphery asymmetricly, and if the hardness of some LED luminescent layer material big (as A1InGap) or did special processing (as roughening) inadequately, then above-mentioned these energy can directly cause the injury of luminescent layer material, as (the Crack that bursts apart, Cratering) damage etc., and then cause the yield loss of LED potted element, electrically unstable problem.
Summary of the invention
Technical problem underlying to be solved by this invention is, overcomes the above-mentioned defective that prior art exists, and a kind of semiconductor wafer electrode structure and manufacture method are provided, and have the effect that promotes ball-type routing quality.
Semiconductor wafer electrode structure of the present invention is:
A kind of semiconductor wafer electrode structure, it is characterized in that, make the electrode surface central area smooth and outer peripheral areas is coarse, and borrow the central area to provide the thread tacking pommel required then viscosity, and the concussion energy that is stopped routing by outer peripheral areas can meet the routing technical standard to electrode outside lateral transport so that be engaged in the balling end of electrode.
Aforesaid semiconductor wafer electrode structure, wherein to account for the ratio of entire electrode surface area be 50%～90% to the electrode surface central flat area.
Aforesaid semiconductor wafer electrode structure, wherein the electrode surface central flat area ratio that accounts for the entire electrode surface area is about 70%.
Aforesaid semiconductor wafer electrode structure, wherein semiconductor wafer is a light-emitting diode.
The manufacture method of semiconductor wafer electrode structure of the present invention is:
A kind of manufacture method of semiconductor wafer electrode structure is characterized in that, utilizes the little shadow technology of light shield to define the electrode centers zone in the semiconductor wafer top layer, and earlier the semiconductor wafer top layer is given roughening in the zone beyond the light shield; Then the electrode evaporation metal can form smooth and the electrode structure that outer peripheral areas is coarse in centre of surface zone in the semiconductor wafer top layer to the smooth and alligatoring face on semiconductor wafer top layer again.
The manufacture method of aforesaid semiconductor wafer electrode structure, wherein the semiconductor wafer top layer is the luminescent layer of light-emitting diode.
The manufacture method of semiconductor wafer electrode structure of the present invention is:
A kind of manufacture method of semiconductor wafer electrode structure is characterized in that, earlier electrode metal is finished in semiconductor wafer top layer evaporation, and is utilized the little shadow technology of light shield to define the electrode outer peripheral areas; Then again in the mode of physical shock or chemical etching, the electrode surface of outer peripheral areas is given roughening, can form smooth and the electrode structure that outer peripheral areas is coarse in centre of surface zone in the semiconductor wafer top layer.
The manufacture method of aforesaid semiconductor wafer electrode structure, wherein the semiconductor wafer top layer is the luminescent layer of light-emitting diode.
The invention has the beneficial effects as follows to have the effect that promotes ball-type routing quality.
Description of drawings
The present invention is further described below in conjunction with drawings and Examples.
Fig. 1 is in the structural representation of semiconductor wafer routing.
Fig. 2 is the structural representation that the thread tacking pommel is engaged in the tabular surface electrode.
Fig. 3 is the structural representation that the thread tacking pommel is engaged in the matsurface electrode.
Fig. 4 is a structural representation of the present invention.
Embodiment
At first, see also shown in Figure 2ly, the electrode 21a surface of existing semiconductor wafer 20 is the design of smooth formula; Other sees also shown in Figure 3, the semiconductor wafer 20 of (as the luminescent layer of light-emitting diode) is made the electrode 21b of rough surface on identical top layer, and observe the routing process that both form balling end 11 and can learn, rough surface electrode 21b more can resist the concussion of (counteracting) ultrasonic waves than flat surfaces electrode 21a, its lateral transport that may be interpreted as energy is hindered because of rough surface, supersonic concussion energy is difficult to be transmitted downwards by rough surface electrode 21b both sides, so the routing process causes wafer to produce the possibility of bursting apart and damaging, under rough surface electrode 21b, be difficult for taking place, but then just opposite at flat surfaces electrode 21a.
Moreover, but the comprehensive roughening of electrode surface design no all roses, because the then not high enough problem of viscosity is caused on coarse surface easily, this phenomenon is because thread tacking pommel 11 touches the moment of coarse electrode, the part air can be confined to the electrode centers vicinity, perhaps be difficult for being cleaned event than being easier to residual contaminants matter.
Therefore, comprehensive above-mentioned observation and routing (Wire bonding) technical standard, please consult shown in Figure 4 again, the electrode 21c surface texture that the present invention has designed a kind of " central area is smooth, outer peripheral areas is coarse ", utilize the higher then viscosity of electrode centers zone flat surfaces, guarantee to have enough engaging forces between thread tacking pommel 11 and the electrode 21c, and utilize the rough surface of electrode outer peripheral areas, stop that ultrasonic waves concussion energy is to electrode 21c outside lateral transport; Wherein, central flat area accounts for the ratio of entire electrode surface area, is can meeting routing technical standard (for example thrust magnitude) for prerequisite designs, and welding (Welding) area about common 50%～90% (preferable about 70%) is can be received.
Yet a kind of manufacture method of the present invention is to utilize the little shadow technology of light shield (as the luminescent layer of light-emitting diode) defines the electrode centers zone in the semiconductor wafer top layer, and earlier the semiconductor wafer top layer is given roughening in the zone beyond the light shield; Then the electrode evaporation metal can form smooth and the electrode structure that outer peripheral areas is coarse in centre of surface zone in the semiconductor wafer top layer to the smooth and alligatoring face on semiconductor wafer top layer again.Again, of the present invention other plants manufacture method, is earlier electrode metal to be finished in semiconductor wafer top layer evaporation, and utilizes the little shadow technology of light shield to define the electrode outer peripheral areas; Then again in the mode of physical shock or chemical etching, the electrode surface of outer peripheral areas is given roughening, can form smooth and the electrode structure that outer peripheral areas is coarse in centre of surface zone in the semiconductor wafer top layer.
Based on said structure, the present invention utilizes little shadow technology of light shield and alligatoring processing procedure, make smooth and the design that outer peripheral areas is coarse in electrode surface central area, its central area can provide the thread tacking pommel required then viscosity, outer peripheral areas then can stop the outside lateral transport of concussion energy of routing, can meet the routing technical standard so that be engaged in the balling end of electrode, have the effect that promotes ball-type routing quality.
Claims (8)
1. semiconductor wafer electrode structure, it is characterized in that, make the electrode surface central area smooth and outer peripheral areas is coarse, and borrow the central area to provide the thread tacking pommel required then viscosity, and the concussion energy that is stopped routing by outer peripheral areas can meet the routing technical standard to electrode outside lateral transport so that be engaged in the balling end of electrode.
2. semiconductor wafer electrode structure according to claim 1 is characterized in that, the ratio that described electrode surface central flat area accounts for the entire electrode surface area is 50%～90%.
3. semiconductor wafer electrode structure according to claim 2 is characterized in that, the ratio that described electrode surface central flat area accounts for the entire electrode surface area is about 70%.
4. semiconductor wafer electrode structure according to claim 3 is characterized in that, described semiconductor wafer is a light-emitting diode.
5. the manufacture method of a semiconductor wafer electrode structure is characterized in that, utilizes the little shadow technology of light shield to define the electrode centers zone in the semiconductor wafer top layer, and earlier the semiconductor wafer top layer is given roughening in the zone beyond the light shield; Then the electrode evaporation metal can form smooth and the electrode structure that outer peripheral areas is coarse in centre of surface zone in the semiconductor wafer top layer to the smooth and alligatoring face on semiconductor wafer top layer again.
6. the manufacture method of semiconductor wafer electrode structure according to claim 5 is characterized in that, described semiconductor wafer top layer is the luminescent layer of light-emitting diode.
7. the manufacture method of a semiconductor wafer electrode structure is characterized in that, earlier electrode metal is finished in semiconductor wafer top layer evaporation, and is utilized the little shadow technology of light shield to define the electrode outer peripheral areas; Then again in the mode of physical shock or chemical etching, the electrode surface of outer peripheral areas is given roughening, can form smooth and the electrode structure that outer peripheral areas is coarse in centre of surface zone in the semiconductor wafer top layer.
8. the manufacture method of semiconductor wafer electrode structure according to claim 7 is characterized in that, described semiconductor wafer top layer is the luminescent layer of light-emitting diode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010101371532A CN102214625A (en) | 2010-04-01 | 2010-04-01 | Semiconductor wafer electrode structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010101371532A CN102214625A (en) | 2010-04-01 | 2010-04-01 | Semiconductor wafer electrode structure and manufacturing method thereof |
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| CN102214625A true CN102214625A (en) | 2011-10-12 |
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| CN2010101371532A Pending CN102214625A (en) | 2010-04-01 | 2010-04-01 | Semiconductor wafer electrode structure and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103606607A (en) * | 2013-10-21 | 2014-02-26 | 溧阳市东大技术转移中心有限公司 | Electrode structure with coarsened surface |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5797686A (en) * | 1980-12-10 | 1982-06-17 | Nec Corp | Light emitting element pellet |
| CN87100973A (en) * | 1986-02-24 | 1987-09-02 | 夏普公司 | The manufacture method of semiconductor device |
| CN101326649A (en) * | 2005-12-14 | 2008-12-17 | 昭和电工株式会社 | Gallium nitride compound semiconductor light-emitting device and method for manufacturing same |
| TW200924086A (en) * | 2007-11-16 | 2009-06-01 | Fupo Electronics Corp | Roughened structure for rearranged bonding pad and its manufacturing method |
-
2010
- 2010-04-01 CN CN2010101371532A patent/CN102214625A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5797686A (en) * | 1980-12-10 | 1982-06-17 | Nec Corp | Light emitting element pellet |
| CN87100973A (en) * | 1986-02-24 | 1987-09-02 | 夏普公司 | The manufacture method of semiconductor device |
| CN101326649A (en) * | 2005-12-14 | 2008-12-17 | 昭和电工株式会社 | Gallium nitride compound semiconductor light-emitting device and method for manufacturing same |
| TW200924086A (en) * | 2007-11-16 | 2009-06-01 | Fupo Electronics Corp | Roughened structure for rearranged bonding pad and its manufacturing method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103606607A (en) * | 2013-10-21 | 2014-02-26 | 溧阳市东大技术转移中心有限公司 | Electrode structure with coarsened surface |
| CN103606607B (en) * | 2013-10-21 | 2016-04-06 | 溧阳市东大技术转移中心有限公司 | A kind of electrode structure with coarse surface |
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Application publication date: 20111012 |