CN102208961A - Low-delay R-S coder/decoder realization method applicable to CCSDS (Consultative Committee for Space Data Systems) standard - Google Patents
Low-delay R-S coder/decoder realization method applicable to CCSDS (Consultative Committee for Space Data Systems) standard Download PDFInfo
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- CN102208961A CN102208961A CN2011101269929A CN201110126992A CN102208961A CN 102208961 A CN102208961 A CN 102208961A CN 2011101269929 A CN2011101269929 A CN 2011101269929A CN 201110126992 A CN201110126992 A CN 201110126992A CN 102208961 A CN102208961 A CN 102208961A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a low-delay R-S coder/decoder realization method applicable to the CCSDS (Consultative Committee for Space Data Systems) standard. The invention aims at providing a simple and reliable method with low hardware resource consumption, which is applicable to the CCSDS standard. The low-delay R-S coder/decoder realization method is realized by the technical scheme which comprises the following steps of: processing continuous data by using multiple stages of buffer pools and a high-speed clock, and storing the continuous data to be processed in the first stage of buffer pool of an R-S coder/decoder at first; when one R-S data packet to be processed is full, reading the data to be processed according to bytes by using the high-speed clock, and deinterlacing the data under the push of the high-speed clock; then, decomposing and storing the data into multiple buffer pools according to interlacing depth in accordance with the CCSDS standard, and carrying out R-S coding/decoding in the serial sequence; whenever the data of one buffer pool is processed, storing data into next stage of buffer pool; when data in all upper stages of buffer pools are processed, interlacing the data, and storing the interlaced data into the next stage of data buffer pool; and finally, continuously reading the processed data.
Description
Technical field
The present invention relates to a kind ofly in the space flight measurement and control field, observing and controlling, number be passed under the demanding environment of data processing real-times, data are carried out the method for R-S volumes/decoding processing.It is a kind of implementation of low time delay R-S (Reed-Solomon sign indicating number) volume/decoder that remote measurement in the space flight communication and number pass the CCSDS standard of data that adapts to.CCSDS has defined two kinds of R-S volume/decoded modes to data transmission frames: R-S (255,223) or R-S (255,239), two kinds of all optional choosing friends of R-S coding are knitted degree of depth I=1,2,3,4,5,8, to a certain task phase, the selected interleave depth of same physical channel is fixed, and will do the deinterleaving of response during decoding.
Background technology
R-S volume/realization of decoding the technology that relates to the CCSDS standard in space flight measurement and control field at present, most employing can't reach the software of data in real time processing and realize, in the hardware of using is realized, to the processing delay of the R-S volume/realization of decoding that interweaves is arranged, all in the magnitude of data frame length (L)/(data rate) S.With frame length 4096bit, speed 4096bit/s is that example is calculated, and its R-S processing delay is a second-time.This time delay also reduces with data rate and frame length increases, and existing R-S volume/decoding hardware in the processing implementation that interweaves is arranged, is delayed time during as the employing serial process, on above-mentioned time delay basis, also will multiply by interleave depth.With maximum interweave (8) calculate, adopt serial process R-S volume/decoding processing delay, more than 10 seconds.
In interleaving treatment is arranged,, can on processing delay, overcome the serial process problem, but its cost is being multiplied of hardware resource as adopting parallel processing.Still with maximum interweave (8) calculate, adopting parallel processing to play hardware resource is 8 times of serial process, this realizes producing restriction to hardware equally.Therefore in measuring and control data was handled, the delay problem and the hardware resource occupation problem that how to solve R-S volume/decoding became a bottleneck.
Summary of the invention
The objective of the invention is at above-mentioned prior art exist defective, provide a kind of simple and reliable, to expend hardware resource little, adapts to the low time delay R-S volume/decoder implementation method of CCSDS standard.
The technical solution adopted for the present invention to solve the technical problems is: a kind of low time delay R-S volume/decoder implementation method that adapts to the CCSDS standard, it is characterized in that comprising the steps: handling continuous data with multi-buffer pond and high-frequency clock, in the one-level data buffering pond of R-S volume/decoder, store pending continuous data earlier; When reading a full pending R-S packet, use high-frequency clock again, pending data are read by byte, make this sense data, under high-frequency clock promotes, carry out deinterleaving and handle; According to the CCSDS standard,, press interleave depth and decompose then, deposit a plurality of data bufferings pond in, and, carry out R-S volume/decoding by serial order and handle the data of buffering with above-mentioned data; Whenever handle Buffer Pool data, deposit the next stage Buffer Pool in; After data processing in all higher level's Buffer Pools is intact, carry out data interlacing again and handle, and the data after will interweaving, exist in the one-level data buffering pond, back, again the data after handling are read continuously at last.
The present invention has following beneficial effect than prior art:
R-S volume/the decoding of the present invention based on the system of packet utilizes multi-buffer pond and high-frequency clock to handle continuous data dexterously, uses high-frequency clock to promote the mode of R-S volume/decoding.Both guarantee not expend too much hardware resource, and can significantly reduce processing delay again.Can also carry out Dynamic Selection to R-S (255,223) and two kinds of R-S volume/decoders of R-S (255,239) of CCSDS standard definition to data R-S interleave depth controllable parameters, improve application flexibility.Adapting to data rate handles from the R-S volume/decoding of 1bit/s to 300Mbit/s real time continuous data.The present invention realizes all R-S volume/decoders in FPGA, system clock 10M to 300M has simplified the application in the practical multiple field of external interface.
The technology of the present invention superior performance, realize simple, resource occupation is less, can satisfy the real-time requirement that handle data in the space flight measurement and control field.
Description of drawings
The present invention is further described below in conjunction with accompanying drawing and embodiment.
Fig. 1 is that the present invention adapts to the low time delay R-S decoder circuit schematic diagram of CCSDS standard.
Embodiment
Consult Fig. 1.Volume/the decoder of R-S shown in the figure, comprise on the same circuit, be connected on two between the level Four fast data buffer pond virtual packing module of deinterleaving/interpolation and R-S volume/decoder main control module, be connected in parallel on the R-S (255 between R-S volume/decoder main control module and the controlled module of R-S volume/decoder, 223) volume/decoding module and R-S (255,239) volume/decoding module, and by a plurality of data bufferings pond, the virtual packing module of the data interlacing of continuous data output/go.
Continuous data from demodulator, use high speed clock reading of data to the virtual packing module of deinterleaving/add, the virtual packing module of deinterleaving/add, deposit different Buffer Pools in according to interleave depth, arrive R-S volume/decoder main control module through a plurality of data bufferings pond, the output of R-S volume/decoder main control module, through R-S (255,223) volume/decoding module and R-S (255,239) volume/decoding module, the controlled module of R-S volume/decoder, deposit different Buffer Pools in according to interleave depth, again through a plurality of data bufferings pond, be delivered to data interlacing/remove virtual packing module, by a plurality of data bufferings pond output continuous data.To data R-S interleave depth controllable parameters, to two kinds of R-S volume/decoders of CCSDS standard definition R-S (255,223) and R-S (255,239) but Dynamic Selection.
In order to reduce the resource occupation amount of R-S volume/decoder hardware, can use the mode of serial process to the R-S volume/decoding that interweaves is arranged.Because R-S volume/decoding is based on the system of packet, therefore can adopt multi-stage data buffering and high-frequency clock to promote the mode of R-S volume/decoding, utilize high-frequency clock can reduce the processing delay of R-S volume/decoding greatly.Specific implementation is: utilize the pending continuous data of one-level data buffering pond storage earlier, when reading a full pending R-S packet, utilize high-frequency clock that data are read processing by byte, the deal with data clock reaches as high as 300MB/s.These data are carried out the deinterleaving processing under high-frequency clock promotes, according to the CCSDS standard data are decomposed by interleave depth to deposit eight data Buffer Pools in, and for example interleave depth is that 3 o'clock needs are with in data decomposition to the 3 data Buffer Pool.Next the data of buffering are carried out R-S volumes/decoding processing by serial order, deposit the data of handling in the next stage Buffer Pool after whenever handling Buffer Pool data.After data are all handled in all higher level's Buffer Pools, carry out data interlacing again and handle, and data are deposited after will interweaving, in afterbody data buffering pond.Data after will handling are again at last read continuously.
In said process, the clock of processing at different levels all adopts high-frequency clock to promote.Can be 4 by 100MB/S processing clock, 4096bit frame length, interleave depth.The analyzing and processing time delay: deinterleaving relates to twice packet read-write time delay: S1=2*512/10 with interweaving
8=0.01ms; 4 volume/decoding processing delay: S2=4*0.05=0.2ms of serial; Afterbody data buffering pond relates to a packet and postpones: S3=512/10
8=0.005ms, total R-S processing delay is: S=S1+S2+S3=0.215ms, the R-S processing delay of actual test is less than 0.5ms.
Appendix: CCSDS standard: CCSDS 131.0-B-1BLUE BOOK September 2003.GJB1549-1992。CCSDS?RECOMMENDATION?FOR?TM?SYNCHRONIZATION?AND?CHANNEL?CODING。
Claims (4)
1. low time delay R-S volume/decoder implementation method that adapts to the CCSDS standard, it is characterized in that comprising the steps: handling continuous data with multi-buffer pond and high-frequency clock, in the one-level data buffering pond of R-S volume/decoder, store pending continuous data earlier; When reading a full pending R-S packet, use high-frequency clock again, pending data are read by byte, and under high-frequency clock promotes, carry out deinterleaving and handle; According to the CCSDS standard,, deposit a plurality of data bufferings pond in then, carry out R-S volume/decoding by serial order and handle by the interleave depth decomposition with above-mentioned data; Whenever handle Buffer Pool data, deposit the next stage Buffer Pool in; After data processing in all higher level's Buffer Pools is intact, carry out data interlacing again and handle, and the data after interweaving are deposited in the one-level data buffering pond, back, at last the data after handling are read continuously.
2. by the described low time delay R-S volume/decoder implementation method that adapts to the CCSDS standard of claim 1, it is characterized in that, described R-S volume/decoder comprises, on the same circuit, be connected on two virtual packing module of deinterleaving/interpolation and R-S volume/decoder main control modules between the level Four fast data buffer pond, be connected in parallel on the R-S (255 between R-S volume/decoder main control module and the controlled module of R-S volume/decoder, 223) volume/decoding module and R-S (255,239) volume/decoding module, the virtual packing module of and the data interlacing by a plurality of data bufferings pond continuous data output/go.
3. by the described low time delay R-S volume/decoder implementation method that adapts to the CCSDS standard of claim 1, it is characterized in that, according to the CCSDS standard, with pending continuous data, deposit eight data Buffer Pools in by the interleave depth decomposition, in data decomposition to eight a data Buffer Pool, carry out R-S volume/decoding by serial order and handle.
4. by the described low time delay R-S volume/decoder implementation method that adapts to the CCSDS standard of claim 1, it is characterized in that, continuous data from demodulator, use high speed clock reading of data to the virtual packing module of deinterleaving/add, the virtual packing module of deinterleaving/add, deposit different Buffer Pools in according to interleave depth, arrive R-S volume/decoder main control module through a plurality of data bufferings pond, the output of R-S volume/decoder main control module, through R-S (255,223) volume/decoding module and R-S (255,239) volume/decoding module, the controlled module of R-S volume/decoder, deposit different Buffer Pools in according to interleave depth, again through a plurality of data bufferings pond, be delivered to data interlacing/remove virtual packing module, by a plurality of data bufferings pond output continuous data.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103795425A (en) * | 2014-01-27 | 2014-05-14 | 中国电子科技集团公司第十研究所 | Code rate compatible RS code decoder |
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| US20070237246A1 (en) * | 2006-04-11 | 2007-10-11 | In Gi Lim | Wireless modem, modulator, and demodulator |
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Patent Citations (5)
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| US6480976B1 (en) * | 1999-03-11 | 2002-11-12 | Globespanvirata, Inc. | System and method for resource optimized integrated forward error correction in a DMT communication system |
| CN1791089A (en) * | 2004-12-17 | 2006-06-21 | 华为技术有限公司 | Method for improving code and decode treatment efficiency |
| CN2819662Y (en) * | 2005-09-27 | 2006-09-20 | 中国电子科技集团公司第五十四研究所 | Channel cascade coding decoder |
| US20070237246A1 (en) * | 2006-04-11 | 2007-10-11 | In Gi Lim | Wireless modem, modulator, and demodulator |
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| CN103795425A (en) * | 2014-01-27 | 2014-05-14 | 中国电子科技集团公司第十研究所 | Code rate compatible RS code decoder |
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Application publication date: 20111005 |