CN105406876A - Multi-channel LDPC code reuse decoder - Google Patents
Multi-channel LDPC code reuse decoder Download PDFInfo
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- CN105406876A CN105406876A CN201510688769.1A CN201510688769A CN105406876A CN 105406876 A CN105406876 A CN 105406876A CN 201510688769 A CN201510688769 A CN 201510688769A CN 105406876 A CN105406876 A CN 105406876A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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Abstract
The invention is suitable for the error correction technology field and provides a multi-channel LDPC code reuse decoder. The multi-channel LDPC code reuse decoder comprises n deinterleavers, an LDPC decoder, n FIFOs, a gating device, a demultiplexer, a decoder state machine and a channel number FIFO, wherein the n deinterleavers are respectively connected with the gating device and the decoder state machine to deinterleave input data, transferring the deinterleaved data from an input data clock domain to a high frequency clock domain and outputting the deinterleaved data to the gating device, the LDPC decoder is respectively connected with the gating device, the decoder state machine and the demultiplexer, the demultiplexer is respectively connected with the LDPC decoder, the decoder state machine and the n FIFOs, the LDPC decoder decodes the deinterleaved data and outputs a ready signal to the decoder state machine, the decoder state machine is respectively connected with the n deinterleavers and the channel number FIFO and controls the deinterleaver corresponding to a channel number i for outputting the deinterleaved data, and the deinterleaved data is sent to the LDPC decoder through the gating device for decoding. The reuse decoder can save hardware resources.
Description
Technical field
The present invention relates to error-correcting code technique field, particularly relate to a kind of multiplexing decoder of multichannel LDPC code.
Background technology
In order to reliable transfer of data can be realized in communication system, usually forward error correction (ForwardErrorCorrection is needed, FEC), at given signal to noise ratio (SIGNAL-NOISERATIO, SNR) in transmission channel, its channel capacity C of foundation Shannon theory is limited
unit is bit/s.In order to the limit of the channel capacity C that Shannon theory proposes can be reached, people expand the research to chnnel coding, in numerous chnnel coding, especially with LDPC (LowDensityParityCheckCode, low density parity check code) the performance closely shannon limit of code, simultaneously, LDPC encoding ratio is easier to realize, LDPC decoding adopts belief propagation iterative algorithm (BeliefPropagation, BP) its decoding complex degree is also acceptable, can realize on existing level of hardware.
Traditional single channel LDPC decoding is coupled together respectively deinterleaver 11, ldpc decoder 12 and FIFO (FirstInputFirstOutput, First Input First Output) 13, as shown in Figure 1.When running into multichannel, existingly generally multiple single pass hardware can be carried out copying many parts, thus become multichannel.But so not only can consume a large amount of hardware resources, also may cause being difficult to realize in the engineering of reality.When the increase along with port number, will the appearance of the problems such as complexity is high, resource occupation is large, efficiency is low be there is, thus hinder the extensive use of LDPC.
Summary of the invention
Technical problem to be solved by this invention is the multiplexing decoder providing a kind of multichannel LDPC code, is intended to solve in prior art the problems such as hardware resource takies greatly, efficiency is low of carrying out channel transmission and occurring.
The present invention is achieved in that a kind of multiplexing decoder of multichannel LDPC code, and comprise n deinterleaver, a ldpc decoder and n FIFO, described multiplexing decoder also comprises gate, splitter, decoder state machine and channel number FIFO;
The input of a described n deinterleaver is input data, the clock signal of input data and high frequency clock signal, the clock signal of n described input data is also input to the input of corresponding described n FIFO respectively, the output of a described n deinterleaver is connected with the input of described gate, for input data are carried out deinterleaving, and the deinterleaved data obtained after deinterleaving is transformed into high frequency clock domain from the clock zone of input data, output to described gate, the output of a described n deinterleaver is also connected with the input of described decoder state machine, for the index signal that output data frame completes,
The output of described gate is connected with the input of described ldpc decoder, the output of described decoder state machine is connected with the input of described gate, described gate is controlled to carry out gating by the channel number i inputted, for the Frame with channel number i respective channel is exported to described ldpc decoder, wherein i=1,2,3 ... n;
The output of described ldpc decoder is connected with the input of described decoder state machine, the input of described splitter respectively, deinterleaved data after deinterleaving is carried out decoding by described ldpc decoder, and the decoded data obtained after decoding is exported to described splitter, export a ready signal after decoding to described decoder state machine simultaneously;
Described decoder state machine is connected with a described n deinterleaver, described gate, described channel number FIFO, described ldpc decoder, described splitter respectively, when receiving the ready signal that described ldpc decoder sends, according to stored in sequencing from described channel number FIFO, read a channel number i, and control described gate according to channel number i and carry out gating, export and start de-interleaved signal to the deinterleaver corresponding with channel number i, make corresponding deinterleaver start to export deinterleaved data to described gate; And control described splitter according to channel number i and carry out gating;
The sequencing that described channel number FIFO is used for being filled with according to the input data of a described n deinterleaver Frame stores channel number i corresponding to described deinterleaver;
Described splitter is used for according to the channel number i received by corresponding data channel gating, and is exported by the decoded data received;
A described n FIFO is connected with n output of described splitter respectively, and the decoded data exported by described splitter gating stored in FIFO, and is transformed into the clock zone of input data from high frequency clock domain, export decoded data and data enable.
Further, described multiplexing decoder also comprises phase-locked loop and crystal oscillator, the input of described phase-locked loop is connected with the output of described crystal oscillator, the output of described phase-locked loop is connected with the input of a described n deinterleaver, described gate, described ldpc decoder, described splitter, a described n FIFO respectively, for inputting described high frequency clock signal to a described n deinterleaver, described gate, described ldpc decoder, described splitter, a described n FIFO.
Further, the frequency of described high frequency clock signal is greater than the frequency summation of the clock signal of the input data of a described n deinterleaver.
The present invention compared with prior art, beneficial effect is: the multiplexing decoder of described multichannel LDPC code uses the decoded state of decoder state machine to ldpc decoder to monitor, the sequencing that channel number FIFO is used for being filled with according to the input data of a described n deinterleaver Frame stores channel number i corresponding to described deinterleaver, make when only using a ldpc decoder, allow ldpc decoder can input the situation of data according to each passage, process the Frame of different passage successively, thus realize multichannel data decoding, and saved hardware resource.
Accompanying drawing explanation
Fig. 1 is the logic diagram of the single pass ldpc decoder that prior art provides;
Fig. 2 is the logic diagram of the multiplexing decoder of the multichannel LDPC code that the embodiment of the present invention provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
As shown in Figure 2, be the present invention one preferred embodiment, a kind of multiplexing decoder of multichannel LDPC code, comprises n deinterleaver, ldpc decoder 22, a n FIFO, gate 21, splitter 23, decoder state machine 24 and channel number FIFO25.N deinterleaver is respectively deinterleaver 1, deinterleaver 2, deinterleaver 3 ... deinterleaver n, a n FIFO is respectively FIFO1, FIFO2, FIFO3 ... FIFOn.
Being input as of n deinterleaver inputs data data_in [1], data_in [2], data_in [3] ... clock signal clk [1], clk [2], the clk [3] of data_in [n], input data ... clk [n] and high frequency clock signal clk_F.Clock signal clk [1], clk [2], the clk [3] of n input data ... clk [n] is also input to the input of a corresponding n FIFO respectively, such as, clock signal clk [1] is input to FIFO1, clock signal clk [2] and is input to FIFO2 ... clock signal clk [n] is input to FIFOn.The output of n deinterleaver is connected with n input of gate 21, for data data_in [1], data_in [2], data_in [3] will be inputted ... data_in [n] carries out deinterleaving, and the deinterleaved data data_deinterleave [1], data_deinterleave [2], the data_deinterleave [3] that will obtain after deinterleaving ... data_deinterleave [n] is transformed into high frequency clock domain from the clock zone of input data, and outputs to gate 21.The output of n deinterleaver is also connected with the input of decoder state machine 24, for index signal frame_done [1], frame_done [2], frame_done [3] that output data frame completes ... frame_done [n].
The output of gate 21 is connected with the input of ldpc decoder 22, and the output of decoder state machine 24 is connected with the input of gate 21.The gate 21 channel number i that decoder state machine 24 inputs carries out gating control, for the deinterleaved data data_deinterleave [i] with channel number i respective channel is exported to ldpc decoder 22, and wherein i=1,2,3 ... n.
The output of ldpc decoder 22 is connected with the input of decoder state machine 24, the input of splitter 23 respectively, the deinterleaved data data_deinterleave [i] that gate 21 exports by ldpc decoder 22 carries out decoding, and the decoded data data_decode [i] obtained after decoding is exported to splitter 23, export a ready signal ready after decoding to decoder state machine 24 simultaneously.
Decoder state machine 24 is connected with n deinterleaver, gate 21, channel number FIFO25, ldpc decoder 22, splitter 23 respectively, is mainly used in the operating state monitoring ldpc decoder 22.When receiving the ready signal ready that ldpc decoder 22 sends, according to stored in sequencing from channel number FIFO25, read a channel number i, and carry out gating according to channel number i control gate 21, export and start de-interleaved signal start [i] to the deinterleaver i corresponding with channel number i, corresponding deinterleaver i is made to start to export deinterleaved data data_deinterleave [i] to gate 21, and carry out gating, wherein i=1,2,3 according to channel number i control splitter 23 ... n.
The sequencing that channel number FIFO25 is used for being filled with according to the input data of n deinterleaver a Frame stores channel number i corresponding to deinterleaver, is also read channel number i to decoder state machine 24 according to the sequencing of input simultaneously.Such as deinterleaver 1 has first been filled with a Frame, so send frame_done [1] to decoder state machine 24, decoder state machine 24 by channel number 1 stored in channel number FIFO25, and then deinterleaver 4 has been filled with a Frame, so send frame_done [4] to decoder state machine 24, decoder state machine 24 is by channel number 4 stored in channel number FIFO25, and channel number 4 is stored in after channel number 1.
Splitter 23 for according to the channel number i that receives by corresponding data channel gating, and the decoded data data_decode [i] received to be exported, wherein i=1,2,3 ... n.Such as, output be decoded data data_decode [5], now, splitter 23, by data channel 5 gating, makes decoded data data_decode [5] export from data channel 5.
N FIFO is connected with n output of splitter 23 respectively, the decoded data data_decode [i] exported by splitter 23 gating is stored in FIFO, and the clock zone of input data is transformed into from high frequency clock domain, export decoded data data_out [i] and data enable dataen_out [i].Namely the data that FIFOi output exports are data_out [i] and data enable dataen_out [i], data_out [i]=data_decode [i], i=1,2 ... n.Because the gating of gate 21 and the shunt of splitter 23 all carry out action according to channel number i, the data of coming in from which data channel can be exported from corresponding data channel.Such as, input data data_in [1] is come in from data channel 1, exports during output from FIFO1, and input data data_in [5] is come in from data channel 5, exports during output from FIFO5.Because the input at n FIFO all have input the clock signal clk [i] of corresponding input data data_in [i], therefore when exporting data data_out [i], do not change the clock signal clk [i] of data itself yet.
The multiplexing decoder of multichannel LDPC code also comprises phase-locked loop 26 and crystal oscillator 27, the input of phase-locked loop 26 is connected with the output of crystal oscillator 27, its output is connected with the input of n deinterleaver, gate 21, ldpc decoder 22, splitter 23, a n FIFO respectively, for inputting high frequency clock signal clk_F to n deinterleaver, gate 21, ldpc decoder 22, splitter 23, a n FIFO.The frequency of high frequency clock signal clk_F is greater than the frequency summation of the clock signal clk [i] of the input data data_in [i] of n deinterleaver, i.e. clk_F>clk [1]+clk [2]+clk [3]+... + clk [n].Thus make the processing speed of ldpc decoder 22 can tackle the decoding of n channel parallel data input, there will not be the loss of data.
The internal structure of n deinterleaver all has a deinterleaving switch, whether carries out deinterleaving to input data for selecting.A dual port RAM (randomaccessmemory is comprised in deinterleaver 11, random access memory), two complete Frames can be stored, when inputting frame data of coming in and storing complete, deinterleaver i exports index signal frame_done [i] that a Frame completes to decoder state machine 24, to show that this passage has frame data and can deliver to ldpc decoder 22 and carry out decoding.
The multiplexing decoder of described multichannel LDPC code uses the decoded state of decoder state machine 24 pairs of ldpc decoders 22 to monitor, channel number FIFO25 stores channel number i corresponding to deinterleaver for the sequencing being filled with a Frame according to the input data of n deinterleaver simultaneously, when selecting one ldpc decoder 22, by rational time-sharing multiplex, achieve the decoding of multi-channel data, decrease the hardware resource needed for multichannel decoding, improve treatment effeciency, save cost.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. a multiplexing decoder for multichannel LDPC code, comprise n deinterleaver, a ldpc decoder and n FIFO, it is characterized in that, described multiplexing decoder also comprises gate, splitter, decoder state machine and channel number FIFO;
The input of a described n deinterleaver is input data, the clock signal of input data and high frequency clock signal, the clock signal of n described input data is also input to the input of corresponding described n FIFO respectively, the output of a described n deinterleaver is connected with the input of described gate, for input data are carried out deinterleaving, and the deinterleaved data obtained after deinterleaving is transformed into high frequency clock domain from the clock zone of input data, output to described gate, the output of a described n deinterleaver is also connected with the input of described decoder state machine, for the index signal that output data frame completes,
The output of described gate is connected with the input of described ldpc decoder, the output of described decoder state machine is connected with the input of described gate, described gate is controlled to carry out gating by the channel number i inputted, for the Frame with channel number i respective channel is exported to described ldpc decoder, wherein i=1,2,3 ... n;
The output of described ldpc decoder is connected with the input of described decoder state machine, the input of described splitter respectively, deinterleaved data after deinterleaving is carried out decoding by described ldpc decoder, and the decoded data obtained after decoding is exported to described splitter, export a ready signal after decoding to described decoder state machine simultaneously;
Described decoder state machine is connected with a described n deinterleaver, described gate, described channel number FIFO, described ldpc decoder, described splitter respectively, when receiving the ready signal that described ldpc decoder sends, according to stored in sequencing from described channel number FIFO, read a channel number i, and control described gate according to channel number i and carry out gating, export and start de-interleaved signal to the deinterleaver corresponding with channel number i, make corresponding deinterleaver start to export deinterleaved data to described gate; And control described splitter according to channel number i and carry out gating;
The sequencing that described channel number FIFO is used for being filled with according to the input data of a described n deinterleaver Frame stores channel number i corresponding to described deinterleaver;
Described splitter is used for according to the channel number i received by corresponding data channel gating, and is exported by the decoded data received;
A described n FIFO is connected with n output of described splitter respectively, and the decoded data exported by described splitter gating stored in FIFO, and is transformed into the clock zone of input data from high frequency clock domain, export decoded data and data enable.
2. the multiplexing decoder of multichannel LDPC code according to claim 1, it is characterized in that, described multiplexing decoder also comprises phase-locked loop and crystal oscillator, the input of described phase-locked loop is connected with the output of described crystal oscillator, the output of described phase-locked loop is connected with the input of a described n deinterleaver, described gate, described ldpc decoder, described splitter, a described n FIFO respectively, for inputting described high frequency clock signal to a described n deinterleaver, described gate, described ldpc decoder, described splitter, a described n FIFO.
3. the multiplexing decoder of multichannel LDPC code according to claim 1 and 2, is characterized in that, the frequency of described high frequency clock signal is greater than the frequency summation of the clock signal of the input data of a described n deinterleaver.
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Cited By (3)
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| CN107957584A (en) * | 2016-10-18 | 2018-04-24 | 深圳市德赛微电子技术有限公司 | A kind of real time multi-channel ranging code generating means and method |
| CN109952729A (en) * | 2019-01-31 | 2019-06-28 | 香港应用科技研究院有限公司 | Parallel LDPC decoder |
| CN113206674A (en) * | 2021-04-11 | 2021-08-03 | 南京理工大学 | Efficient interleaver for LDPC decoder and interleaving method |
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| CN113206674A (en) * | 2021-04-11 | 2021-08-03 | 南京理工大学 | Efficient interleaver for LDPC decoder and interleaving method |
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