CN102194795B - Test structure of dielectric layer under metal layer - Google Patents
Test structure of dielectric layer under metal layer Download PDFInfo
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- CN102194795B CN102194795B CN 201010123607 CN201010123607A CN102194795B CN 102194795 B CN102194795 B CN 102194795B CN 201010123607 CN201010123607 CN 201010123607 CN 201010123607 A CN201010123607 A CN 201010123607A CN 102194795 B CN102194795 B CN 102194795B
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Abstract
The invention provides a test structure of a dielectric layer under a metal layer. The test structure comprises a substrate, a grid structure positioned above the substrate, multiple stages of metal connecting wire layers positioned above the substrate and the grid structure, interconnecting through holes and interlayer dielectric layers positioned among the multiple stages of metal connecting wires, and pressure welding spots positioned above the metal layer at the top layer, wherein the interconnecting through holes among the multiple stages of metal connecting wire layers cannot realize the electric interconnection among all metal interconnecting wire layers. In the test structure of the dielectric layer under the metal layer, the interconnecting through holes among the multiple stages of metal connecting wire layers cannot realize the electric interconnection among all the metal interconnecting wire layers, and thus the problem that a part between an active region in the test structure and the first metal layer cannot be burnt during testing when a testing voltage is applied to the pressure welding spots of the test structure and then the performance of the dielectric layer under the metal layer at the top layer is tested with a ramp voltage method is solved.
Description
Technical field
The present invention relates to the fail-safe analysis field in the semiconductor manufacturing, particularly a kind of test structure of dielectric layer under metal layer.
Background technology
In semiconductor device structure, inner layer dielectric (ILD, Inter Layer Dielectric) refers to intermetallic insulating barrier, generally by SiO
2Form Deng non-conductive material, its effect is to make mutually isolation between the different circuit structures.The character of inner layer dielectric is vital for the performance of semiconductor device, usually requires it to have good resistance and wears performance.
The performance that Voltage ramp test (Vramp methodology) can be used for testing inner layer dielectric, the main means of this method are that the inner layer dielectric two ends are applied the voltage that raises with constant step, when voltage is elevated to a certain degree, inner layer dielectric is breakdown, then according to the corresponding data that records in this process, the inner layer dielectric performance of tested person is assessed.This testing result can reflect the defective in the material usually, can be used for detecting the defective in the electric dielectric layer in the integrated circuit, processing procedure abnormal conditions (remain in metal wire between such as materials such as metal, photoresistance residues etc.), and the situation that is used for the diffusion of monitoring copper in the copper diffusion process.
When the dielectric layer under the metal level of semiconductor device is carried out performance test, because simple dielectric layer is softer, be not easy to test, therefore the test structure of usually making as depicted in figs. 1 and 2 in the prior art is tested the dielectric layer under its metal level, so that the dielectric layer under the top layer metallic layer is tested as example, also comprise the dielectric layer in the test structure of prior art under comprising top layer metallic layer and top layer metallic layer and the substrate by grid structure and multistage metal connecting line layer, the through-hole interconnection of multistage metal connecting line interlayer and the dummy structures that interlayer dielectric layer forms.The purpose that this illusory mechanism is set is to overcome the sinking that circular arc occurs when dielectric layer under the top layer metallic layer carried out chemical mechanical planarization easily even the defective of subsiding, still there is metal residual thereby cause after top layer metallic layer is carried out chemical mechanical planarization, the problem that causes test structure to lose efficacy.Please referring to Fig. 1 and Fig. 2, Fig. 1 is the cross section structure schematic diagram of the test structure of prior art; Fig. 2 is the dielectric layer under the top layer metallic layer and the perspective view of following structure thereof in the test structure of prior art.As depicted in figs. 1 and 2, the test structure of prior art comprises: have through-hole interconnection 140, the interlayer dielectric layer 150 (transparent part among the figure) of substrate 110, grid structure 120 and the multistage metal connecting line layer 130 (M1-M5 metal connecting line layer as shown in FIG. and top-level metallic connecting line layer 131) of active area, multistage metal connecting line interlayer and be positioned at pressure welding point 160 on the top layer metallic layer, 130 on described multistage metal interconnecting wires layer is realized being electrically connected by described through-hole interconnection 140.During test, apply test voltage in described pressure welding point 160, test the performance of the dielectric layer 151 under the described top layer metallic layer 131 with above-mentioned Voltage ramp test.
When adopting the test structure of prior art to test for 45nm and following semiconductor device, be easy to occur the situation that test component burns out during test.Find through research, because 45nm and following semiconductor device are compared to 65nm and above semiconductor device, its active area is very thin to the thickness between the first metal layer, after applying test voltage on the described pressure welding point, electric current conducts to the first layer metal layer by the interconnection vias in the test component, along with the gradually increase of test voltage, large voltage is easy to active area to the part between the first metal layer is burnt out.In a single day occur the situation that circuit structure is burnt first in the test, test just can not be proceeded again, even obtain wrong test result, because above-mentioned test process is not recorded to the breakdown data of inner layer dielectric.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of test structure of dielectric layer under metal layer, with the test structure that solves prior art when being used for dielectric layer under metal layer to 45nm and following semiconductor device and carrying out performance test, the problem that causes easily test component to burn out.
For solving the problems of the technologies described above, the invention provides a kind of test structure of dielectric layer under metal layer, comprise: substrate, be positioned at the grid structure on the described substrate, be positioned at the multistage metal connecting line layer on described substrate and the described grid structure, be positioned at through-hole interconnection and the interlayer dielectric layer of described multistage metal connecting line interlayer, and be positioned at the pressure welding point on the top layer metallic layer, the electrical interconnects of unrealized each the metal interconnecting wires interlayer of the through-hole interconnection of described multistage metal connecting line interlayer.
Optionally, has active area in the described substrate.
Adopt in the test structure of dielectric layer under metal layer provided by the invention, the electrical interconnects of unrealized each layer metal interconnecting wires of the through-hole interconnection interlayer of each layer metal connecting line interlayer, therefore can avoid when testing, after the pressure welding point at test structure applies test voltage, can not cause the problem that active area burns out to the part between the first metal layer in the test structure during performance of testing the dielectric layer under the described metal level with Voltage ramp test.
Description of drawings
Fig. 1 is the cross section structure schematic diagram of the test structure of prior art;
Fig. 2 is the dielectric layer under the top layer metallic layer and the perspective view of following structure thereof in the test structure of prior art;
Fig. 3 is the cross section structure schematic diagram of test structure of the present invention;
Fig. 4 is the perspective view of the dielectric layer under the top layer metallic layer and following structure thereof in the test structure of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Test structure of dielectric layer under metal layer of the present invention can utilize multiple substitute mode to realize; the below is illustrated by preferred embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention undoubtedly.
Secondly, the present invention utilizes schematic diagram to describe in detail, and when the embodiment of the invention was described in detail in detail, for convenience of explanation, schematic diagram was disobeyed the local amplification of general ratio, should be with this as limitation of the invention.
Please in conjunction with referring to Fig. 3 and Fig. 4, Fig. 3 is the cross section structure schematic diagram of test structure of the present invention; Fig. 4 is the perspective view of the dielectric layer under the top layer metallic layer and following structure thereof in the test structure of the present invention.
As shown in Figure 3 and Figure 4, test structure of the present invention comprises: the substrate 210 with active area, be positioned at grid structure 220 and the multistage metal connecting line layer 230 (described multistage metal connecting line layer 230 comprises M1-M5 metal connecting line layer and the top-level metallic connecting line layer 231 as shown in Fig. 3 and Fig. 4) that is positioned on described substrate 210 and the described grid structure 220 on the described substrate 210, the through-hole interconnection 240 that described multistage metal connecting line layer is 230 and interlayer dielectric layer 250 (transparent part among the figure) and be positioned at pressure welding point 260 on the described top layer metallic layer 231, the electrical interconnects that the through-hole interconnection 240 unrealized described multistage metal interconnecting wires layers that described multistage metal connecting line layer is 230 are 230.
Usually, in semiconductor device, multistage metal interconnecting wires interlayer is realized being electrically connected by through-hole interconnection.Namely realized the electric connection of multistage metal interconnecting wires interlayer in the test structure of dielectric layer under metal layer of prior art by through-hole interconnection.But this kind test structure is prone to the situation that active area burns out to the part between the first metal layer when test as described in the background art, and what impact was tested accurately carries out.For overcoming this defective, in the test structure of the present invention, make the electrical interconnects of 230 on through-hole interconnection 240 unrealized each layer metal interconnecting wires layers of 230 on its each layer metal connecting line layer, can not realize between each layer metal interconnecting wires layer 230 like this being electrically connected.Like this, when testing, after applying test voltage in described pressure welding point 260, when testing the performance of the dielectric layer under the described multistage layer metal interconnection line layer with Voltage ramp test, electric current can't arrive the first metal layer on the active area, the problem that then can not cause active area to burn out to the part between the first metal layer.
For 45nm and following semiconducter device testing, as long as have flimsy weakness zone in the zone except dielectric layer, all can adopt test structure of the present invention.Simultaneously, the semiconducter device testing even without the weakness zone branch problem also can use this test structure.Test structure of the present invention also can be used for electrical conformity testing (Wafer Acceptance Test, WAT) field, comes the inside of quick semiconductor test whether abnormal conditions are arranged with this.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (2)
1. test structure of dielectric layer under metal layer, comprise: substrate, be positioned at the grid structure on the described substrate, be positioned at the multistage metal connecting line layer on described substrate and the described grid structure, be positioned at through-hole interconnection and the interlayer dielectric layer of described multistage metal connecting line interlayer, and be positioned at pressure welding point on the top layer metallic layer, it is characterized in that the electrical interconnects of unrealized each the metal connecting line interlayer of the through-hole interconnection of described multistage metal connecting line interlayer.
2. test structure of dielectric layer under metal layer as claimed in claim 1 is characterized in that, has active area in the described substrate.
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| CN 201010123607 CN102194795B (en) | 2010-03-12 | 2010-03-12 | Test structure of dielectric layer under metal layer |
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| CN 201010123607 CN102194795B (en) | 2010-03-12 | 2010-03-12 | Test structure of dielectric layer under metal layer |
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| CN102194795B true CN102194795B (en) | 2013-01-30 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102386169B (en) * | 2011-10-21 | 2013-06-05 | 华中科技大学 | Electromigration test structure of silicon through hole metal interconnection wire |
| CN103630825B (en) * | 2012-08-29 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Chip test circuit and forming method thereof |
| CN103887280B (en) * | 2012-12-20 | 2016-08-03 | 武汉新芯集成电路制造有限公司 | Interlayer dielectric is carried out test structure and the method for testing of fail-safe analysis |
| CN103943606B (en) * | 2013-01-22 | 2017-05-10 | 中芯国际集成电路制造(上海)有限公司 | Detection structure and detection method for defect in semiconductor device |
| CN104752405B (en) * | 2013-12-27 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Test structure of semiconductor devices and forming method thereof |
| CN104465620B (en) * | 2014-04-22 | 2017-05-17 | 上海华力微电子有限公司 | Novel chip test structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101494216A (en) * | 2008-01-25 | 2009-07-29 | 中芯国际集成电路制造(上海)有限公司 | Structure for testing reliability analysis of integrated circuit inner layer dielectric |
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| KR100414223B1 (en) * | 2001-07-24 | 2004-01-07 | 삼성전자주식회사 | Apparatus for testing reliability of metal line in integrated circuit |
| KR100440071B1 (en) * | 2001-12-04 | 2004-07-14 | 주식회사 하이닉스반도체 | A test pattern of semiconductor device |
| KR100520509B1 (en) * | 2003-01-30 | 2005-10-11 | 동부아남반도체 주식회사 | A equipment for monitoring electrical test of dielectric layer using guardring pattern |
| KR100558064B1 (en) * | 2003-12-31 | 2006-03-07 | 동부아남반도체 주식회사 | Method of fabricating test pattern for junction leakage current |
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| CN101494216A (en) * | 2008-01-25 | 2009-07-29 | 中芯国际集成电路制造(上海)有限公司 | Structure for testing reliability analysis of integrated circuit inner layer dielectric |
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