CN104465620B - Novel chip test structure - Google Patents
Novel chip test structure Download PDFInfo
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- CN104465620B CN104465620B CN201410164090.8A CN201410164090A CN104465620B CN 104465620 B CN104465620 B CN 104465620B CN 201410164090 A CN201410164090 A CN 201410164090A CN 104465620 B CN104465620 B CN 104465620B
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- metal line
- comb
- comb metal
- active areas
- polysilicon
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Abstract
The invention discloses a wafer acceptability test method. The method includes the steps that high voltage is applied on a first comb-shaped metal line, meanwhile medium voltage is applied on a second comb-shaped metal line, and all polycrystalline silicon is kept being earthed; if the tested current of the polycrystalline silicon exceeds the specification, it is indicated that leakage occurs between contact holes and the polycrystalline silicon; if the tested current of the polycrystalline silicon does not exceed the specification, it is indicated that invalidation occurs between the metal lines or invalidation occurs in interlayer dielectric holes; By means of the wafer acceptability test method, a production line can be helped to find out the interlayer dielectric holes, the contact holes, holes among the polycrystalline silicon and other process defects in the first time so as to conduct adjustment timely; a plurality of process problems can be monitored at the same time through the wafer acceptability test method, the test structure area is greatly reduced, and the production cost including the test is reduced.
Description
Technical field
The present invention relates to a kind of test structure, more particularly to a kind of new chip testing structure.
Background technology
In the semiconductor chip fabrication process, there are various technological problemses, various chip failures can be caused；In order to
These failures are found in time, so that production line can make improvement, various wafer acceptance test structures the very first time
It is designed and tests；Such as test the metal wire pectinate texture of insulating properties between adjacent metal lines；The inter-level dielectric of semiconductor chip
In isolation manufacturing process, because of the not good hole for causing inter-level dielectric isolation silicon nitride layer corner occur of sedimentary condition,
It is also possible to cause inter-level dielectric isolation from oxygen SiClx hole occur in centre because filling capacity is not good, so as to cause follow-up two pole
Adjacent shorted diode is together after the completion of plumber's skill；Also it is exactly the electric leakage failure between diode and liner, or
Electric leakage failure between common metal wire；But at present a test structure can not simultaneously test these projects.
Chinese patent (CN103413771A) discloses a kind of work dispatching method of wafer acceptance test board, including following step
Suddenly：Work rule is sent in step 1. setting；Step 2. pair sorts in the product assortment of on-line monitoring test zone, check and calculate, by sending
Work system sends work, obtains primary product；Primary product are sent to final shipment test zone by step 3. by transmission system, secondary
Sort out sequence, quadratic search to calculate, by dispatching system is secondary work is sent.Work rule is sent in present invention setting, and product of all categories is defined respectively
Product Inline WAT regions and Final WAT regions sequence, and according to send work rule work send to WAT boards, by inspection
Calculate, arrange a collection of product to be tested every time, the test process in WAT regions is efficiently completed in time；Realize WAT boards without
The automatization of people's operation sends work to produce, and the production capacity of the WAT boards in WAT regions has been played to greatest extent.
Chinese patent (CN102339816A) discloses a kind of wafer sort bond structure and crystal round test approach.According to this
Bright wafer sort bond structure includes multiple feeler switchs, and the plurality of feeler switch is in line, and the plurality of feeler switch exists
There is uneven width in orientation.The plurality of feeler switch is divided into first group and second group, described first group of survey
Examination feeler switch arranged for interval of the key with described second group, and the width phase of described first group of feeler switch in orientation
Together, and the width of described second group of feeler switch in orientation is identical.By using the structure so that according to this
Bright wafer sort bond structure can be universally used in wafer acceptability test and wafer radio frequency testing.
The content of the invention
In view of this, the present invention proposes a kind of new chip testing structure, to solve above-mentioned inter-level dielectric isolation silicon nitride
There is the hole of corner in layer, and inter-level dielectric isolation from oxygen SiClx hole occurs in centre, shorted diode together, diode and
Electric leakage failure between liner, or the problem of the electric leakage failure between common metal wire.
To reach above-mentioned purpose, the technical scheme is that what is be achieved in that：
A kind of chip testing structure, wherein, including comb metal line, strip metal line, some parallels from each other
The active area of row, some polysilicons arranged in parallel from each other and some contact holes；
Some polysilicons are located at the upper strata of some active areas, and some active areas and some polycrystalline
Silicon projection in the horizontal plane is orthogonal；
The comb metal line is located at the top of the polysilicon, and some active areas are connected by some contact holes
It is connected to the comb metal line；
The strip metal line is located at the top of some polysilicons, and some polysilicons are by some contacts
Hole is connected to the strip metal line.
Above-mentioned new chip testing structure, wherein, the comb metal line includes the first comb metal line and the second pectination
Metal wire.
Above-mentioned new chip testing structure, wherein, some active areas include some first active areas and some second
Active area.
Above-mentioned new chip testing structure, wherein, some first active areas by some contact holes with it is described
First comb metal line connects.
Above-mentioned new chip testing structure, wherein, some second active areas by some contact holes with it is described
Second comb metal line connects.
A kind of method of wafer acceptability test, wherein, using the test as described in any one in claim 2-5
Structure, methods described includes：
Apply high voltage on the first comb metal line, while electricity in applying on the second comb metal line
Pressure, and keep whole polysilicons to be grounded；
If measuring electric current on the comb metal line exceeds specification, and the electric current of polysilicon also exceeds specification, then show
It is the presence of leakage between the contact hole and the polysilicon；
If measuring electric current on the comb metal line exceeds specification, but the electric current of polysilicon is then shown to be without departing from specification
Failure or the failure of interlayer dielectric hole between metal wire.
As a result of above-mentioned technology, the good effect of generation is the present invention：
By the use of the present invention, production line can helped to find interlayer dielectric hole, contact hole in the very first time
The defective workmanships such as the hole and polysilicon between, adjust in time；And ask because the present invention can simultaneously monitor multiple techniques
Topic, substantially reduces test structure area, reduces the production cost comprising test.
Description of the drawings
The accompanying drawing for constituting the part of the present invention is used for providing a further understanding of the present invention, the schematic reality of the present invention
Apply example and its illustrate, for explaining the present invention, not constituting inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is the structural representation of a kind of new chip testing structure of the present invention；
Fig. 2 is the structural representation gone wrong in a kind of new chip testing structure of the invention.
Specific embodiment
Below in conjunction with the accompanying drawings the invention will be further described with specific embodiment, but not as limiting to the invention.
Embodiment：
Incorporated by reference to shown in Fig. 1, a kind of chip testing structure of the present invention, if including comb metal line, strip metal line 7,
Dry bar active area arranged in parallel from each other, some polysilicons 6 and some contact holes 1 arranged in parallel from each other；
Some polysilicons 6 are located at the upper strata of some active areas, and some active areas and some polysilicons 6 are in the horizontal plane
Projection is orthogonal；
Comb metal line is located at the top of polysilicon 6, and some active areas are connected to comb metal by some contact holes 1
Line；
Strip metal line 7 is located at the top of some polysilicons 6, and some polysilicons 6 are connected to strip by some contact holes 1
Metal wire 7.
The present invention also has on the basis of the above implementation below, continuing with shown in Figure 1,
In further embodiment of the present invention, comb metal line includes the first comb metal line 4 and the second comb metal line
5。
In further embodiment of the present invention, some active areas include some first active areas 2 and some second active areas
3。
In further embodiment of the present invention, some first active areas 2 pass through the comb metal line of some contact holes 1 and first
4 connections.
In further embodiment of the present invention, some second active areas 3 pass through the comb metal line of some contact holes 1 and second
5 connections.
Present invention additionally comprises a kind of method of wafer acceptability test, using the test structure of above-mentioned middle any one,
Method includes：
Apply high voltage on the first comb metal line 4, while voltage in applying on the second comb metal line 5, and protect
Hold whole polysilicons 6 to be grounded；
If measuring electric current on the comb metal line exceeds specification, and the electric current of polysilicon also exceeds specification, then show
It is the presence of leakage between the contact hole 1 and the polysilicon 6；
If measuring electric current on the comb metal line exceeds specification, but the electric current of polysilicon is then shown to be without departing from specification
Failure or interlayer dielectric hole failure (not shown) between metal wire.
User can according to it is following explanation further insight the present invention characteristic and function,
In the semiconductor chip fabrication process, in order to find these failures in time, various wafer acceptance are tested
Structure is designed and tests.In the inter-level dielectric isolation manufacturing process of semiconductor chip, cause because of sedimentary condition is not good
There is the hole of corner in inter-level dielectric isolation silicon nitride layer, it is also possible to cause inter-level dielectric to isolate because filling capacity is not good
There is hole in centre in silicon oxide, so as to cause follow-up diode technique after the completion of adjacent shorted diode together, contact
Electric leakage failure between hole and polysilicon, the electric leakage failure and metal wire between.
The present invention is above-mentioned in order to solve the problems, such as, the test structure of the present invention is put in the test of actual wafer acceptance
Afterwards, inter-level dielectric isolation hole, the failure between diode and liner and metal wire can simultaneously be monitored.By testing the first pectination
Electric current between metal wire and the second comb metal line, monitoring inter-level dielectric isolation hole and metal wire；By testing strip gold
Category line and the electric current between the first comb metal line and the second comb metal line, can monitor between contact hole 1 and polysilicon 6
Failure relation, concrete scheme is as follows,
In test chip, on the first comb metal line 4 high-tension electricity is applied, in applying on the second comb metal line 5
Piezoelectricity, strip metal line 7 is grounded；If the electric current of polysilicon 6 exceeds specification during measurement, contact hole 1 and polysilicon 6 are shown to be
Between there is leakage, if measuring the electric current of polysilicon 6 without departing from specification, be shown to be between metal wire failure or interlayer dielectric
Matter hole fails.
A is to fail between metal wire in Fig. 2, as shown in Fig. 2 the failure between metal wire can be the first comb metal line 4
Failure between two metal lines, can be the second comb metal line 5 two metal lines between failure, or first
Failure between the metal wire of the comb metal line 5 of comb metal line 4 and second, can also be the first comb metal line 4 and strip
Failure between failure between metal wire 7, or the second comb metal line 5 and strip metal line 7, B and C is contact hole 1 and connects
Failure between contact hole 1, D is the failure between contact hole 1 and polysilicon 6.
In some alternative embodiments, high voltage (or claiming first voltage value) ratio applied on the first comb metal line 4
The middle voltage (or referred to as second voltage value) applied on second comb metal line 5 is slightly higher in pressure drop.
In sum, by the use of the present invention, production line can helped to find interlayer dielectric hole in the very first time
The defective workmanships such as the hole between hole, contact hole and polysilicon, adjust in time；And because the present invention can simultaneously monitor many
Individual technological problemses, substantially reduce test structure area, reduce the production cost comprising test.
Preferred embodiments of the present invention are the foregoing is only, embodiments of the present invention and protection model is not thereby limited
Enclose, to those skilled in the art, should can appreciate that done by all utilization description of the invention and diagramatic content
Scheme obtained by equivalent and obvious change, should be included in protection scope of the present invention.
Claims (6)
1. a kind of chip testing structure, it is characterised in that put down from each other including comb metal line, strip metal line, some
Active area, some polysilicons arranged in parallel from each other and some contact holes that row is arranged；
Some polysilicons are located at the upper strata of some active areas, and some active areas exist with some polysilicons
Projection in horizontal plane is orthogonal；
The comb metal line is located at the top of the polysilicon, and some active areas are connected to by some contact holes
The comb metal line；
The strip metal line is located at the top of some polysilicons, and some polysilicons are connected by some contact holes
It is connected to the strip metal line.
2. chip testing structure as claimed in claim 1, it is characterised in that the comb metal line includes the first comb metal
Line and the second comb metal line.
3. chip testing structure as claimed in claim 2, it is characterised in that some active areas include that some first is active
Area and some second active areas.
4. chip testing structure as claimed in claim 3, it is characterised in that some first active areas are by some described
Contact hole is connected with the first comb metal line.
5. chip testing structure as claimed in claim 4, it is characterised in that some second active areas are by some described
Contact hole is connected with the second comb metal line.
6. a kind of method of wafer sort, it is characterised in that using test structure as described in claim 5, methods described
Including：Apply high voltage on the first comb metal line, while voltage in applying on the second comb metal line, and
Keep whole polysilicon ground connection；
If measuring electric current on the comb metal line exceeds specification, and the electric current of polysilicon also exceeds specification, then be shown to be institute
State and exist between contact hole and the polysilicon leakage；
If measuring electric current on the comb metal line exceeds specification, but the electric current of polysilicon is then shown to be metal without departing from specification
Failure or the failure of interlayer dielectric hole between line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410164090.8A CN104465620B (en) | 2014-04-22 | 2014-04-22 | Novel chip test structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410164090.8A CN104465620B (en) | 2014-04-22 | 2014-04-22 | Novel chip test structure |
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| Publication Number | Publication Date |
|---|---|
| CN104465620A CN104465620A (en) | 2015-03-25 |
| CN104465620B true CN104465620B (en) | 2017-05-17 |
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| CN201410164090.8A Active CN104465620B (en) | 2014-04-22 | 2014-04-22 | Novel chip test structure |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107346751B (en) * | 2016-05-05 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Test structure, forming method thereof and test method |
| CN108807342B (en) * | 2018-06-01 | 2019-11-15 | 上海华力集成电路制造有限公司 | The wafer of capacitor permits Acceptance Tests figure between flash memory floating gate pole plate |
| US11237205B2 (en) * | 2020-05-06 | 2022-02-01 | Nanya Technology Corporation | Test array structure, wafer structure and wafer testing method |
| CN112951806B (en) * | 2021-02-23 | 2023-12-01 | 长江存储科技有限责任公司 | Semiconductor structure and method for determining step height of semiconductor structure |
| CN113410155A (en) * | 2021-08-20 | 2021-09-17 | 广州粤芯半导体技术有限公司 | Electrical property test structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531777B1 (en) * | 2000-06-22 | 2003-03-11 | Advanced Micro Devices, Inc. | Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP |
| CN101494216A (en) * | 2008-01-25 | 2009-07-29 | 中芯国际集成电路制造(上海)有限公司 | Structure for testing reliability analysis of integrated circuit inner layer dielectric |
| CN102194795A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure of dielectric layer under metal layer |
| CN203026497U (en) * | 2012-12-31 | 2013-06-26 | 中芯国际集成电路制造(北京)有限公司 | Electric leakage test structure |
-
2014
- 2014-04-22 CN CN201410164090.8A patent/CN104465620B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531777B1 (en) * | 2000-06-22 | 2003-03-11 | Advanced Micro Devices, Inc. | Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP |
| CN101494216A (en) * | 2008-01-25 | 2009-07-29 | 中芯国际集成电路制造(上海)有限公司 | Structure for testing reliability analysis of integrated circuit inner layer dielectric |
| CN102194795A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure of dielectric layer under metal layer |
| CN203026497U (en) * | 2012-12-31 | 2013-06-26 | 中芯国际集成电路制造(北京)有限公司 | Electric leakage test structure |
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