JP2010232239A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device suppressing the generation of cracks of an insulating film on a metal wiring disposed below a conductive pad in a probing test. <P>SOLUTION: This semiconductor device is provided with: a conductive pad; a first insulating film disposed on the conductive pad and having an opening region formed so that a part of the conductive pad is exposed; a second insulating film disposed below the conductive pad; and at least a single wiring layer having a wiring using copper (Cu) and disposed below the conductive pad via the second insulating film so that the maximum wiring width w (nm) of the wiring on the uppermost layer in a region superimposed with the opening region, and a covering ratio R(%) of the wiring meet the conditions in formula (1). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device. For example, the present invention relates to a structure of a wiring layer disposed below a conductive pad.

  There are roughly two types of packaging structures for LSI products. One is mounted by wire bonding (wire bonding product), and the other is mounted by bumps arranged on the chip surface (flip chip product). In a wire bonding product, a conductive pad is generally formed only at the chip end. In flip chip products, conductive pads are generally formed uniformly at desired intervals on the entire surface of the chip. A bump is formed on the conductive pad and connected to the outside.

  In particular, in a flip chip product, a conductive pad is easily formed on the entire surface of the chip. Therefore, a structure in which an effective wiring is arranged under the conductive pad is very advantageous for miniaturization of an LSI.

  However, when connecting to the conductive pad in the probing test, the insulating film under the conductive pad is likely to break down, and if an effective wiring is arranged, a short circuit failure due to the breakdown of the insulating film becomes a problem. Specifically, a vertical load applied to the conductive pad during the probing test causes the metal wiring disposed under the conductive pad to undergo plastic deformation, resulting in a large stress concentration in the insulating film on the metal wiring. Cracks occur in the insulating film. Then, short-circuit defects occur when the metal wiring protrudes from the crack portion. As a countermeasure to such a problem, a countermeasure has been taken to suppress by disposing a metal wiring under the conductive pad or by arranging a dummy wiring for reinforcement instead of arranging an effective wiring (for example, Patent Document 1). However, this structure has a problem that the chip area cannot be reduced because the effective wiring cannot be arranged under the conductive pad. Further, even when the dummy wiring is arranged without arranging the effective wiring, there is a problem that if the insulating film on the dummy wiring arranged under the conductive pad is cracked, corrosion may occur. That is, it is required to suppress the occurrence of cracks in the insulating film on the metal wiring regardless of whether the effective wiring is arranged or the dummy wiring is arranged. However, conventionally, a sufficiently effective means for such a problem has not been found.

JP 2005-236277 A

  In order to overcome such problems, an object of the present invention is to provide a semiconductor device capable of suppressing the generation of cracks in an insulating film on a metal wiring disposed under a conductive pad in a probing test.

A semiconductor device of one embodiment of the present invention includes a conductive pad, a first insulating film which is disposed on the conductive pad and has an opening region formed so as to expose a part of the conductive pad, and the conductive pad A second insulating film disposed below and a wiring using copper (Cu), disposed below the conductive pad via the second insulating film, and in a region overlapping the opening region And at least one wiring layer arranged so that the maximum wiring width w (nm) of the wiring in the uppermost layer and the coverage ratio R (%) of the wiring satisfy the following condition (1): It is characterized by.

A semiconductor device according to another aspect of the present invention includes a conductive pad, a first insulating film disposed on the conductive pad and having an opening region formed so as to expose a part of the conductive pad, and the conductive pad. A region having a second insulating film disposed below and a wiring using aluminum (Al), disposed below the conductive pad via the second insulating film, and overlapping the opening region At least one wiring layer arranged so that the maximum wiring width w (nm) of the wiring in the uppermost layer and the coverage ratio R (%) of the wiring satisfy the following condition (2): A semiconductor device.

  ADVANTAGE OF THE INVENTION According to this invention, it can suppress that a crack generate | occur | produces in the insulating film on the metal wiring arrange | positioned under a conductive pad in a probing test.

3 is a conceptual diagram illustrating an example of a cross section of the semiconductor device in Embodiment 1. FIG. 3 is a diagram showing an example of a wiring structure under an opening region in the first embodiment as viewed from above. FIG. It is a figure which shows the simulation result and experiment result in Embodiment 1. FIG. FIG. 3 is a conceptual diagram showing an example of a cross section of an LC wiring layer in the first embodiment. FIG. 3 is a conceptual diagram showing an example of a cross section of an IM wiring layer in the first embodiment. 3 is a conceptual diagram showing an example of a cross section of an SG wiring layer in the first embodiment. FIG. 4 is a conceptual diagram showing an example of a cross section of a GL wiring layer in the first embodiment. FIG. 6 is a diagram illustrating an example of a wiring shape of an uppermost layer under an opening region in the first embodiment. FIG. 6 is a diagram illustrating an example of a wiring shape of an uppermost layer under an opening region in the first embodiment. FIG. 6 is a diagram illustrating an example of a wiring shape of an uppermost layer under an opening region in the first embodiment. FIG. It is a figure which shows the simulation result and experiment result in Embodiment 2. FIG.

Embodiment 1 FIG.
In the first embodiment, a case where a wiring layer having a copper (Cu) wiring is disposed under a conductive pad will be described. The first embodiment will be described below with reference to the drawings.

  FIG. 1 is a conceptual diagram illustrating an example of a cross section of the semiconductor device according to the first embodiment. For example, when a multilayer wiring structure is formed, the wiring layers are grouped into a wiring layer group having a common minimum wiring width. In the example of FIG. 1, a local (LC) layer group is formed on the substrate 200, an intermediate (IM) layer group is formed thereon, a semi-global (SG) layer group is formed thereon, and a global (GL) layer group is formed thereon. The The LC layer group is composed of one wiring layer 100, for example. The IM layer group includes, for example, five wiring layers 111, 112, 113, 114, and 115. The SG layer group includes, for example, three wiring layers 121, 122, and 123. The GL layer group is composed of one wiring layer 131, for example. The number of laminated wiring layers in each group is not limited to this, and it may be more or less. The wiring width of the minimum wiring increases in order from the LC layer group to the GL layer group. Further, Cu wiring is formed in the wiring layer 100. In each wiring layer excluding the wiring layer 100, a Cu wiring and a Cu via plug for connecting the Cu wiring to the lower layer wiring are formed. Therefore, in the example of FIG. 1, it has a multilayer wiring structure by Cu wiring. As the substrate 200, for example, a silicon wafer having a diameter of 300 mm is used. Here, for example, a device portion below the wiring layer 100 and a tungsten (W) plug portion connected to the device portion are not shown.

  In the uppermost wiring layer 131 of the GL layer group, Cu wirings 20, 22, and 26 are formed by using a laminated film (third insulating film) of the insulating film 410 and the insulating film 420 as an interlayer insulating film. On the uppermost wiring layer 131 of the GL layer group, a laminated film (second insulating film) of an insulating film 527 and an insulating film 528 is formed. Here, the insulating film 527 serves as a diffusion prevention film. On the upper layer side of the insulating film 528, an aluminum (Al) conductive pad 30 (also referred to as an electrode pad) is connected to at least one of the effective wirings 10, 12, 14, and 16 of the wiring layer 131 of the GL layer group. Connected with. In the example of FIG. 1, the effective wirings 10, 12, 14, and 16 are formed on the substrate 200 with a multilayer wiring structure.

  A laminated protective film PF (passivation film) (first insulating film) that protects the final surface of the multilayer wiring structure is arranged so that a part of the upper surface of the conductive pad 30 is exposed and an opening region 150 is formed. Is done. Insulating films 531, 532, and 533 are formed as the laminated protective film PF.

  As described above, the Cu wirings 20, 22, and 26 of the wiring layer 131 that is the uppermost layer of the multilayer wiring layer are disposed below the conductive pad 30 with the insulating films 527 and 528 interposed therebetween. Further, the Cu wirings 20, 22, and 26 are disposed in a region overlapping the opening region 150 in the wiring layer 131.

  Here, when the Cu wirings 20, 22, and 26 of the wiring layer 131 are not formed in a structure to be described later, when a probing test is performed on such a semiconductor device, cracks and short-circuit defects are generated as in the related art. It might be. Specifically, the Cu wirings 20, 22, and 26 disposed under the conductive pad 30 may cause plastic deformation due to a vertical load applied from above to the conductive pad 30 exposed from the opening region 150. When plastic deformation occurs, a large stress concentration occurs in the insulating film 527 on the Cu wirings 20, 22, and 26, and cracks may occur in the insulating film 527. A short defect may occur due to the Cu wirings 20, 22, and 26 protruding in the crack portion. Therefore, in order to avoid such cracks and short circuits, in the first embodiment, the Cu wirings 20, 22, and 26 of the wiring layer 131 are formed in the following structure.

FIG. 2 is a diagram showing an example of the wiring structure under the opening region in the first embodiment as viewed from above. In FIG. 2, a case will be described in which wirings 40, 42, 44, and 46 using, for example, Cu are arranged in a region overlapping the opening region 150 in the wiring layer 131 that is the uppermost layer of the multilayer wiring layer. It is assumed that the wiring widths of the wirings 40, 42, 44, and 46 that overlap the opening region 150 are w ₁ , w ₂ , w ₃ , and w ₄ , respectively, and that w ₂ > w ₃ = w ₄ > w ₁ . At this time, the wirings 40 and 42 are set so that the maximum wiring width w (nm) of the Cu wiring in the uppermost layer in the region overlapping the opening region 150 and the coverage ratio R (%) of the Cu wiring satisfy the following condition (1). , 44, 46 are formed.

The example of FIG. 2, the maximum wiring width w = _{w 2.} Further, the coverage ratio R of the Cu wiring is a value obtained by dividing the area of the wirings 40, 42, 44, 46 in the region overlapping the opening region 150 (the area shown by hatching) by the area of the opening region 150.

  By forming the Cu wirings 20, 22, and 26 of the wiring layer 131 under the opening region 150 shown in FIG. 1 so as to satisfy the structure satisfying the condition (1), the insulating film 527 and the insulating film 528 accompanying it are formed. Cracks and shorts at the Cu wirings 20, 22, and 26 can be avoided. Furthermore, it is possible to avoid a crack in the wiring layer below the wiring layer 131, for example, a crack in the insulating film 410 on the Cu wiring in the wiring layer 123 and a short in the Cu wiring in the wiring layer 123.

The condition (1) is obtained as follows. The Cu wirings 20, 22, and 26 of the uppermost wiring layer 131 under the Al conductive pad 30 are arranged as a line and space pattern, and the wiring width w of the Cu wiring is 200 nm to 3200 nm (0.2 μm to 3.2 μm). Until then, the wiring coverage ratio R was changed from 10% to 80%. Table 1 shows a list of the created wiring structures.

For these structures, in order to investigate the effect of suppressing the insulating film cracking, the presence or absence of the insulating film breakage during probing was observed using an optical microscope. As for the probing load, the load was sufficient to obtain electrical characteristics in a normal semiconductor device. Here, the load was 8 gf / cm ² as a sufficient load. Further, the probing test was performed five times. Insulation breakdown was not observed in all 5 times, ○ (good), 1 to 4 insulation film breakdowns were observed in △ (insufficient), and insulation film breakdown was observed in all 5 times Was indicated by x (NG). Table 1 shows a list of experimental results.

  When the wiring width w was 200 nm, the wiring coverage R was 10 to 20% x, 30 to 40% ◯, 50% △, and 60 to 80% x. When the wiring width w was 400 nm, the wiring coverage R was 10%, x was 20 to 40%, Δ was 50%, and x was 60% to 80%. When the wiring width w is 600 nm and 800 nm, the wiring coverage ratio R is 10%, Δ is 20 to 40%, Δ is 50%, and x is 60% to 80%. When the wiring width w was 1200 nm, the wiring coverage R was 10%, Δ from 20 to 30%, Δ from 40 to 50%, and x from 60% to 80%. When the wiring width w was 1600 nm, the wiring coverage ratio R was 10 to 40% and Δ and 50 to 80%. When the wiring width w was 2000 nm or more, the wiring coverage ratio R was x.

  Next, a stress simulation reproducing the probing test was performed, and the maximum principal stress generated in the insulating film was calculated.

  FIG. 3 is a diagram showing a simulation result and an experimental result in the first embodiment. FIG. 3A shows a simulation result and an experimental result of the maximum principal stress generated in the insulating film 527 disposed on the Cu wirings 20, 22, and 26 of the uppermost wiring layer 131. FIG. 3B shows a simulation result and an experimental result of the maximum principal stress generated in the insulating film 410 arranged on the Cu wiring of the wiring layer 123 on the lowermost layer of the uppermost layer. In the simulation, a stress analysis was performed when a vertical load was applied by a probe needle to the conductive pad 30 exposed in the opening region 150, simulating probing. The probing load in the simulation is adjusted to the above-described experiment. Cu wirings 20, 22, and 26 of the wiring layer 131 that is the uppermost layer of the multilayer wiring layer are disposed below the conductive pad 30 with the insulating films 527 and 528 interposed therebetween. Needless to say, the Cu wires 20, 22, and 26 are arranged in a region overlapping the opening region 150 in the wiring layer 131.

  In FIG. 3A, the maximum principal stress decreases as the wiring width w of the uppermost layer wiring decreases and as the wiring coverage ratio R decreases. However, when the wiring width w is 400 nm or less and the wiring coverage R is in the range of 20% or less, the stress value of the insulating film 410 one layer below increases as shown in FIG. In order to reflect this result, also in the experimental results, when the wiring width w is 400 nm and the wiring coverage ratio R is 10%, an insulating film crack occurs, and the wiring width w is 200 nm and the wiring coverage ratio R is 20%. In this case, an insulating film crack occurs. When the wiring coverage ratio R is 20% or less, the rate at which the probe needle contacts the region where the uppermost wiring layer does not exist under the conductive pad 30 increases. Therefore, as shown in FIG. The stress value of the insulating film 410 on the wiring increases. As a result, cracks are likely to occur in the insulating film 410. As described above, the simulation results are supported by the experimental results.

On the other hand, the breaking strength of the insulating films 410, 420, 527, and 528 was measured using a nanoindenter. As described later, these materials include, for example, silicon nitride (SiN), silicon carbide (SiC), and silicon carbonitride (SiCN) in the insulating films 410 and 527, and silicon oxide (SiO2) in the insulating films 420 and 528, for example. ₂ ) are used respectively. In such insulating films 410, 420, 527, and 528, cracks occurred when the maximum principal stress exceeded 4 GPa in both measurement results. Therefore, from the simulation results, the boundary condition of the maximum wiring width w and the wiring coverage ratio R when the critical stress value at which no insulating film crack is observed is 4 GPa is expressed as the above condition (1). That is, by setting the maximum wiring width w and the wiring coverage ratio R of the uppermost layer Cu wiring under the conductive pad 30 so as to satisfy the condition (1), it is possible to suppress insulating film cracks during probing.

  An effective wiring is formed under the conductive pad 30 by forming the Cu wirings 20, 22, and 26 in the wiring layer 131 under the opening region 150 shown in FIG. 1 so as to satisfy the condition (1). be able to. Of course, it goes without saying that the same effect can be achieved even if the effective wiring and the dummy wiring are mixed.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described. In each wiring layer in each group, it is preferable to form a main insulating film having a common wiring width of the minimum wiring and having a relative dielectric constant k corresponding to the wiring width. For example, in the LC layer group, the IM layer group, and the SG layer group, an insulating film having a relative dielectric constant k of 3.4 or less, for example, about 2.8 is used. For the SG layer group, an insulating film having a relative dielectric constant k larger than 3.4 may be used. Hereinafter, the manufacturing method of each layer is demonstrated in order.

  FIG. 4 is a conceptual diagram showing an example of a cross section of the LC wiring layer in the first embodiment. First, an insulating film 220 using a porous low dielectric constant insulating material is formed on the substrate 200 with a thickness of, for example, 100 nm. As a material of the insulating film 220, porous silicon carbonate (SiOC) is preferably used. With the porous SiOC film, an interlayer insulating film having a relative dielectric constant k of about 2.8 can be obtained. Here, as an example, the insulating film 220 is formed using a material containing methylsiloxane as a main component. As the material of the insulating film 220, in addition to polymethylsiloxane containing methylsiloxane as a main component, for example, a film having a siloxane skeleton such as polysiloxane, hydrogen silsesquioxane, methyl silsesquioxane, or the like is used. it can. As a formation method, for example, an SOD (spin on dielectric coating) method in which a thin film is formed by spin-coating a solution and performing heat treatment can be used. For example, a film is formed by a spinner, and this substrate is baked at 80 ° C. in a nitrogen atmosphere for 1 minute on a hot plate, and finally 30 ° C. at 450 ° C. higher than the baking temperature in the nitrogen atmosphere on the hot plate. It can be formed by performing a cure for a minute. The formation method is not limited to the SOD method, and a CVD method is also suitable.

Then, a cap insulating film 222 is formed on the insulating film 220 by depositing SiOC, for example, with a thickness of 20 nm by the CVD method. As the cap insulating film 222, for example, SiO ₂ having a relative dielectric constant k of about 4.0 can be used in addition to SiOC having a relative dielectric constant k of about 3.0. By forming the cap insulating film 222, the SiOC insulating film 220 having a low mechanical strength can be protected.

  Then, a wiring trench (trench) for forming a damascene wiring is formed in the cap insulating film 222 and the insulating film 220 by a lithography process and a dry etching process.

  Then, a barrier metal film 240 is formed on the surface of the trench and cap insulating film 222 by physical vapor deposition (PVD) such as sputtering. Examples of the material of the barrier metal film 240 include tantalum (Ta), titanium (Ti), niobium (Nb), tungsten (W), ruthenium (Ru), rhodium (Rh), alloys containing them, and compounds thereof. Or it can comprise from those laminated films. As the compound, nitrides such as tantalum nitride (TaN), titanium nitride (TiN), and niobium nitride (NbN) are particularly suitable. Then, by a PVD method such as sputtering, a Cu thin film serving as a cathode electrode in the next electrolytic plating process is deposited (formed) on the inner wall of the trench and the surface of the substrate 200 where the barrier metal film 240 is formed as a seed film. Then, using this seed film as a cathode electrode, a Cu film 260 is deposited in the trench and on the surface of the substrate 200 by an electrochemical growth method such as electrolytic plating. Thereafter, annealing is performed. Annealing is performed using an electric furnace or a hot plate in a forming gas or in a nitrogen atmosphere at a temperature range of 150 ° C. to 300 ° C., about 1 hour for an electric furnace, and about 1 minute to 5 for a hot plate. Do minutes. Then, the excess Cu film 260 and the barrier metal film 240 deposited on the trench from the state after the annealing treatment are removed by CMP to form a damascene wiring, thereby forming the wiring layer 100. For example, a Cu wiring having a minimum wiring width of 65 nm can be formed. For example, the line and space minimum wiring rule can be 65 nm / 65 nm and the wiring height can be 120 nm.

Here, the main insulating film 220 of the wiring layer 100 may be an organic insulating film, a carbon-containing SiO ₂ film (SiOC), a porous silica film, a polymer film, or an amorphous carbon film (F-doped) instead of SiOC. Is preferred. As a material for the organic insulating film, for example, an organic compound having an unsaturated bond such as polyarylene or polybenzoxazole can be used. As a result, an insulating film having a relative dielectric constant k of 3.4 or less can be formed. Further, the cap insulating film 222 on the insulating film 220 may be omitted. The carbon-containing SiO ₂ film is preferably formed using a chemical vapor deposition (CVD) method instead of the SOD method. All of these materials including SiOC formed by the SOD method have a relative dielectric constant of 3.4 or less. Further, the insulating film 220 may be formed of a stacked film including one or more of these.

FIG. 5 is a conceptual diagram showing an example of a cross section of the IM wiring layer in the first embodiment.
First, an insulating film 210 that serves as both diffusion prevention and an etching stopper is deposited on the wiring layer 100 by CVD, for example, with a thickness of 30 nm. As a material of the insulating film 210, for example, it is preferable to use SiCN, SiC, SiN, or a stacked film thereof.

  Then, an insulating film 220 using a porous low dielectric constant insulating material is formed with a thickness of, for example, 180 nm on the insulating film 210 as in the case of the LC wiring layer. Here, it can be formed of the same material as the main insulating film of the LC wiring layer. For example, a porous SiOC film is formed. Thereby, an interlayer insulating film having a relative dielectric constant k of about 2.8 can be obtained. Therefore, as the material of the insulating film 220, a film having a siloxane skeleton such as polysiloxane, hydrogen silsesquioxane, methyl silsesquioxane, or the like is used in addition to polymethylsiloxane containing methylsiloxane as a main component. be able to. The formation method is the same as that of the LC wiring layer. Alternatively, it is also preferable to perform curing by electron beam (EB) irradiation, ultraviolet (UV) irradiation or heat.

Then, a cap insulating film 222 is formed on the insulating film 220 by depositing SiOC, for example, with a thickness of 30 nm by the CVD method. Here, the same SiOC film as the cap insulating film 222 of the LC wiring layer is formed. Therefore, as the cap insulating film 222, for example, SiOC having a relative dielectric constant k of about 3.0 or SiO ₂ having a relative dielectric constant k of about 4.0 can be used. By forming the cap insulating film 222, the insulating film 220 having low mechanical strength can be protected.

  Then, a wiring trench (trench) for forming a damascene wiring and a hole (via hole) thereunder are formed in the cap insulating film 222, the insulating film 220, and the insulating film 210 by a lithography process and a dry etching process. Then, a barrier metal film 240 similar to the LC wiring layer is formed in the via hole, in the trench, and on the surface of the cap insulating film 222 by a PVD method such as sputtering. Then, by sputtering or the like, a Cu thin film serving as a cathode electrode in the next electrolytic plating process is deposited (formed) on the inner wall of the via hole, the inner wall of the trench, and the surface of the substrate 200 where the barrier metal film 240 is formed. Then, using this seed film as a cathode electrode, a Cu film 260 (an example of a copper-containing film) is deposited in the via hole, in the trench, and on the surface of the substrate 200 by an electrochemical growth method such as electrolytic plating. Then, the excess Cu film 260 and the barrier metal film 240 deposited on the trench after the annealing treatment are removed by CMP to form a dual damascene wiring, thereby forming the wiring layer 111. For example, a Cu wiring having a minimum wiring width of 70 nm can be formed. For example, the line and space minimum wiring rule can be 70 nm / 70 nm and the wiring height can be 130 nm. A via plug having a via diameter of 70 nm and a height of 110 nm can be formed.

Here, the main insulating film 220 of the wiring layer 111 is an organic insulating film, a carbon-containing SiO ₂ film (SiOC), a porous silica film, a polymer film, an amorphous carbon film similar to the case of the LC wiring layer instead of SiOC. It is also preferable to use (F dope). The insulating film 220 may be formed of a laminated film including one or more of these, whereby an insulating film having a relative dielectric constant k of 3.4 or less can be formed. Further, the cap insulating film 222 on the insulating film 220 may be omitted.

  Then, the wiring layer 112 is formed on the wiring layer 111. Subsequently, a wiring layer 113 is formed on the wiring layer 112. Subsequently, a wiring layer 114 is formed on the wiring layer 113. Subsequently, the wiring layer 115 is formed on the wiring layer 114. The formation method of the wiring layers 112 to 115 is the same as that of the wiring layer 111. In this manner, a plurality (here, five layers) of wiring layers 111, 112, 113, 114, and 115 of the IM wiring layer group are laminated.

Next, the wiring layer 121 is formed on the wiring layer 115 which is the uppermost layer of the IM wiring layer group.
FIG. 6 is a conceptual diagram showing an example of a cross section of the SG wiring layer in the first embodiment. In FIG. 6, SiN is deposited on the wiring layer 115 by CVD, for example, to a thickness of 70 nm, thereby forming an insulating film 310 that serves both as diffusion prevention and an etching stopper. As a material of the insulating film 310, for example, SiCN, SiC, SiN, or a stacked film thereof is preferably used.

  Then, an insulating film 320 is formed on the insulating film 310 with a film thickness of 400 nm, for example. Here, the same material as the insulating film 220 of the IM wiring layer group can be used. For example, polymethylsiloxane is applied by the SOD method. The formation method is not limited to the SOD method, and a CVD method is also suitable. As the material of the insulating film 320, in addition to the polymethylsiloxane containing methylsiloxane as a main component, for example, a siloxane skeleton such as polysiloxane, hydrogen silsesquioxane, and methyl silsesquioxane is used as the material of the insulating film 220. The film | membrane which has can be used. The formation method is the same as that of the LC wiring layer and the IM wiring layer. Alternatively, it is also preferable to perform curing by electron beam (EB) irradiation, ultraviolet (UV) irradiation or heat.

Next, a cap insulating film 322 is formed on the insulating film 320 by depositing SiOC, for example, to a thickness of 50 nm by a CVD method. As the cap insulating film 322, for example, SiO ₂ having a relative dielectric constant k of about 4.0 can be used. By forming the cap insulating film 322, the SiOC insulating film 320 having a low mechanical strength can be protected.

  Subsequently, a wiring trench (trench) and a hole (via hole) for forming a damascene wiring in the lithography process and the dry etching process are formed in the cap insulating film 322, the insulating film 320, and the insulating film 310. A barrier metal film 340 using a barrier metal material is formed on the surfaces of the trench, via hole, and cap insulating film 322. That is, for example, a Ta film thin film is deposited to a thickness of 5 nm, for example, in a sputtering apparatus using a sputtering method, which is one of the PVD methods, to form a barrier metal film 340. As described above, the material of the barrier metal film can be composed of Ta, Ti, Nb, W, Ru, Rh, an alloy containing them, a compound thereof, or a laminated film thereof. Then, by sputtering or the like, a Cu thin film serving as a cathode electrode in the subsequent electroplating process, which is the next process, is deposited (formed) on the inner wall of the via hole, the inner wall of the trench, and the surface of the substrate 200 where the barrier metal film 340 is formed. Then, using this seed film as a cathode electrode, a Cu film 360 (an example of a copper-containing film) is deposited in the via hole, in the trench, and on the surface of the substrate 200 by an electrochemical growth method such as electrolytic plating. Then, the excess Cu film 360 and the barrier metal film 340 deposited on the trench from the state after the annealing treatment are removed by CMP to form a dual damascene wiring, thereby forming the wiring layer 121. For example, a Cu wiring having a minimum wiring width of 140 nm can be formed. For example, the line and space minimum wiring rule can be 140 nm / 140 nm and the wiring height can be 280 nm. A via plug having a via diameter of 140 nm and a height of 230 nm can be formed.

Here, the main insulating film 320 of the wiring layer 121 is an organic insulating film, a carbon-containing SiO ₂ film (SiOC), a porous silica film, or a polymer film similar to the case of the LC wiring layer or IM wiring layer instead of SiOC. It is also preferable to use an amorphous carbon film (F-doped). The insulating film 320 may be formed of a laminated film including one or more of these, and thus an insulating film having a relative dielectric constant k of 3.4 or less can be formed. In FIG. 1, although a low-k film is used, an insulating film having a relative dielectric constant of 3.4 or more may be used. Further, the cap insulating film 322 over the insulating film 320 may be omitted.

  Then, the wiring layer 122 is formed on the wiring layer 121. Subsequently, the wiring layer 123 is formed on the wiring layer 122. The formation method of the wiring layers 122 to 123 is the same as that of the wiring layer 121. In this way, a plurality (three layers in this case) of wiring layers 121, 122, and 123 of the SG wiring layer group are stacked.

Next, the wiring layer 131 is formed on the wiring layer 123 that is the uppermost layer of the SG wiring layer group.
FIG. 7 is a conceptual diagram showing an example of a cross section of the GL wiring layer in the first embodiment. First, by depositing SiC, for example, with a thickness of 100 nm on the wiring layer 123 by a CVD method, an insulating film 410 that serves both as diffusion prevention and an etching stopper is formed. As a material of the insulating film 410, for example, SiCN, SiN, or a stacked film thereof is preferably used in addition to SiC. Then, SiO ₂ is deposited to a thickness of, for example, 1950 nm on the insulating film 410 by using a CVD method to form the insulating film 420. Thereby, the main insulating film 420 of k = 4.1 for wiring and via plugs can be formed.

  Then, a barrier metal film 440 is formed in the via hole and the trench opened in the insulating film 420 using the insulating film 410 as an etching stopper. The material of the barrier metal film 440 can be composed of Ta, Ti, Nb, W, Ru, Rh, an alloy containing them, a compound thereof, or a laminated film thereof. Then, a Cu film 460 is deposited on the inner wall of the via hole and the inner wall of the trench where the barrier metal film 440 is formed. Thereafter, a dual damascene wiring is formed through annealing and CMP, thereby forming the wiring layer 131. In the wiring layer 131, for example, a Cu wiring having a minimum wiring width of 1000 nm can be formed. For example, the line and space minimum wiring rule can be 1000 nm / 1000 nm and the wiring height can be 1100 nm. In addition, a via plug having a via diameter of 600 nm and a height of 850 nm can be formed. In this way, the wiring layer 131 of the GL wiring layer group is formed.

Next, SiN is deposited to a thickness of, for example, 70 nm on the wiring layer 131 of the GL wiring layer group, and an insulating film 527 serving as a diffusion prevention film is formed. As the material for the insulating film 527, it is preferable to use SiC, SiCN, or a stacked film thereof in addition to SiN. Then, an SiO ₂ film is deposited on the insulating film 527 by using a CVD method to form an insulating film 528.

  Next, a plug layer in which the conductive pads 30 and the contact plugs of the conductive pads 30 are arranged is formed. First, a barrier metal film 34 is formed in a contact hole opened on the insulating film 528 using the insulating film 527 as an etching stopper and on the surface of the insulating film 528. The material of the barrier metal film 34 can be composed of Ta, Ti, Nb, W, Ru, Rh, alloys containing them, compounds thereof, or laminated films thereof. Then, an Al film is deposited on the inner wall of the contact hole where the barrier metal film 34 is formed and on the surface of the insulating film 528. Then, a conductive pad 30 using an Al material is formed in the lithography process and the dry etching process.

Subsequently, an insulating film 531 to be a first layer of the laminated protective film PF is deposited on the conductive pad 30 and the surface of the insulating film 528 by using a plasma CVD method. Then, an insulating film 532 serving as the second layer of the laminated protective film PF is formed on the surface of the insulating film 531 using a plasma CVD method. Then, an insulating film 533 serving as the third layer of the stacked protective film PF is formed on the insulating film 532 using a plasma CVD method. As a material for the first and third insulating films 531, 533, SiN is preferably used. In addition, as a material for the _second insulating film 532, SiO ₂ is preferably used.

  Thereafter, using an electric furnace, sintering is performed in forming gas at 370 ° C. for 60 minutes. The insulating film 531, the insulating film 532, and the insulating film 533 on the Al conductive pad 30 are removed by reactive ion etching (RIE) to form an opening region 150. Then, dicing is performed, and the semiconductor device having the structure shown in FIG. 1 is manufactured by cutting out the chip.

  FIGS. 8 to 10 are diagrams showing examples of the wiring shape of the uppermost layer under the opening region in the first embodiment. FIG. 8 shows a case where the Cu wiring of the uppermost wiring layer 131 under the opening region 150 is formed in a line and space pattern. FIG. 9 shows a case where the Cu wiring of the uppermost wiring layer 131 under the opening region 150 is formed in a wiring shape whose direction is changed in a region overlapping with the opening region 150. FIG. 10 shows a case where the Cu wiring of the uppermost wiring layer 131 under the opening region 150 is formed in a wiring shape that is connected vertically and horizontally in a region overlapping the opening region 150. In the first embodiment, any of the wiring shapes shown in FIGS. 8 to 10 may satisfy the condition (1). Any wiring shape can exhibit the same effect as long as the condition (1) is satisfied.

Embodiment 2. FIG.
In the first embodiment, the case where the wiring of the uppermost wiring layer 131 is the Cu wirings 20, 22, and 26 has been described. However, the wiring of the uppermost wiring layer is not limited to the Cu wiring. Therefore, in the second embodiment, a case where the wiring of the wiring layer 131 is Al wirings 21, 23, 27 will be described. Other configurations are the same as those in FIG.

  Here, when the Al wirings 21, 23, and 27 of the wiring layer 131 are not formed in the structure described later, when a probing test is performed on such a semiconductor device, cracks and short-circuit defects are generated as in the related art. It might be. Specifically, the Al wirings 21, 23, and 27 disposed under the conductive pad 30 can cause plastic deformation due to a vertical load applied from above to the conductive pad 30 exposed from the opening region 150. When plastic deformation occurs, a large stress concentration occurs in the insulating film 527 on the Al wirings 21, 23, 27, and cracks may occur in the insulating film 527. Then, a short circuit failure may occur due to the Al wirings 21, 23, 27 protruding in the crack portion. Therefore, in order to avoid such cracks and shorts, in the first embodiment, the Al wirings 21, 23, 27 of the wiring layer 131 are formed in the following structure.

When the wiring of the uppermost wiring layer 131 is Al wirings 21, 23, 27, the maximum wiring width w (nm) of the Al wiring in the uppermost layer in the region overlapping the opening region 150 and the coverage ratio R ( %) Are formed so as to satisfy the following condition (2).

In the example of FIG. 2, the maximum wiring width w = w ₂ as in the case of the Cu wiring. Further, the coverage ratio R of the Al wiring is a value obtained by dividing the area of the wirings 40, 42, 44, 46 in the region overlapping the opening region 150 (the area indicated by hatching) by the area of the opening region 150.

  By forming Al wirings 21, 23, and 27 in the wiring layer 131 under the opening region 150 shown in FIG. 1 so as to satisfy the structure satisfying the condition (2), the insulating film 527 and the insulating film 528 associated therewith are formed. Cracks and shorts in the Al wirings 21, 23, 27 can be avoided. Furthermore, it is possible to avoid a crack in the wiring layer below the wiring layer 131, for example, a crack in the insulating film 410 on the Cu wiring in the wiring layer 123 and a short in the Cu wiring in the wiring layer 123.

The condition (2) is obtained as follows. The Al wirings 21, 23, 27 of the uppermost wiring layer 131 below the Al conductive pad 30 are arranged as a line and space pattern, and the wiring width w of the Al wiring is 200 nm to 3200 nm (0.2 μm to 3.2 μm). Until then, the wiring coverage ratio R was changed from 10% to 80%. Table 2 shows a list of the created wiring structures.

For these structures, in order to investigate the effect of suppressing the insulating film cracking, the presence or absence of the insulating film breakage during probing was observed using an optical microscope. As for the probing load, as in the first embodiment, the probing load was performed with a sufficient load to obtain electrical characteristics in the semiconductor device. Here, the load was 8 gf / cm ² as a sufficient load. Further, the probing test was performed five times. Insulation breakdown was not observed in all 5 times, ○ (good), 1 to 4 insulation film breakdowns were observed in △ (insufficient), and insulation film breakdown was observed in all 5 times Was indicated by x (NG). Table 2 shows a list of experimental results.

  When the wiring width w was 200 nm, the wiring coverage R was 10% to 20% x, 30% ◯, 40-50% △, 60-80% x. When the wiring width w was 400 nm, the wiring coverage ratio R was 10%, X was 20-30%, B was 40% -50%, and X was 60-80%. When the wiring width w was 600 nm, the wiring coverage ratio R was 10%, Δ at 20-30%, Δ at 40-50%, and x at 60-80%. When the wiring width w was 800 nm, the wiring coverage ratio R was 10%, Δ, 20%, Δ, 30% -50%, and 60-80%. When the wiring width w was 1200 nm, the wiring coverage ratio R was 10 to 50%, and the evaluation was 60 to 80%. When the wiring width w was 1600 nm, the wiring coverage R was 10 to 40% and Δ, and 50 to 80%. When the wiring width was 2000 nm or more, all the wiring coverages were x.

  Next, a stress simulation reproducing the probing test was performed, and the maximum principal stress generated in the insulating film was calculated.

  FIG. 11 is a diagram illustrating simulation results and experimental results in the second embodiment. FIG. 11A shows simulation results and experimental results of the maximum principal stress generated in the insulating film 527 disposed on the Al wirings 21, 23, 27 of the uppermost wiring layer 131. FIG. FIG. 11B shows a simulation result and an experimental result of the maximum principal stress generated in the insulating film 410 arranged on the Cu wiring of the wiring layer 123 on the lowermost layer of the uppermost layer. In the simulation, a stress analysis was performed when a vertical load was applied by a probe needle to the conductive pad 30 exposed in the opening region 150, simulating probing. The probing load in the simulation is adjusted to the above-described experiment. Al wirings 21, 23, and 27 of the wiring layer 131 that is the uppermost layer of the multilayer wiring layer are disposed below the conductive pad 30 with the insulating films 527 and 528 interposed therebetween. Needless to say, the Al wirings 21, 23, and 27 are arranged in a region overlapping the opening region 150 in the wiring layer 131.

  In FIG. 11A, the maximum principal stress decreases as the wiring width w of the uppermost layer wiring decreases and the wiring coverage ratio R decreases. However, when the wiring width w is 500 nm or less and the wiring coverage ratio R is in the range below the center of 30 to 20%, the stress value of the lower insulating film 410 increases as shown in FIG. End up. In order to reflect this result, also in the experimental results, when the wiring width w is 400 nm and the wiring coverage ratio R is 10%, an insulating film crack occurs, and the wiring width w is 200 nm and the wiring coverage ratio R is 20%. In this case, an insulating film crack occurs. In the case of Al wiring, the rate of contact of the probe needle with a region where the uppermost layer wiring does not exist under the conductive pad 30 is increased when the wiring coverage ratio R is slightly higher than the center of the Cu wiring, which is 30 to 20%. The increase in stress of the insulating film 410, which is estimated to be caused by this, starts. Even in the case of Al wiring, the result of the simulation is supported by the experimental result.

  From the result of the simulation, the boundary condition of the maximum wiring width w and the wiring coverage R when the critical stress value at which no insulating film crack is observed is 4 GPa as in the first embodiment is expressed as the above-mentioned condition (2). It becomes. That is, by setting the maximum wiring width w and the wiring coverage R of the uppermost Al wiring under the conductive pad 30 so as to satisfy the condition (2), it is possible to suppress insulating film cracks during probing.

  An effective wiring is formed under the conductive pad 30 by forming the Al wirings 21, 23, 27 in the wiring layer 131 under the opening region 150 shown in FIG. be able to. Of course, it goes without saying that the same effect can be achieved even if the effective wiring and the dummy wiring are mixed.

  Next, a method for manufacturing a semiconductor device in the second embodiment will be described. The wiring layers 123 shown in FIG. 1 are the same as those in the first embodiment. Further, when the wiring layer 131 is formed, as shown in FIG. 7, until the barrier metal film 440 is formed in the via hole opened in the insulating film 420 and the trench using the insulating film 410 as an etching stopper. This is the same as the first embodiment. Then, an Al film is deposited by sputtering at room temperature on the inner wall of the via hole, the inner wall of the trench, and the surface of the insulating film 420 where the barrier metal film 440 is formed. Then, Al is reflow-embedded by high-temperature sputtering at 400 ° C. Thereafter, the dual damascene wiring is formed through CMP to form the wiring layer 131 of the GL wiring layer group.

  Here, even when the Al wirings 21, 23, and 27 are formed in the wiring layer 131, the wiring shapes shown in FIGS. 8 to 10 may be used as in the first embodiment.

  In the above description, as a material for the wiring layer in each of the above embodiments, in addition to Cu, a material mainly composed of Cu used in the semiconductor industry, such as a Cu—Sn alloy, a Cu—Ti alloy, and a Cu—Al alloy. The same effect can be obtained by using. Alternatively, even when Al or an Al alloy is used in addition to Cu as the material of the wiring layer other than the uppermost layer, the same effect can be exhibited.

  The embodiments have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, in each of the above-described embodiments, the multilayer wiring structure is shown, but the present invention is not limited to this. The same is true if at least one wiring layer is formed under the conductive pad 30 with an insulating film interposed therebetween. The effect of can be demonstrated. That is, in the semiconductor device in which the conductive pad 30, the insulating films 527 and 528, the wiring of the wiring layer 131, and the opening region 150 are formed, the conditions shown in (1) are used for Cu wiring, and (2) for Al wiring. It is sufficient to satisfy the conditions shown in. In addition, for example, a wire bonding product in which the conductive pad 30 is disposed only at the chip end portion and a flip chip product in which the conductive pad 30 is disposed on the entire surface of the chip, for example, Although it is sufficient if the condition 1) or (2) is satisfied, the structure is particularly effective in a flip chip product in which the conductive pads 30 provided with bumps are arranged on the entire chip surface.

  Further, the film thickness of the interlayer insulating film and the size, shape, number, and the like of the opening can be appropriately selected from those required in the semiconductor integrated circuit and various semiconductor elements.

  In addition, all semiconductor devices and methods of manufacturing a semiconductor device that include elements of the present invention and that can be appropriately modified by those skilled in the art are included in the scope of the present invention.

  Further, for the sake of simplicity of explanation, techniques usually used in the semiconductor industry, such as a photolithography process, cleaning before and after processing, are omitted, but it goes without saying that these techniques may be included.

10, 12, 14, 16 Effective wiring, 20, 22, 26 Cu wiring, 21, 23, 27 Al wiring, 30 Conductive pad, 100, 111, 112, 113, 114, 115, 121, 122, 123, 131 wiring Layer, 150 opening region, 200 substrate, 410, 420, 527, 528, 531, 532, 533 insulating film

Claims (5)

A conductive pad;
A first insulating film disposed on the conductive pad and having an opening region formed so as to expose a part of the conductive pad;
A second insulating film disposed below the conductive pad;
A wiring having copper (Cu), disposed below the conductive pad via the second insulating film, and having a maximum wiring width w (nm) of the wiring in an uppermost layer in a region overlapping the opening region; ) And the coverage ratio R (%) of the wiring, at least one wiring layer disposed so as to satisfy the following condition (1):
A semiconductor device comprising:
A conductive pad;
A first insulating film disposed on the conductive pad and having an opening region formed so as to expose a part of the conductive pad;
A second insulating film disposed below the conductive pad;
A wiring having aluminum (Al), disposed below the conductive pad via the second insulating film, and having a maximum wiring width w (nm) in the uppermost layer in a region overlapping the opening region; ) And the coverage ratio R (%) of the wiring, at least one wiring layer arranged so as to satisfy the following condition (2):
A semiconductor device comprising:
  As the material of the second insulating film, at least one of silicon nitride (SiN), silicon oxide (SiO2), silicon carbide (SiC), and silicon carbonitride (SiCN) is used. The semiconductor device according to claim 1 or 2. The wiring layer has a third insulating film,
As a material of the third insulating film, at least one of silicon nitride (SiN), silicon oxide (SiO 2), silicon carbide (SiC), and silicon carbonitride (SiCN) is used. The semiconductor device according to claim 1.   5. The semiconductor device according to claim 1, wherein an effective wiring is included in a wiring arranged in a region overlapping at least the opening region in the uppermost wiring layer.