CN102193870A

CN102193870A - Memory management and write-in method, memory controller and memory storage system

Info

Publication number: CN102193870A
Application number: CN201010129216XA
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2010-03-09
Filing date: 2010-03-09
Publication date: 2011-09-21
Anticipated expiration: 2030-03-09
Also published as: CN102193870B

Abstract

The invention discloses a memory management and write-in method, a memory controller and a memory storage system. The memory management and write-in method is used for managing a memory module. The memory module comprises a plurality of memory units and a plurality of data input/output buses corresponding to the memory units respectively. The method comprises the following steps of: configuring a plurality of logic units; partitioning each logic unit into a plurality of logic parts corresponding to the data input/output buses respectively; and mapping the logic part of each logic unit to entity blocks of the memory units respectively. The method further comprises the following steps of: establishing a mapping table corresponding to each input/output bus respectively; and writing data from a host computer system into a corresponding memory unit by using one input/output bus according to the mapping table corresponding to the input/output bus. By adopting the method, the data write-in speed can be increased effectively.

Description

Memory management and wiring method, Memory Controller and storage system

Technical field

The invention relates to a kind of memory management and wiring method, and particularly relevant for a kind of memory management that is used to manage the duplicative nonvolatile memory and wiring method and Memory Controller and the storage system of using the method.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years, make the consumer also increase rapidly the demand of medium.Because duplicative nonvolatile memory (rewritable non-volatilememory) has that data are non-volatile, power saving, volume is little and the characteristic of no mechanical structure etc., be fit to portable applications, the most suitable being used on the battery-powered product of this class Portable.Solid state hard disc is exactly a kind of with the memory storage of duplicative nonvolatile memory as medium.Because duplicative nonvolatile memory volume low capacity is big, so be widely used in the storage of individual significant data.Therefore, duplicative nonvolatile memory industry becomes a ring quite popular in the electronic industry in recent years.

Is example with the flash memory module as the memory storage of medium, the memory cell of flash memory module has a plurality of physical blocks (physical block), and each physical blocks has a plurality of physical page (physical page), must write data in order according to the order of physical page when wherein writing data in physical blocks.In addition, the physical page that has been written into could be written into after also needing be erased earlier once more.Particularly, physical blocks is the least unit of erasing, and physical page is the sequencing minimum unit of (also claiming to write).Therefore, in the management of flash memory module, physical blocks can be divided into data field and spare area.The physical blocks of data field is the data of storing in order to host system.And the physical blocks of spare area is in order to the physical blocks in the data field of rotating.Therefore, the physical blocks in the spare area is empty or spendable unit, i.e. no record data or be labeled as invalid data useless.That is to say that the physical blocks of data field and spare area is the data of coming memory storage that host system is write in the mode of rotating.For example, when the host computer system desire writes to memory storage with data, the memory management circuitry of memory storage can be identified in desires the physical blocks that is updated in the data field, and extracts physical blocks write data to replace this physical blocks of desiring to be updated from the spare area.Specifically, the memory management circuitry of memory storage can be copied to the valid data in the physical blocks of desiring to be updated at this in physical blocks of being extracted, the data of desiring to write are write in the physical blocks of being extracted, and the physical blocks of written data is associated to the data field.In addition, the physical blocks of desiring to be updated can be performed and erase running and be associated to the spare area.

Particularly, have in a plurality of memory cells and these memory cells example with data input/output bus (Data Input/Output Bus) transmission data independently at the flash memory module, the physical blocks of memory cell can be grouped into solid element and be that unit manages with the solid element.Specifically, solid element is made up of a correspondent entity block of each memory cell respectively.For example, have in the example of first memory unit and second memory unit at the flash memory module, a correspondent entity block of first memory unit and a correspondent entity block of second memory unit can be grouped into a solid element regularly.And, physical blocks being grouped into the running of above-mentioned data field and spare area and writing in the running, memory management circuitry is to be that unit carries out with the solid element, reduces the required resource of diode-capacitor storage module thus.In addition, a plurality of physical blocks that write simultaneously in data to a solid element by a plurality of data input/output bus also can promote writing speed effectively.

Along with the progress of manufacture of semiconductor, the capacity of each physical page is increasing in the physical blocks.Yet, in with the application of solid state hard disc as the Primary Hard Drive of host computer system, the size of the continuous data that host computer system write is often less than a physical page, therefore memory management circuitry need spend the long above-mentioned running of duplicating valid data of time execution when execution writes instruction, and influences the usefulness of memory storage.

In addition, the indegree of writing of physical blocks is limited.Yet, above-mentioned be in the management framework of unit with the solid element, when host computer system only write data in one of them physical blocks at a solid element, it be that unit carries out erasing of data that Memory Management Unit still needs with the solid element.Base this, the writing indegree and can increase apace because of carrying out the above-mentioned valid data that duplicate of physical blocks is so that the life-span of shortening memory storage.

Summary of the invention

The invention provides a kind of memory management and wiring method, it can shorten carries out time that writes instruction and the life-span that prolongs memory module.

The invention provides a kind of Memory Controller, it can shorten carries out time that writes instruction and the life-span that prolongs memory module.

The invention provides a kind of storage system, it can shorten carries out time that writes instruction and the life-span that prolongs memory module.

The present invention proposes a kind of memory management and wiring method, is used to manage a memory module.This memory module comprises the first memory unit, be used for first input/output bus of first memory unit, second memory unit and be used for second input/output bus of second memory unit, and wherein first memory unit and second memory unit have a plurality of physical blocks.This memory management and wiring method comprise a plurality of logical blocks of configuration, and first logic section of each logical block being divided into corresponding first input/output bus with to second logic section that should second input/output bus.This memory management and wiring method also comprise these logical unit mappings at least a portion to the physical blocks of first memory unit and second memory unit, and wherein second logic section of one of them and each logical block of the physical blocks of first logic section of each logical block mapping first memory unit is shone upon one of them of those physical blocks of second memory unit.This memory management and wiring method also comprise first mapping table of setting up corresponding first input/output bus with first mapping relations between the physical blocks of first logic section of record logical block and first memory unit, and second mapping table of setting up corresponding second input/output bus is with second mapping relations between the physical blocks of second logic section that writes down logical block and second memory unit.This memory management and wiring method also comprise receiving and write instruction and write the data of instruction with corresponding this, and wherein these data desire to be written into one of them of first logic section of logical block.This memory management comprises also that with wiring method first mapping table according to corresponding first input/output bus only uses first input/output bus so that the corresponding data that this writes instruction are write in the first memory unit.

The embodiment of the invention proposes a kind of Memory Controller, and it comprises memory interface, memory management circuitry and host interface unit.Memory interface unit is electrically connected to memory management circuitry, and in order to be electrically connected to above-mentioned memory module.Host interface is electrically connected to memory management circuitry and in order to be electrically connected to host computer system.The memory management circuitry unit is in order to carry out at least one step of above-mentioned memory management and wiring method.

The embodiment of the invention proposes a kind of storage system, and it comprises connector, above-mentioned memory module and electrically connects the Memory Controller of memory module so far.At this, this Memory Controller is in order to carry out at least one step of above-mentioned memory management and wiring method.

Based on above-mentioned, the memory management of the embodiment of the invention and wiring method can operate each physical blocks that maps to same logical block independently, can shorten thus and carry out the time of duplicating valid data, the life-span of Bing and prolongation memory module.

For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.

Description of drawings

Figure 1A is a host computer system of using memory storage apparatus shown in the first embodiment of the invention.

Figure 1B is the synoptic diagram of the computer shown in the embodiment of the invention, input/output device and memory storage apparatus.

Fig. 1 C is the synoptic diagram of host computer system shown in another embodiment of the present invention and memory storage apparatus.

Fig. 2 is the summary calcspar of the duplicative nonvolatile memory stores device shown in Figure 1A.

Fig. 3 is the summary calcspar of Memory Controller shown in the first embodiment of the invention and memory module.

Fig. 4 and Fig. 5 are the synoptic diagram of the diode-capacitor storage module shown in the first embodiment of the invention.

Fig. 6 and Fig. 7 are the embodiment of the logical block-physical blocks mapping table of the corresponding data input/output bus shown in the first embodiment of the invention.

Fig. 8～Figure 10 writes the embodiment of data to memory module shown in the first embodiment of the invention.

Figure 11 A and Figure 11 B are another embodiment of the logical block-physical blocks mapping table of the corresponding data input/output bus shown in the first embodiment of the invention.

Figure 12 is the process flow diagram of memory management shown in the first embodiment of the invention and wiring method.

Figure 13 is the summary calcspar of the memory storage apparatus shown in the second embodiment of the invention.

Figure 14 is the process flow diagram of memory management shown in the second embodiment of the invention and wiring method.

Figure 15 is the summary calcspar of the memory storage apparatus shown in the third embodiment of the invention.

Figure 16 is the process flow diagram of memory management shown in the third embodiment of the invention and wiring method.

Figure 17 is the summary calcspar of the memory storage apparatus shown in the fourth embodiment of the invention.

Figure 18 is the process flow diagram of memory management shown in the fourth embodiment of the invention and wiring method.

The main element symbol description:

1000: host computer system 1100: computer

1102: microprocessor 1104: random access memory

1106: input/output device 1108: system bus

1110: data transmission interface 1202: mouse

1204: keyboard 1206: display

1208: printer 1212: carry-on dish

1214: memory card 1216: solid state hard disc

1310: digital camera 1312:SD card

1314:MMC card 1316: memory stick

1318:CF card 1320: embedded memory storage

100,1300,1500,1700: storer 102: connector

Memory storage

104: Memory Controller 106: memory module

202: memory management circuitry 204: host interface

206: memory interface 252: memory buffer

254: electric power management circuit 256: bug check and correcting circuit

302: first memory unit 312: the second memory unit

352: 354: the first control buss of wafer activation pin

364: the second control buss of 356: the first data input/output bus

366: the second data input/output bus 402: data field

404: spare area 406: system region

408: replace district 510 (0)～510 (H): logical block

602: the first logic section-612: the second logic section-physical blocks mapping tables of physical blocks mapping table

1302: memory management circuitry 1304: Memory Controller

1352: the first wafer activation pins 1354: control bus

1356: the first data input/output bus wafer activation in 1362: the second pin

1366: the second data input/output bus 1502: memory management circuitry

1504: Memory Controller 1552: wafer activation pin

1554: 1556: the first data input/output bus of control bus

1566: the second data input/output bus 1702: memory management circuitry

1704: Memory Controller wafer activation in 1752: the first pin

1756: the first data input/output bus of 1754: the first control buss

1764: the second control buss of 1762: the second wafer activation pins

1766: the second data input/output bus

304 (0)～304 (R), 314 (0)～314 (R): physical blocks

S1201, S1203, S1205, S1207, S1209, S1211, S1213, S1215, S1217, S1219, S1221: the step of memory management and wiring method

S1401, S1403, S1405, S1407, S1409, S1411, S1413, S1415, S1417, S1419, S1421: the step of memory management and wiring method

S1601, S1603, S1605, S1607, S1609, S1611, S1613, S1615, S1617, S1619, S1621: the step of memory management and wiring method

S1801, S1803, S1805, S1807, S1809, S1811, S1813, S1815, S1817, S1819, S1821: the step of memory management and wiring method

Embodiment

Generally speaking, memory storage apparatus (also claiming storage system) comprises memory module and controller (also claiming control circuit).Usually memory storage apparatus can use with host computer system, so that host computer system can write to data memory storage apparatus or reading of data from memory storage apparatus.In addition, memory storage apparatus also being arranged is to comprise in-line memory and can be executed on the host computer system with substantially as the software of the controller of this in-line memory.

First embodiment

Please refer to Figure 1A, host computer system 1000 generally comprises computer 1100 and I/O (input/output; Hereinafter to be referred as: I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (random access memory; Hereinafter to be referred as: RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 as Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.

In embodiments of the present invention, memory storage apparatus 100 is to electrically connect by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memory storage apparatus 100 or reading of data from memory storage apparatus 100 by microprocessor 1102, random access memory 1104 with the processing of input/output device 1106.For example, memory storage apparatus 100 can be carry-on dish 1212, memory card 1214 or solid state hard disc (the Solid StateDrive shown in Figure 1B; Hereinafter to be referred as: SSD) 1216.

Generally speaking, host computer system 1000 can be substantially for storing any system of data.Though but in the present embodiment, host computer system 1000 is to explain with computer system, still, host computer system 1000 can be systems such as digital camera, video camera, communicator, audio player or video player in another embodiment of the present invention.For example, in host computer system is digital camera (video camera) 1310 o'clock, and memory storage apparatus then is its employed SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded memory storage 1320 (shown in Fig. 1 C).Embedded memory storage 1320 comprises built-in multimedia card (EmbeddedMMC; Hereinafter to be referred as: eMMC).What deserves to be mentioned is that the built-in multimedia card is directly to be electrically connected on the substrate of host computer system.

Please refer to Fig. 2, memory storage apparatus 100 comprises connector 102, Memory Controller 104 and memory module 106.

In the present embodiment, connector 102 is advanced annex (the Serial AdvancedTechnology Attachment of sequence; Hereinafter to be referred as: SATA) connector.But, it must be appreciated that the invention is not restricted to this, connector 102 can also be universal serial bus (Universal SerialBus; Hereinafter to be referred as: USB) connector, Institute of Electrical and Electric Engineers (Institute ofElectrical and Electronic Engineers; Hereinafter to be referred as: IEEE) 1394 connectors, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express; Hereinafter to be referred as: PCI Express) connector, safe digital (Secure Digital; Hereinafter to be referred as: SD) interface connector, memory stick (Memory Stick; Hereinafter to be referred as: MS) interface connector, multimedia storage card (Multi Media Card; Hereinafter to be referred as: MMC) interface connector, compact flash (CompactFlash; Hereinafter to be referred as: CF) interface connector, integrated driving electrical interface (Integrated DeviceElectronics; Hereinafter to be referred as: IDE) connector or other connectors that is fit to.

A plurality of logic locks or steering order that Memory Controller 104 is done with hardware pattern or firmware pattern in fact in order to execution, and in memory module 106, carry out the runnings such as writing, read and erase of data according to the instruction of host computer system 1000.Particularly, Memory Controller 104 is in order to carry out data access mechanism and the memory management mechanism according to present embodiment.

Memory module 106 is to be electrically connected to Memory Controller 104, and the data that write in order to host system 1000.At this, memory module 106 is the duplicative nonvolatile memory.For example, memory module 106 is a multilayer memory cell (Multi Level Cell; Hereinafter to be referred as: MLC) NAND flash memory module.But, the invention is not restricted to this, memory module 106 is individual layer memory cell (Single Level Cell also; Hereinafter to be referred as: SLC) NAND flash memory module, other flash memory modules or other have the memory module of identical characteristics.

Please refer to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.

Memory management circuitry 202 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 202 has a plurality of steering orders, and when memory storage apparatus 100 runnings, these steering orders can be performed with the data access mechanism according to present embodiment comes diode-capacitor storage module 106 with memory management mechanism.These data access mechanism will elaborate in following conjunction with figs. with memory management mechanism.

In the present embodiment, the steering order of memory management circuitry 202 is to do in fact with a firmware pattern.For example, memory management circuitry 202 has a microprocessor unit (not shown) and a ROM (read-only memory) (not shown), and these steering orders are by imprinting so far in the ROM (read-only memory).When memory storage apparatus 100 runnings, these steering orders can be carried out to finish data access mechanism and the memory management mechanism according to the embodiment of the invention by microprocessor unit.

In another embodiment of the present invention, the steering order of memory management circuitry 202 can also the procedure code pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the memory module) of memory module 106.In addition, memory management circuitry 202 has a microprocessor unit (not shown), a ROM (read-only memory) (not shown) and a random access memory (not shown).Particularly, this ROM (read-only memory) has one and drives the sign indicating number section, and when Memory Controller 104 is enabled, microprocessor unit can be carried out this driving yard steering order that section will be stored in the memory module 106 earlier and be loaded in the random access memory of memory management circuitry 202, reruns these steering orders afterwards to carry out the data access mechanism and the memory management mechanism of the embodiment of the invention.In addition, in another embodiment of the present invention, the steering order of memory management circuitry 202 can also a hardware pattern be done in fact.

Host interface 204 is instruction and the data that are electrically connected to memory management circuitry 202 and transmitted in order to reception and identification host computer system 1000.That is to say that instruction that host computer system 1000 is transmitted and data can be sent to memory management circuitry 202 by host interface 204.In the present embodiment, host interface 204 is that corresponding connector 102 is the SATA interface.But, it must be appreciated to the invention is not restricted to this that host interface 204 can also be PATA interface, USB interface, IEEE 1394 interfaces, PCI Express interface, SD interface, MS interface, MMC interface, CF interface, ide interface or other data transmission interfaces that is fit to.

Memory interface 206 is to be electrically connected to memory management circuitry 202 and in order to access memory module 106.That is to say that the data of desiring to write to memory module 106 can be converted to 106 receptible forms of memory module via memory interface 206.

In an embodiment of the present invention, Memory Controller 104 also comprises memory buffer 252.Memory buffer 252 is to be electrically connected to memory management circuitry 202 and in order to the temporary data that come from the data and instruction of host computer system 1000 or come from memory module 106.

In an embodiment of the present invention, Memory Controller 104 also comprises electric power management circuit 254.Electric power management circuit 254 is to be electrically connected to memory management circuitry 202 and in order to the power supply of control store memory storage 100.

In an embodiment of the present invention, Memory Controller 104 also comprises bug check and correcting circuit 256.Bug check and correcting circuit 256 are to be electrically connected to memory management circuitry 202 and in order to carry out a bug check and correction program to guarantee the correctness of data.Specifically, write when instruction when memory management circuitry 202 receives from host computer system 1000, bug check can write the corresponding bug check and correcting code (the Error Checking and Correcting Code of data generation of instruction for corresponding this with correcting circuit 256; Hereinafter to be referred as: ECC Code), and memory management circuitry 202 can write to the corresponding data that this writes instruction in the memory module 106 with corresponding error-correcting code.Afterwards, when memory management circuitry 202 can read the bug check and the correcting code of this data correspondence during reading of data simultaneously from memory module 106, and bug check and correcting circuit 256 can be according to this bug check and correcting code the data execution error correction program to being read.

Memory module 106 comprises first memory unit 302 and second memory unit 312.Specifically, first memory unit 302 is to be electrically connected to memory interface 206 via wafer activation pin (Chip EnablePin) 352, first control bus (Control Bus) the 354 and first data input/output bus (DataInput/Output Bus) 356.In addition, second memory unit 312 is to be electrically connected to memory interface 206 via wafer activation pin 352, second control bus 364 and the second data input/output bus 366.In the present embodiment, control bus can comprise RE (read enable) pin, WE (write enable) pin, CLE (command latchenable) pin, ALE (address latch enable) pin, WP (write protect) pin and R/B (ready/busy output) pin position.In addition, it must be appreciated that in the present embodiment, memory module 106 comprises 2 memory cells, but the invention is not restricted to this.In another embodiment of the present invention, the number of the memory cell of memory module 106 can be any proper number.Wherein, what deserves to be explained is that memory cell can be a memory chips in an embodiment of the present invention, and each memory chips can have the naked crystalline substance of at least one storer.

First memory unit 302 has a plurality of physical blocks respectively with second memory unit 312.Each physical blocks has a plurality of pages respectively, and wherein the page corresponding to same physical blocks can independently write and erase simultaneously.In more detail, physical blocks is the least unit of erasing.That is each physical blocks contains the memory cell of being erased in the lump of minimal amount.Each physical blocks has several physical page, and physical page is the minimum unit of sequencing.In other words, physical page is the minimum unit that writes data or reading of data.Each physical page generally includes user data field and redundant area.The user data field is in order to storage user's data, and redundant area is in order to the data (for example, bug check and correcting code) of storage system.

It must be appreciated that when this described the running of physical blocks of memory module 106, coming the application entity block with speech such as " extraction ", " exchange ", " grouping ", " rotating " was in logic notion.That is to say that the physical location of the physical blocks of memory module 106 is not changed, but in logic the physical blocks of memory module 106 is operated.

Please refer to Fig. 4, memory management circuitry 202 can logically be grouped into the physical blocks 304 (0)～304 (R) of first memory unit 302 and the physical blocks 314 (0)～314 (R) of second memory unit 312 data field 402, spare area 404, system region 406 and replace district 408.

Data field 402 is the data that come from host computer system 1000 in order to storage with the physical blocks of spare area 404.Specifically, data field 402 is the physical blocks of having stored data, and the physical blocks of spare area 404 is the physical blocks in order to replacement data district 402.Therefore, the physical blocks of spare area 404 is empty or spendable physical blocks, i.e. no record data or be labeled as invalid data useless.That is to say that the physical blocks in the spare area has been performed the running of erasing, perhaps the physical blocks in the spare area is extracted the physical blocks that is used to be extracted before storing data and can be performed the running of erasing.Therefore, the physical blocks of the physical blocks of spare area for being used.What deserves to be mentioned is that in the present embodiment, memory management circuitry 202 is to come the management entity block according to the data input/output bus.Therefore, the physical blocks that belongs to first memory unit 302 in spare area 404 is only belong to the physical blocks of first memory unit 302 in order to replace in data field 402, and the physical blocks that belongs to second memory unit 312 in spare area 404 is only in order to replace the physical blocks that belongs to second memory unit 312 in data field 402.In another embodiment, the physical blocks in spare area 404 can be shared for first memory unit 302 and second memory unit 312 arbitrarily.

The physical blocks that belongs to system region 406 in logic is in order to the register system data, and wherein this system data comprises about the manufacturer of memory cell and model, the physical blocks number of memory cell, physical page number of each physical blocks etc.

Belonging to the physical blocks that replaces in the district 408 in logic is to substitute physical blocks.For example, memory module 106 or memory cell can be reserved 4% physical blocks and use as changing when dispatching from the factory.That is to say that when data field 402, spare area 404 were damaged with the physical blocks in the system region 406, the physical blocks of reserving in replacing district 408 was in order to replacing damaged physical blocks (that is bad physical blocks (bad block)).Therefore, if replace when still having normal physical blocks in the district 408 and the physical blocks damage taking place, memory management circuitry 202 can be extracted the physical blocks that normal physical blocks is changed damage from replace district 408.If when no normal physical blocks and generation physical blocks were damaged in the replacement district 408, then memory management circuitry 202 can be declared as write protection (write protect) state with memory storage apparatus 100, and can't write data again.

Particularly, the quantity of the physical blocks in data field 402, spare area 404, system region 406 and replacement district 408 can be different according to different storer specifications.In addition, it must be appreciated that in the running of memory storage apparatus 100, the grouping relation that physical blocks is associated to data field 402, spare area 404, system region 406 and replacement district 408 can dynamically change.For example, when the physical blocks in the spare area 404 is damaged and when being substituted district's physical blocks of 408 and replacing, the physical blocks that then replaces district 408 originally can be associated to spare area 404.

Please refer to Fig. 5, as mentioned above, data field 402 is the data of coming host system 1000 to be write in the mode of rotating with the physical blocks of spare area 404.In the present embodiment, memory management circuitry 202 configuration logic access addresses are beneficial to carry out data access in the physical blocks of storing data in the above-mentioned mode of rotating for host computer system 1000.Particularly, memory management circuitry 202 can be grouped into logical block 510 (0)～510 (H) with the logical bit access location that is provided, and each logical block is divided into first logic section of the corresponding first data input/output bus 356 and second logic section of the corresponding second data input/output bus 366.That is to say that the logical address of logical block can be according to the series arrangement of input/output bus.For example, formed (promptly by 8 logic access addresses in each logical block, logical block 510 (0) is made up of 0～7 of logic access address, logical block 510 (1) is made up of 8～15 of logical addresses, and in the example by that analogy), first logic section of the corresponding first data input/output bus 356 is logic access address 0～3 in logical block 510 (0), second logic section of the corresponding second data input/output bus 366 is for being logic access address 4～7 in logical block 510 (0), first logic section of the corresponding first data input/output bus 356 is logic access address 8～11 in logical block 510 (1), second logic section of the corresponding second data input/output bus 366 is logic access address 12～15 in logical block 510 (1), and by that analogy.

In addition, memory management circuitry 202 can map to the physical blocks that belongs to first memory unit 302 in the data field 402 with first logic section of logical block, and second logic section of logical block is mapped to the physical blocks that belongs to second memory unit 312 in the data field 402.For example, when memory storage apparatus 100 was initialised (for example, format), first logic section of logical block 510 (0)～510 (H) and second logic section can be mapped to the physical blocks of data field 402 respectively.That is to say that logical block can be shone upon a physical blocks of first memory unit 302 and a physical blocks of second memory unit.At this, memory management circuitry 202 can be set up 602 (as shown in Figure 6) of first logic section-physical blocks mapping table (logical part-physical block mapping table) for the first data input/output bus 356, and be that the second data input/output bus 366 is set up second logic section-physical blocks mapping table 612 (as shown in Figure 7), with the mapping relations between record logical block and the physical blocks.At this, first logic section-physical blocks mapping table also is called first mapping table, and second logic section-physical blocks mapping table also is called second mapping table.

Please be simultaneously with reference to Fig. 8～Figure 10, for example, if under Fig. 6 and mapping status shown in Figure 7, write instruction and when desiring to write data to the logic access address of first logic section that belongs to logical block 510 (0) when Memory Controller 104 receives from host computer system 1000, memory management circuitry 202 can be to map to physical blocks 304 (0) and extract physical blocks 304 (D+1) the physical blocks physical blocks 304 (0) of rotating as an alternative that belongs to first memory unit 302 from spare area 404 according to first logic section of first logic section-physical blocks mapping table 602 recognition logic unit 510 (0) at present.But, when memory management circuitry 202 write to physical blocks 304 (D+1) with new data, memory management circuitry 202 can not moved all valid data in the physical blocks 304 (0) at once to physical blocks 304 (D+1) and the physical blocks 304 (0) of erasing.Specifically, memory management circuitry 202 can write physical page valid data before (promptly with desiring in the physical blocks 304 (0), the 0th physical page and the 1st physical page) be copied to physical blocks 304 (D+1) (as shown in Figure 8), and new data is write to the 2nd physical page and the 3rd physical page (as shown in Figure 9) of physical blocks 304 (D+1).At this moment, memory management circuitry 202 is promptly finished the running that writes.Because the valid data in the physical blocks 304 (0) might be in next operation (for example, write instruction) in become invalidly, therefore at once all valid data in the physical blocks 304 (0) are moved to physical blocks 304 (D+1) and may be caused meaningless moving.In addition, data must write to the physical page in the physical blocks in order, so memory management circuitry 202 only can be moved the valid data of desiring to write before the physical page earlier.

In the present embodiment, temporarily keep these mother and sons' transient state relations (promptly, physical blocks 304 (0) and physical blocks 304 (D+1)) running be called unlatching (open) mother and child blocks, and former physical blocks is called female physical blocks and replaces physical blocks and be called the fructification block.

Afterwards, in the time the content of physical blocks 304 (0) and physical blocks 304 (D+1) really need being merged, memory management circuitry 202 just can be put in order the physical blocks 304 (0) and the data of physical blocks 304 (D+1) and to a physical blocks, be promoted the service efficiency of physical blocks thus.At this, the running that merges mother and child blocks is called closes (close) mother and child blocks.For example, as shown in figure 10, when closing mother and child blocks, memory management circuitry 202 can be with remaining valid data in the physical blocks 304 (0) (promptly, the 4th physical page～K physical page) is copied to replacement physical blocks 304 (D+1), but after physical blocks 304 (0) erased and be associated to spare area 404, simultaneously, (D+1) is associated to data field 402 with physical blocks 304.That is to say that memory management circuitry 202 can remap logical block 510 (0) to physical blocks 304 (D+1) (shown in Figure 11 A) in first logic section-physical blocks mapping table 602.In addition, in the present embodiment, memory management circuitry 202 can be set up spare area physical blocks table (not shown) and write down the physical blocks that is associated to the spare area at present.What deserves to be mentioned is that memory management circuitry 202 needs to use the storage space of more memory buffer 252 to come the storage administration parameter when opening mother and child blocks, to write down more detailed store status.For example, these management parameters valid data that can write down first logic section that belongs to logical block 510 (0) are stored in which physical page of physical blocks 304 (0) and physical blocks 304 (D+1) (as shown in Figure 9) dispersedly.Base this, during memory storage apparatus 100 running, the group number of mother and child blocks is limited.Therefore, when memory storage apparatus 100 receives when instruction of writing that comes from host computer system 1000, if having opened the group number of mother and child blocks reaches in limited time, memory management circuitry 202 need be closed at least one group of mother and child blocks of having opened at present (that is, the mother and child blocks running is closed in execution) and be write instruction to carry out this.

In the running of Fig. 8～shown in Figure 10, memory management circuitry 202 only needs the start first data input/output bus 356 to transmit data, and finishes the writing with valid data of physical blocks that belongs to first memory unit 302 and duplicate.Specifically, in the present embodiment, memory interface 206 is to be electrically connected to first memory unit 302 and second memory unit 312 via same wafer activation pin 352.When memory management circuitry 202 desires first memory unit 302 is assigned and to be write instruction and when assigning wafer activation instruction with activation first memory unit 302 via wafer activation pin 352, second memory unit 312 can be enabled simultaneously.At this moment, memory management circuitry 202 can only be assigned via first control bus 354 and write instruction and transmit data via the first data input/output bus 356.Because second control bus 364 and the second data input/output bus 366 can be by starts, though therefore second memory unit 312 can not carried out any running by the while activation.

Similarly, under Figure 11 A and mapping status shown in Figure 7, write instruction and when desiring to write data to the logic access address of second logic section that belongs to logical block 510 (1) when Memory Controller 104 receives from host computer system 1000, memory management circuitry 202 can be to map to physical blocks 314 (1) and extract physical blocks 314 (D+1) the physical blocks physical blocks 314 (1) of rotating as an alternative that belongs to second memory unit 312 from spare area 404 according to second logic section of second logic section-physical blocks mapping table 612 recognition logic unit 510 (1) at present.And after the mother and child blocks running was closed in execution, memory management circuitry 202 can remap logical block 510 (1) to 314 (D+1) (shown in Figure 11 B) in second logic section-physical blocks mapping table 612.And this writes in the process of instruction in execution, and memory management circuitry 202 only needs the start second data input/output bus 366 to transmit data, and finishes the writing with valid data of physical blocks that belongs to second memory unit 312 and duplicate.Same, in this process, memory management circuitry 202 can be assigned wafer activation instruction with activation second memory unit 312 via wafer activation pin 352, and first memory unit 302 also can be enabled simultaneously simultaneously.At this moment, memory management circuitry 202 can only be assigned via second control bus 364 and write instruction and transmit data via the second data input/output bus 366.Because first control bus 354 and the first data input/output bus 356 can be by starts, though therefore first memory unit 302 can not carried out any running by the while activation.

Particularly, all logical blocks-physical blocks mapping table (for example can be stored in memory module 106, the physical blocks that belongs to system region) in, and when needing access memory unit, corresponding logical block-physical blocks mapping table just can be loaded in the memory buffer 252 in order to reading and upgrading.

Though memory management circuitry 202 is to come diode-capacitor storage unit independently according to different data input/output bus.But a plurality of data input/output bus also can operate simultaneously, to promote the usefulness of memory storage apparatus 100.

For example, when receiving, Memory Controller 104 writes instruction and when desiring to write data to the logic access address of first logic section that belongs to logical block 510 (0) from host computer system 1000, memory management circuitry 202 can judge whether that needing to carry out in the physical blocks of first memory unit 302 valid data earlier duplicates (for example, the above-mentioned mother and child blocks of closing operates).Particularly, when memory management circuitry 202 judged that needing to carry out in the physical blocks of first memory unit 302 valid data earlier duplicates, memory management circuitry 202 can judge also that whether needing to carry out valid data in the physical blocks of second memory unit 312 duplicates.Duplicate if need to carry out valid data in the physical blocks of second memory unit 312, memory management circuitry 202 can be carried out synchronous operation, duplicates to carry out valid data in first memory unit 302 and second memory unit 312.

Specifically, in this synchronous operation, at first, memory management circuitry 202 can be via wafer activation pin 352 first memory of activation simultaneously unit 302 and second memory unit 312.Then, memory management circuitry 202 can be assigned first steering order via first control bus 354 and give first memory unit 302, assigns second steering order via second control bus 364 simultaneously and gives second memory unit 312.Afterwards, valid data duplicate and can be performed in first memory unit 302 and second memory unit 312 with the method for synchronization.For example, when the execution valid data duplicate, the valid data that belong to first memory unit 302 and second memory unit 312 respectively transfer to memory buffer 252 via the first data input/output bus 356 and the second data input/output bus 366 discriminably, and are written into corresponding physical page afterwards again.

Please refer to Figure 12, when receiving from host computer system 1000 when writing instruction and writing the data of instruction with corresponding this, memory management circuitry 202 can write logical block and the logic section that correspondence is discerned in logic access address that instruction comprises according to this in step S1201.And memory management circuitry 202 is written into corresponding logical block-physical blocks mapping table and related management parameter to discern corresponding memory cell and data input/output bus according to logical block of being discerned and logic section in step S1203.

Afterwards, memory management circuitry 202 need can judge whether elder generation's execution valid data between the physical blocks of the memory cell of correspondence to duplicate in step S1205.If when need not earlier between the physical blocks of the memory cell of correspondence, to carry out valid data and duplicating, then memory management circuitry 202 can be via wafer activation pin (promptly in step S1207, wafer activation pin 352) assigns wafer activation instruction, and assign steering order via the control bus of correspondence.Afterwards, memory management circuitry 202 only uses corresponding data input/output bus to transmit the data of desiring to write in step S1209.

If when judging that in step S1205 needing elder generation to carry out valid data between the physical blocks of the memory cell of correspondence duplicates, then memory management circuitry 202 can judge that whether need be performed valid data between the physical blocks of other memory cells duplicates in step S1211.

If in the time of also need being performed valid data duplicating between the physical blocks of other memory cells, then memory management circuitry 202 can be written into the logical block-physical blocks mapping table and the related management parameter of corresponding other memory cells in step S1213.Afterwards, memory management circuitry 202 can be assigned wafer activation instruction via wafer activation pin (that is wafer activation pin 352) in step S1215.Then, memory management circuitry 202 can be assigned steering order via different control buss respectively and duplicates synchronously to carry out valid data in a plurality of memory cells in step S1217, and step S1207 can be performed afterwards.

If when need not to be performed valid data duplicating between the physical blocks of other memory cells, then memory management circuitry 202 can be assigned wafer activation instruction via wafer activation pin (that is wafer activation pin 352) in step S1219.And memory management circuitry 202 can be assigned steering order via the control bus of correspondence and duplicates to carry out valid data in the memory cell of correspondence in step S1221, and step S1207 can be performed afterwards.

Second embodiment

The memory storage apparatus of second embodiment is the memory storage apparatus that is same as first embodiment in essence, below will partly describe at difference.

Please refer to Figure 13, memory storage apparatus 1300 comprises connector 102, Memory Controller 1304 and memory module 106.

Memory Controller 1304 can be carried out with hardware pattern or real a plurality of logic locks or the steering order of doing of firmware pattern, and carries out the runnings such as writing, read and erase of data in memory module 106 according to the instruction of host computer system 1000.Particularly, Memory Controller 1304 is in order to carry out data access mechanism and the memory management mechanism according to present embodiment.

Memory Controller 1304 comprises memory management circuitry 1302, host interface 204, memory interface 206, memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.

In the present embodiment, the first memory unit 302 of memory module 106 is to be electrically connected to memory interface 206 via the first wafer activation pin 1352, control bus 1354 and the first data input/output bus 1356.In addition, the second memory unit 312 of memory module 106 is to be electrically connected to memory interface 206 via the second wafer activation pin 1362, control bus 1354 and the second data input/output bus 1366.

Memory management circuitry 1302 is in order to the overall operation of control store controller 1304.Specifically, memory management circuitry 1302 has a plurality of steering orders, and when memory storage apparatus 1300 runnings, these steering orders can be performed with the data access mechanism according to present embodiment comes diode-capacitor storage module 106 with memory management mechanism.

In the present embodiment, memory management circuitry 1302 also can execution graph 4～Figure 10 and Figure 11 A and 11B shown in running come diode-capacitor storage module 106.But, because the electric connection mode of memory module 106 and Memory Controller 1304 is different from first embodiment, base this, memory management circuitry 1302 can be assigned instruction in a different manner to finish the running shown in Fig. 4～Figure 10 and Figure 11 A and Figure 11 B.

For example, in the running of execution graph 8～shown in Figure 10, memory management circuitry 1302 also only needs the start first data input/output bus 1356 to transmit data, and finishes the writing with valid data of physical blocks that belongs to first memory unit 302 and duplicate.But memory management circuitry 1302 is to assign first wafer activation instruction with activation first memory unit 302 via the first wafer activation pin 1352 earlier.Afterwards, memory management circuitry 1302 can be assigned steering order via control bus 1354.At this, memory interface 206 is to be electrically connected to first memory unit 302 and second memory unit 312 via same control bus 1354, and therefore the steering order of being assigned can be transferred to first memory unit 302 and second memory unit 312 simultaneously.Yet owing to second memory unit 312 is not enabled, so this steering order can be to the 312 generation effects of second memory unit.At this moment, memory management circuitry 1302 can be only transmitted data to finish the instruction that writes at the physical blocks of first memory unit 302 via the first data input/output bus 1356.

In addition, when above-mentioned synchronous operation was performed, at first, memory management circuitry 1302 can be assigned first wafer activation instruction and assign second wafer activation instruction via the second wafer activation pin 1362 via the first wafer activation pin 1352.Then, memory management circuitry 1302 can be assigned identical steering order via control bus 1354 and give first memory unit 302 and second memory unit 312.Afterwards, valid data duplicate and can be performed in first memory unit 302 and second memory unit 312 with the method for synchronization.For example, when the execution valid data duplicate, the valid data that belong to first memory unit 302 and second memory unit 312 respectively transfer to memory buffer 252 via the first data input/output bus 1356 and the second data input/output bus 1366 discriminably, and are written into corresponding physical page afterwards again.

Please refer to Figure 14, when receiving from host computer system 1000 when writing instruction and writing the data of instruction with corresponding this, memory management circuitry 1302 can write logical block and the logic section that correspondence is discerned in logic access address that instruction comprises according to this in step S1401.And memory management circuitry 1302 is written into corresponding logical block-physical blocks mapping table and related management parameter to discern corresponding memory cell and data input/output bus according to logical block of being discerned and logic section in step S1403.

Afterwards, memory management circuitry 1302 need can judge whether elder generation's execution valid data between the physical blocks of the memory cell of correspondence to duplicate in step S1405.If when need not earlier between the physical blocks of the memory cell of correspondence, to carry out valid data and duplicating, then memory management circuitry 1302 can be assigned wafer activation instruction via the wafer activation pin of correspondence in step S1407, and assign steering order via control bus (that is, control bus 1354).Afterwards, memory management circuitry 1302 only uses corresponding data input/output bus to transmit the data of desiring to write in step S1409.

If when judging that in step S1405 needing elder generation to carry out valid data between the physical blocks of the memory cell of correspondence duplicates, then memory management circuitry 1302 can judge that whether need be performed valid data between the physical blocks of other memory cells duplicates in step S1411.

If in the time of also need being performed valid data duplicating between the physical blocks of other memory cells, then memory management circuitry 1302 can be written into the logical block-physical blocks mapping table and the related management parameter of corresponding other memory cells in step S1413.Afterwards, then in step S1415 memory management circuitry 1302 can assign wafer activation instruction via different wafer activation pins respectively and need be performed the memory cell that valid data duplicate with activation.Then, memory management circuitry 1302 can be assigned same steering order via control bus (that is, control bus 1354) and duplicates synchronously to carry out valid data in a plurality of memory cells in step S1417, and step S1407 can be performed afterwards.

If when need not to be performed valid data duplicating between the physical blocks of other memory cells, then memory management circuitry 1302 can be assigned the memory cell of wafer activation instruction with corresponding this host command of activation via the wafer activation pin of correspondence in step S1419.And memory management circuitry 1302 can be assigned steering order via control bus (that is, control bus 1354) and duplicates to carry out valid data in the memory cell of correspondence in step S1421, and step S1407 can be performed afterwards.

The 3rd embodiment

The memory storage apparatus of the 3rd embodiment is the memory storage apparatus that is same as first embodiment in essence, below will partly describe at difference.

Please refer to Figure 15, memory storage apparatus 1500 comprises connector 102, Memory Controller 1504 and memory module 106.

Memory Controller 1504 can be carried out with hardware pattern or real a plurality of logic locks or the steering order of doing of firmware pattern, and carries out the runnings such as writing, read and erase of data in memory module 106 according to the instruction of host computer system 1000.Particularly, Memory Controller 1504 is in order to carry out data access mechanism and the memory management mechanism according to present embodiment.

Memory Controller 1504 comprises memory management circuitry 1502, host interface 204, memory interface 206, memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.

In the present embodiment, the first memory unit 302 of memory module 106 is to be electrically connected to memory interface 206 via wafer activation pin 1552, control bus 1554 and the first data input/output bus 1556.In addition, the second memory unit 312 of memory module 106 is to be electrically connected to memory interface 206 via wafer activation pin 1552, control bus 1554 and the second data input/output bus 1566.

Memory management circuitry 1502 is in order to the overall operation of control store controller 1504.Specifically, memory management circuitry 1502 has a plurality of steering orders, and when memory storage apparatus 1500 runnings, these steering orders can be performed with the data access mechanism according to present embodiment comes diode-capacitor storage module 106 with memory management mechanism.

In the present embodiment, memory management circuitry 1502 also can execution graph 4～Figure 10 and Figure 11 A and Figure 11 B shown in running come diode-capacitor storage module 106.But, because the electric connection mode of memory module 106 and Memory Controller 1504 is different from first embodiment, base this, memory management circuitry 1502 can be assigned instruction in a different manner to finish the running shown in Fig. 4～Figure 10 and Figure 11 A and Figure 11 B.

For example, in the running of execution graph 8～shown in Figure 10, memory management circuitry 1502 also only needs the start first data input/output bus 1556 to transmit data, and finishes the writing with valid data of physical blocks that belongs to first memory unit 302 and duplicate.But memory management circuitry 1502 is to assign wafer activation instruction with activation first memory unit 302 via wafer activation pin 1552 earlier.At this moment, this wafer activation instruction also can activation second memory unit 312.Afterwards, memory management circuitry 1502 can be assigned steering order via control bus 1554.At this moment, this steering order also can be sent to second memory unit 312.Then, memory management circuitry 1502 can be transmitted data finishing the instruction that writes at the physical blocks of first memory unit 302 via the first data input/output bus 1556, and transmits empty data so that the second memory unit is carried out invalid writing via the second data input/output bus 1566.In the present embodiment, empty data can be one and are all " 1 " data stream, maybe can allow memory management circuitry 1502 regard as insignificant Data Styles.

In addition, when above-mentioned synchronous operation was performed, at first, memory management circuitry 1502 can be assigned wafer activation instruction with while activation first memory unit 302 and second memory unit 312 via wafer activation pin 1552.Then, memory management circuitry 1502 can be assigned same steering order via control bus 1554 and give first memory unit 302 and second memory unit 312.Afterwards, valid data duplicate and can be performed in first memory unit 302 and second memory unit 312 with the method for synchronization.For example, when the execution valid data duplicate, the valid data that belong to first memory unit 302 and second memory unit 312 respectively transfer to memory buffer 252 via the first data input/output bus 1556 and the second data input/output bus 1566 discriminably, and are written into corresponding physical page afterwards again.

Please refer to Figure 16, when receiving from host computer system 1000 when writing instruction and writing the data of instruction with corresponding this, memory management circuitry 1502 can write logical block and the logic section that correspondence is discerned in logic access address that instruction comprises according to this in step S1601.And memory management circuitry 1502 is written into corresponding logical block-physical blocks mapping table and related management parameter to discern corresponding memory cell and data input/output bus according to logical block of being discerned and logic section in step S1603.

Afterwards, memory management circuitry 1502 need can judge whether elder generation's execution valid data between the physical blocks of the memory cell of correspondence to duplicate in step S1605.If when need not earlier between the physical blocks of the memory cell of correspondence, to carry out valid data and duplicating, then memory management circuitry 1502 can be via wafer activation pin (promptly in step S1607, wafer activation pin position 1552) assigns wafer activation instruction, Bing and assign steering order via control bus (that is, control bus 1554).Afterwards, memory management circuitry 1502 only uses corresponding data input/output bus to transmit the data of desiring to write in step S1609, and transmits empty data to carry out invalid writing in other data input/output bus.

If when judging that in step S1605 needing elder generation to carry out valid data between the physical blocks of the memory cell of correspondence duplicates, then memory management circuitry 1502 can judge that whether need be performed valid data between the physical blocks of other memory cells duplicates in step S1611.

If in the time of also need being performed valid data duplicating between the physical blocks of other memory cells, then memory management circuitry 1502 can be written into the logical block-physical blocks mapping table and the related management parameter of corresponding other memory cells in step S1613.Afterwards, memory management circuitry 1502 can be assigned wafer activation instruction via wafer activation pin (that is, wafer activation pin position 1552) in step S1615.But after, memory management circuitry 1502 can be assigned steering order via control bus (that is, control bus 1554) and duplicates synchronously to carry out valid data in a plurality of memory cells in step S1617, and step S1607 can be performed afterwards.

If when need not to be performed valid data duplicating between the physical blocks of other memory cells, then memory management circuitry 1502 can be assigned wafer activation instruction via wafer activation pin (that is, wafer activation pin position 1552) in step S1619.And, memory management circuitry 1502 can be via control bus (promptly in step S1621, control bus 1554) assign steering order and duplicate and in other memory cells, carry out invalid access, and step S1607 can be performed afterwards with execution valid data in the memory cell of correspondence.

The 4th embodiment

The memory storage apparatus of the 4th embodiment is the memory storage apparatus that is same as first embodiment in essence, below will partly describe at difference.

Please refer to Figure 17, memory storage apparatus 1700 comprises connector 102, Memory Controller 1704 and memory module 106.

Memory Controller 1704 can be carried out with hardware pattern or real a plurality of logic locks or the steering order of doing of firmware pattern, and carries out the runnings such as writing, read and erase of data in memory module 106 according to the instruction of host computer system 1000.Particularly, Memory Controller 1704 is in order to carry out data access mechanism and the memory management mechanism according to present embodiment.

Memory Controller 1704 comprises memory management circuitry 1702, host interface 204, memory interface 206, memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.

In the present embodiment, the first memory unit 302 of memory module 106 is to be electrically connected to memory interface 206 via the first wafer activation pin 1752, first control bus 1754 and the first data input/output bus 1756.In addition, the second memory unit 312 of memory module 106 is to be electrically connected to memory interface 206 via the second wafer activation pin 1762, second control bus 1764 and the second data input/output bus 1766.

Memory management circuitry 1702 is in order to the overall operation of control store controller 1704.Specifically, memory management circuitry 1702 has a plurality of steering orders, and when memory storage apparatus 1700 runnings, these steering orders can be performed with the data access mechanism according to present embodiment comes diode-capacitor storage module 106 with memory management mechanism.

In the present embodiment, memory management circuitry 1702 also can execution graph 4～Figure 10 and Figure 11 A and Figure 11 B shown in running come diode-capacitor storage module 106.But, because the electric connection mode of memory module 106 and Memory Controller 1704 is different from first embodiment, base this, memory management circuitry 1702 can be assigned instruction in a different manner to finish the running shown in Fig. 4～Figure 10 and Figure 11 A and Figure 11 B.

For example, in the running of execution graph 8～shown in Figure 10, memory management circuitry 1702 also only needs the start first data input/output bus 1756 to transmit data, and finishes the writing with valid data of physical blocks that belongs to first memory unit 302 and duplicate.But memory management circuitry 1702 is to assign first wafer activation instruction with activation first memory unit 302 via the first wafer activation pin 1752 earlier.Afterwards, memory management circuitry 1702 can be assigned steering order via first control bus 1754.At this moment, memory management circuitry 1702 can be only transmitted data to finish the instruction that writes at the physical blocks of first memory unit 302 via the first data input/output bus 1756.

In addition, when above-mentioned synchronous operation was performed, at first, memory management circuitry 1702 can be assigned first wafer activation instruction and assign second wafer activation instruction via the second wafer activation pin 1762 via the first wafer activation pin 1752.Then, memory management circuitry 1702 can be assigned steering order to first memory unit 302 and via second control bus 1764 and second memory unit 312 via first control bus 1754.Afterwards, valid data duplicate and can be performed in first memory unit 302 and second memory unit 312 with the method for synchronization.For example, when the execution valid data duplicate, the valid data that belong to first memory unit 302 and second memory unit 312 respectively transfer to memory buffer 252 via the first data input/output bus 1756 and the second data input/output bus 1766 discriminably, and are written into corresponding physical page afterwards again.

Please refer to Figure 18, when receiving from host computer system 1000 when writing instruction and writing the data of instruction with corresponding this, memory management circuitry 1702 can write logical block and the logic section that correspondence is discerned in logic access address that instruction comprises according to this in step S1801.And memory management circuitry 1702 is written into corresponding logical block-physical blocks mapping table and related management parameter to discern corresponding memory cell and data input/output bus according to logical block of being discerned and logic section in step S1803.

Afterwards, memory management circuitry 1702 need can judge whether elder generation's execution valid data between the physical blocks of the memory cell of correspondence to duplicate in step S1805.If when need not earlier between the physical blocks of the memory cell of correspondence, to carry out valid data and duplicating, then memory management circuitry 1702 can be assigned wafer activation instruction via the wafer activation pin of correspondence in step S1807, and assigns steering order via the control bus of correspondence.Afterwards, memory management circuitry 1702 only uses corresponding data input/output bus to transmit the data of desiring to write in step S1809.

If when judging that in step S1805 needing elder generation to carry out valid data between the physical blocks of the memory cell of correspondence duplicates, then memory management circuitry 1702 can judge that whether need be performed valid data between the physical blocks of other memory cells duplicates in step S1811.

If in the time of also need being performed valid data duplicating between the physical blocks of other memory cells, then memory management circuitry 1702 can be written into the logical block-physical blocks mapping table and the related management parameter of corresponding other memory cells in step S1813.Afterwards, memory management circuitry 1702 can be assigned wafer activation instruction via different wafer activation pins respectively and need be performed the memory cell that valid data duplicate with activation in step S1815.Then, memory management circuitry 1702 can be assigned steering order via different control buss respectively and duplicates synchronously to carry out valid data in a plurality of memory cells in step S1817, and step S1807 can be performed afterwards.

If when need not to be performed valid data duplicating between the physical blocks of other memory cells, then memory management circuitry 1702 can be assigned the memory cell of wafer activation instruction with corresponding this host command of activation via the wafer activation pin of correspondence in step S1819.And memory management circuitry 1702 can be assigned steering order via the control bus of correspondence and duplicates to carry out valid data in the memory cell of correspondence in step S1821, and step S1807 can be performed afterwards.

In sum, the embodiment of the invention is to come the configuration mapping table and management parameter of management entity block Bing correspondence according to the data input/output bus.Therefore, a plurality of physical blocks that map to same logical block can operate independently, can shorten thus and carry out the above-mentioned time of duplicating valid data, promote the usefulness of memory storage.In addition, physical page is performed the above-mentioned number of times that duplicates valid data and can significantly reduces, and prolongs the life-span of memory storage thus.

Though the present invention discloses as above with embodiment; but it is not in order to qualification the present invention, any affiliated those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim person of defining.

Claims

1. memory management and wiring method, be used to manage a memory module, wherein said memory module comprises a first memory unit, be used for one first input/output bus of described first memory unit, a second memory unit and be used for one second input/output bus of described second memory unit, described first memory unit and described second memory unit have a plurality of physical blocks, and described memory management and wiring method comprise:

Dispose a plurality of logical blocks, and each logical block is divided into one first logic section of corresponding described first input/output bus and one second logic section of corresponding described second input/output bus;

With described a plurality of logical unit mappings at least a portion to described a plurality of physical blocks of described first memory unit and described second memory unit, wherein described first logic section of each logical block described second logic section of one of them and each logical block of shining upon described a plurality of physical blocks of described first memory unit is shone upon one of them of described a plurality of physical blocks of described second memory unit;

One first mapping table of setting up corresponding described first input/output bus is with one first mapping relations between described a plurality of physical blocks of described a plurality of first logic section that write down described a plurality of logical blocks and described first memory unit;

One second mapping table of setting up corresponding described second input/output bus is with one second mapping relations between described a plurality of physical blocks of described a plurality of second logic section that write down described a plurality of logical blocks and described second memory unit;

Receive one and write the data that instruction and corresponding said write are instructed, wherein said data desire to be written into one of them of described a plurality of first logic section of described a plurality of logical blocks; And

Described first mapping table according to corresponding described first input/output bus only uses described first input/output bus to write in the described first memory unit with the data with corresponding said write instruction.

2. memory management according to claim 1 and wiring method, wherein described first mapping table according to corresponding described first input/output bus only uses described first input/output bus to comprise with the step that the data with corresponding said write instruction write in the described first memory unit:

Assign a wafer activation instruction, wherein said wafer activation instruction is activation described first memory unit and described second memory unit simultaneously;

Assign one first steering order and give described first memory unit; And

Described first mapping table according to corresponding described first input/output bus writes in the described first memory unit with the data with corresponding said write instruction via described first input/output bus.

3. memory management according to claim 1 and wiring method also comprise:

Need to judge whether copy data between described a plurality of physical blocks of described first memory unit;

If when needing between described a plurality of physical blocks of described first memory unit copy data, need then to judge whether copy data between described a plurality of physical blocks of described second memory unit; And

If when needing between described a plurality of physical blocks of described second memory unit copy data, then carry out a synchronous operation procedure, described synchronous operation program comprises:

Assigning one first steering order according to described first mapping table gives described first memory unit with copy data between described a plurality of physical blocks of described first memory unit; And

Assigning one second steering order according to described second mapping table gives described second memory unit with copy data between described a plurality of physical blocks of described second memory unit.

4. memory management according to claim 3 and wiring method also comprise:

If when need not between described a plurality of physical blocks of described second memory unit copy data, then assign described wafer activation instruction, and assign described first steering order according to described first mapping table and give described first memory unit with copy data between described a plurality of physical blocks of described first memory unit.

5. memory management according to claim 1 and wiring method, wherein described first mapping table according to corresponding described first input/output bus only uses described first input/output bus to comprise with the step that the data with corresponding said write instruction write in the described first memory unit:

Assigning one first wafer activation instructs to described first memory unit;

Assign a steering order, wherein said steering order is sent to described first memory unit and described second memory unit simultaneously; And

6. memory management according to claim 1 and wiring method also comprise:

Assigning one first wafer activation instructs to described first memory unit;

Assigning one second wafer activation instructs to described second memory unit; And

Assign a steering order with copy data between described a plurality of physical blocks of between described a plurality of physical blocks of described first memory unit and described second memory unit according to described first mapping table and described second mapping table, wherein said steering order is sent to described first memory unit and described second memory unit simultaneously.

7. memory management according to claim 6 and wiring method also comprise:

If when need not between described a plurality of physical blocks of described second memory unit copy data, then assign the described first wafer activation and instruct, and assign described steering order according to described first mapping table and give described first memory unit with copy data between described a plurality of physical blocks of described first memory unit to described first memory unit.

8. memory management according to claim 1 and wiring method, wherein described first mapping table according to corresponding described first input/output bus only uses described first input/output bus to comprise with the step that the data with corresponding said write instruction write in the described first memory unit:

Described first mapping table according to corresponding described first input/output bus writes in the described first memory unit with the data with corresponding said write instruction via described first input/output bus, and has transmitted data and given described second memory unit to carry out invalid writing.

9. memory management according to claim 1 and wiring method also comprise:

Assign a wafer activation instruction, wherein said wafer activation instruction is activation described first memory unit and described second memory unit simultaneously; And

10. memory management according to claim 9 and wiring method also comprise:

If when need not between described a plurality of physical blocks of described second memory unit copy data, then assign described wafer activation instruction, and assign described steering order to carry out an invalid access at copy data between described a plurality of physical blocks of described first memory unit and in described second memory unit according to described first mapping table.

11. memory management according to claim 1 and wiring method, wherein described first mapping table according to corresponding described first input/output bus only uses described first input/output bus to comprise with the step that the data with corresponding said write instruction write in the described first memory unit:

Assigning one first wafer activation instructs to described first memory unit;

Assign one first steering order and give described first memory unit; And

12. memory management according to claim 1 and wiring method also comprise:

Assigning one first wafer activation instructs to described first memory unit;

Assigning one second wafer activation instructs to described second memory unit;

13. memory management according to claim 12 and wiring method also comprise:

If when need not between described a plurality of physical blocks of described second memory unit copy data, then assign the described first wafer activation and instruct, and assign described first steering order according to described first mapping table and give described first memory unit with copy data between described a plurality of physical blocks of described first memory unit to described first memory unit.

14. Memory Controller, be used to manage a memory module, wherein said memory module comprises a first memory unit, one first input/output bus that is used for described first memory unit, one second memory unit and one second input/output bus that is used for described second memory unit, described first memory unit and described second memory unit have a plurality of physical blocks, described a plurality of physical blocks has a plurality of physical page respectively, and described a plurality of physical page of each physical blocks can be written into and side by side be erased independently, and described Memory Controller comprises:

One host interface is in order to be electrically connected to a host computer system;

One memory interface is in order to be electrically connected to described duplicative nonvolatile memory module; And

One memory management circuitry is electrically connected to described host interface and described memory interface, and wherein said memory management circuitry is in order to carry out follow procedure at least:

15. Memory Controller according to claim 14,

Wherein said memory interface is electrically connected to described first memory unit and described second memory unit simultaneously via a wafer activation pin, be electrically connected to described first memory unit via one first control bus, and be electrically connected to described second memory unit via one second control bus

Also in order to assign a wafer activation instruction via described wafer activation pin, described wafer activation instruction is activation described first memory unit and described second memory unit simultaneously for wherein said memory management circuitry, and

Described memory management circuitry is also given described first memory unit in order to assign one first steering order via described first control bus.

16. Memory Controller according to claim 14,

Wherein said memory interface is electrically connected to described first memory unit via one first wafer activation pin, be electrically connected to described second memory unit via one second wafer activation pin, and be electrically connected to described first memory unit and described first memory unit simultaneously via a control bus

Wherein said memory management circuitry is also instructed to described first memory unit in order to assign one first wafer activation via the described first wafer activation pin, and assign a steering order via described controller bus, wherein said steering order is sent to described first memory unit and described second memory unit simultaneously.

17. Memory Controller according to claim 14,

Wherein said memory interface is electrically connected to described first memory unit and described second memory unit simultaneously via a wafer activation pin, and be electrically connected to described first memory unit and described first memory unit simultaneously via a control bus

Also in order to assign a wafer activation instruction via described wafer activation pin, described wafer activation instruction is activation described first memory unit and described second memory unit simultaneously for wherein said memory management circuitry,

Described memory management circuitry is also assigned a steering order in order to described control bus, and wherein said steering order is sent to described first memory unit and described second memory unit simultaneously,

Described memory management circuitry also gives described second memory unit to carry out invalid writing in order to have transmitted data.

18. Memory Controller according to claim 14,

Wherein said memory interface is electrically connected to described first memory unit and described second memory unit simultaneously via a wafer activation pin, and be electrically connected to described first memory unit and described second memory unit simultaneously via a control bus

Wherein said memory management circuitry is also in order to carry out follow procedure:

Assign a wafer activation instruction via described wafer activation pin, wherein said wafer activation instruction is activation described first memory unit and described second memory unit simultaneously; And

Assign a steering order to reach copy data between described a plurality of physical blocks of described second memory unit between described a plurality of physical blocks of described first memory unit according to described first mapping table and described second mapping table via described control bus, wherein said steering order is sent to described first memory unit and described second memory unit simultaneously.

19. Memory Controller according to claim 14,

Wherein said memory interface is electrically connected to described first memory unit via one first wafer activation pin, be electrically connected to described second memory unit via one second wafer activation pin, be electrically connected to described first memory unit via one first control bus, and be electrically connected to described second memory unit via one second control bus

Wherein said memory management circuitry is also instructed to described first memory unit in order to assign one first wafer activation via the described first wafer activation pin, and assigns one first steering order via described first control bus and give described first memory unit.

20. Memory Controller according to claim 14,

Wherein said memory interface is electrically connected to described first memory unit via one first wafer activation pin, be electrically connected to described second memory unit via one second wafer activation pin, be electrically connected to described first memory unit via one first control bus, and be electrically connected to described first memory unit via one second control bus

Assigning one first wafer activation via the described first wafer activation pin instructs to described first memory unit;

Assigning one second wafer activation via the described second wafer activation pin instructs to described second memory unit;

Assigning one first steering order according to described first mapping table via described first control bus gives described first memory unit with copy data between described a plurality of physical blocks of described first memory unit; And

Assigning one second steering order according to described second mapping table via described second control bus gives described second memory unit with copy data between described a plurality of physical blocks of described second memory unit.

21. a storage system comprises:

A connector;

One memory module, comprise a first memory unit, be used for one first input/output bus, a second memory unit of described first memory unit and be used for one second input/output bus of described second memory unit, described first memory unit and described second memory unit have a plurality of physical blocks, described a plurality of physical blocks has a plurality of physical page respectively, and described a plurality of physical page of each physical blocks can be written into and side by side be erased independently; And

One Memory Controller is electrically connected to described memory module and described connector, in order to carry out follow procedure at least:

22. storage system according to claim 21,

Wherein said Memory Controller is electrically connected to described first memory unit and described second memory unit simultaneously via a wafer activation pin, be electrically connected to described first memory unit via one first control bus, and be electrically connected to described second memory unit via one second control bus

Also in order to assign a wafer activation instruction via described wafer activation pin, described wafer activation instruction is activation described first memory unit and described second memory unit simultaneously for wherein said Memory Controller, and

Described Memory Controller is also given described first memory unit in order to assign one first steering order via described first control bus.

23. storage system according to claim 21,

Wherein said Memory Controller is also in order to carry out follow procedure:

Assign a wafer activation instruction via described wafer activation pin, wherein said wafer activation instruction is activation described first memory unit and described second memory unit simultaneously;

24. storage system according to claim 23, if when wherein need not between described a plurality of physical blocks of described second memory unit copy data, described Memory Controller also instructs in order to assign described wafer activation via described wafer activation pin, and assigns described first steering order according to described first mapping table via described first control bus and give described first memory unit with copy data between described a plurality of physical blocks of described first memory unit.

25. storage system according to claim 21,

Wherein said Memory Controller is electrically connected to described first memory unit via one first wafer activation pin, be electrically connected to described second memory unit via one second wafer activation pin, and be electrically connected to described first memory unit and described second memory unit simultaneously via a control bus

Wherein said Memory Controller also instructs to described first memory unit in order to assign one first wafer activation via the described first wafer activation pin, and assign a steering order via described control bus, wherein said steering order is sent to described first memory unit and described second memory unit simultaneously.

26. storage system according to claim 21,

Wherein said Memory Controller is also in order to carry out follow procedure:

Assigning one second wafer activation via the described second wafer activation pin instructs to described second memory unit; And

According to described first mapping table and described second mapping table via described control bus assign a steering order with copy data between described a plurality of physical blocks of described first memory unit and between described a plurality of physical blocks of described second memory unit copy data, wherein said steering order is sent to described first memory unit and this second memory unit simultaneously.

27. storage system according to claim 21,

Wherein said Memory Controller is electrically connected to described first memory unit and described second memory unit simultaneously via a wafer activation pin, and be electrically connected to described first memory unit and described second memory unit simultaneously via a control bus

Also in order to assign a wafer activation instruction via described wafer activation pin, described wafer activation instruction is activation described first memory unit and described second memory unit simultaneously for wherein said Memory Controller,

Also in order to assign a steering order via described control bus, wherein said steering order is sent to described first memory unit and described second memory unit to described Memory Controller simultaneously,

Described Memory Controller also gives described second memory unit to carry out invalid writing in order to have transmitted data.

28. storage system according to claim 21,

Wherein said Memory Controller is also in order to carry out follow procedure:

29. storage system according to claim 21,

Wherein said Memory Controller is electrically connected to described first memory unit via one first wafer activation pin, be electrically connected to described second memory unit via one second wafer activation pin, be electrically connected to described first memory unit via one first control bus, and be electrically connected to described second memory unit via one second control bus

Wherein said Memory Controller also instructs to described first memory unit in order to assign one first wafer activation via the described first wafer activation pin, and assigns one first steering order via described first control bus and give described first memory unit.

30. storage system according to claim 21,

Wherein said Memory Controller is also in order to carry out follow procedure:

If when needing between described a plurality of physical blocks of described second memory unit copy data, then carry out a synchronous operation procedure, this synchronous operation program comprises: